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    • 83. 发明授权
      US6124608A Non-volatile trench semiconductor device having a shallow drain region 失效
    • Non-volatile trench semiconductor device having a shallow drain region
    • 具有浅漏区的非易失性沟槽半导体器件
    • US6124608A
    • 2000-09-26
    • US992961
    • 1997-12-18
    • Yowjuang William Liu , Yu Sun , Donald L. Wollesen
    • Yowjuang William Liu , Yu Sun , Donald L. Wollesen
    • H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/788
    • H01L27/11521 , H01L27/115 , H01L29/42336 , H01L29/7883
    • A non-volatile memory device having a trench structure and a shallow drain region is formed in a substrate, thereby facilitating increased densification, improved planarization and low power programming and erasing. Embodiments include forming first and second trenches in a substrate and, in each trench, sequentially forming a substantially U-shaped tunnel dielectric layer and a substantially U-shaped floating gate electrode. A dielectric layer is then formed on the floating gate electrode extending on the substrate surface and a substantially T-shaped control gate electrode is formed filling the trench and extending on the substrate. Sidewall spacers are formed on side surfaces of the control gate electrode and dielectric layer, followed by ion implantation to form a shallow drain region between the first and second trenches and source regions extending to a greater depth than the drain region. During ion implantation, a region containing an impurity of the first conductivity type is formed at the intersection of each trench and the substrate surface to prevent shorting between the source/drain region and gate electrodes.
    • 在衬底中形成具有沟槽结构和浅漏区的非易失性存储器件，从而有助于增加致密化，改进的平面化和低功率编程和擦除。 实施例包括在衬底中形成第一和第二沟槽，并且在每个沟槽中顺序地形成基本上U形的隧道介电层和基本上U形的浮置栅电极。 然后在衬底表面上延伸的浮栅上形成电介质层，并且形成填充沟槽并在衬底上延伸的大致T形的控制栅电极。 侧壁间隔件形成在控制栅电极和电介质层的侧表面上，然后进行离子注入，以在第一和第二沟槽之间形成浅漏极区域，并且源极区域延伸到比漏极区域更深的深度。 在离子注入期间，在每个沟槽和衬底表面的交叉处形成含有第一导电类型的杂质的区域，以防止源极/漏极区域和栅电极之间的短路。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 84. 发明授权
      US06004862A Core array and periphery isolation technique 失效
    • Core array and periphery isolation technique
    • 核心阵列和外围隔离技术
    • US06004862A
    • 1999-12-21
    • US8320
    • 1998-01-20
    • Unsoon Kim , Hung-Sheng Chen , Kashmir Sahota , Yu Sun
    • Unsoon Kim , Hung-Sheng Chen , Kashmir Sahota , Yu Sun
    • H01L21/762 , H01L21/76
    • H01L21/76202 , H01L21/76224
    • A process for forming a semiconductor integrated circuit with a core area densely populated with active devices and with a periphery area less densely populated with active devices as compared to the core area, comprising the steps of: forming a first layer of first insulator material above a semiconductor substrate having a core area and a periphery area, wherein the first insulator material constitutes a polish stop for polishing processes and also as an oxidation barrier; patterning the first layer of first insulator material to expose first portions of the semiconductor substrate substantially only in the core area while using the first insulator material to substantially mask the periphery area; forming a plurality of trenches into the exposed first portions of semiconductor substrate in the core area; filling the plurality of trenches with an insulator; polishing down to the first layer of first insulator material; removing the first layer of first insulator material; forming a second layer of first insulator material over the core and periphery areas; forming openings down into the second layer of first insulator material to expose second portions of the semiconductor substrate substantially only in the periphery area while using the second layer to substantially mask the core area; and forming an isolation region in the exposed second portions of the semiconductor substrate.
    • 一种用于形成半导体集成电路的方法，所述半导体集成电路具有密集地填充有有源器件的核心区域，并且与所述核心区域相比具有较少密集地填充有源器件的外围区域，包括以下步骤：在第一绝缘体材料的上方形成第一层 具有芯区域和周边区域的半导体衬底，其中所述第一绝缘体材料构成用于抛光工艺的抛光止挡件以及氧化屏障; 图案化第一绝缘体材料层，以在使用第一绝缘体材料基本上遮蔽周边区域的同时，在半导体衬底的基本上仅在芯部区域露出第一部分; 在芯区域中的半导体衬底的暴露的第一部分中形成多个沟槽; 用绝缘体填充多个沟槽; 抛光到第一绝缘体材料层; 去除第一绝缘体材料的第一层; 在所述芯和外围区域上形成第二绝缘体材料层; 将第一绝缘体材料的第二层向下形成开口，以便在使用第二层基本上掩蔽核心区域时，基本上只在周边区域露出半导体衬底的第二部分; 以及在半导体衬底的暴露的第二部分中形成隔离区。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 85. 发明授权
      US5925909A Three-dimensional complementary field effect transistor process and structures 失效
    • Three-dimensional complementary field effect transistor process and structures
    • 三维互补场效应晶体管工艺及结构
    • US5925909A
    • 1999-07-20
    • US555556
    • 1995-11-08
    • Yowjuang W. Liu , Yu Sun
    • Yowjuang W. Liu , Yu Sun
    • H01L21/8234 , H01L21/8238 , H01L27/088 , H01L27/092 , H01L29/423 , H01L29/78 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113
    • H01L29/7834 , H01L21/823487 , H01L21/823885 , H01L27/088 , H01L27/0922 , H01L29/4238 , Y10S148/05
    • A field effect transistor has a short gate and is fabricated by: doping the bottom surface of a depression to form a relatively lightly doped region in the bottom of the depression; forming the gate of the field effect transistor on the sidewall of the depression such that the gate is insulated from the sidewall by a thin insulating layer; and implanting dopants to form the drain region and the source region of the transistor using the gate to mask a part of the relatively lightly doped region. The part of the relatively lightly doped region which is masked by the gate during implanting of the source and drain regions constitutes a lightly doped drain region of the transistor. The drain of the transistor is formed into the bottom of the depression. The length of the gate is primarily determined by the depth and/or profile of the sidewall. The source-to-drain on-resistance of the transistor is low because the transistor does not have a lightly doped source region. The transistor has high quality gate oxide because the sidewall of the depression upon which the gate oxide is grown is substantially free of ion impact damage.
    • 场效应晶体管具有短栅极，并且通过以下方式制造：掺杂凹陷的底表面以在凹陷的底部形成相对轻掺杂的区域; 在凹陷的侧壁上形成场效应晶体管的栅极，使得栅极通过薄绝缘层与侧壁绝缘; 以及使用所述栅极注入掺杂剂以形成所述晶体管的漏极区域和源极区域以掩蔽所述相对轻掺杂区域的一部分。 在注入源极和漏极区域期间被栅极掩蔽的相对轻掺杂区域的部分构成晶体管的轻掺杂漏极区。 晶体管的漏极形成凹陷的底部。 栅极的长度主要由侧壁的深度和/或轮廓确定。 晶体管的源极到漏极导通电阻很低，因为晶体管不具有轻掺杂的源极区域。 晶体管具有高质量的栅极氧化物，因为其上生长栅极氧化物的凹陷的侧壁基本上没有离子冲击损伤。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
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