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81. 发明申请

US20100269081A1 Standard Cells Having Flexible Layout Architecture/Boundaries 有权
标题翻译：具有灵活布局架构/边界的标准单元
公开(公告)号：US20100269081A1
公开(公告)日：2010-10-21
申请号：US12697887
申请日：2010-02-01
申请人： Yung-Chin Hou , David Barry Scott , Lee-Chung Lu , Li-Chun Tien
发明人： Yung-Chin Hou , David Barry Scott , Lee-Chung Lu , Li-Chun Tien
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： An integrated circuit layout includes a standard cell, which includes a first gate strip and a second gate strip parallel to each other and having a gate pitch; a first boundary and a second boundary on opposite ends of the first standard cell; and a third boundary and a fourth boundary on opposite ends of the first standard cell and parallel to the first gate strip and the second gate strip. A cell pitch between the third boundary and the fourth boundary is not equal to integer times the gate pitch. A PMOS transistor is formed of the first gate strip and a first active region. An NMOS transistor is formed of the first gate strip and a second active region.
摘要翻译：集成电路布局包括标准单元，其包括彼此平行并具有栅极间距的第一栅极条和第二栅极条; 在第一标准单元的相对端上的第一边界和第二边界; 以及在第一标准单元的相对端上并且平行于第一栅极条和第二栅极条的第三边界和第四边界。第三边界和第四边界之间的单元间距不等于门间距的整数倍。 PMOS晶体管由第一栅极条和第一有源区形成。 NMOS晶体管由第一栅极条和第二有源区形成。

82. 发明申请

US20100174933A1 System and Method for Reducing Processor Power Consumption 有权
标题翻译：降低处理器功耗的系统和方法
公开(公告)号：US20100174933A1
公开(公告)日：2010-07-08
申请号：US12619428
申请日：2009-11-16
申请人： Lee-Chung Lu , Chung-Hsing Wang , Myron Shak , Wei-Pin Changchien , Kuo-Yin Chen , Chi Wei Hu , Kevin Hung , Wu-An Kuo
发明人： Lee-Chung Lu , Chung-Hsing Wang , Myron Shak , Wei-Pin Changchien , Kuo-Yin Chen , Chi Wei Hu , Kevin Hung , Wu-An Kuo
IPC分类号： G06F1/00
CPC分类号： G06F1/3287 , G06F1/3203 , G06F1/3237 , Y02D10/128 , Y02D10/171 , Y02D50/20
摘要： A system and method for reducing active power in processors is disclosed. A method embodiment comprises the steps of determining when a particular logic block is inactive, determining the powered state of the particular logic block, isolating the particular logic block from a main processor core, and powering off the particular logic block. When the system needs the particular logic block, the method further comprises reactivating the block. A system embodiment comprises software and a processor coupled to a clock control module, an isolation control module and a header/footer module, operable to isolate a particular logic block and power off a particular logic block, thereby reducing power. Another embodiment comprises a logic module coupled to a clock by a clock gating module, an isolation module for isolating the logic module, a header/footer module for disabling power to the logic module, and a power and clock gating control module for controlling the clock gating module and the header/footer module.
摘要翻译：公开了一种用于减少处理器中的有功功率的系统和方法。方法实施例包括以下步骤：确定特定逻辑块何时不活动，确定特定逻辑块的供电状态，将特定逻辑块与主处理器内核隔离，以及断开特定逻辑块。当系统需要特定逻辑块时，该方法还包括重新激活该块。系统实施例包括耦合到时钟控制模块，隔离控制模块和报头/页脚模块的软件和处理器，其可操作以隔离特定逻辑块并关闭特定逻辑块，从而降低功率。另一个实施例包括通过时钟门控模块耦合到时钟的逻辑模块，用于隔离逻辑模块的隔离模块，用于禁止对逻辑模块供电的报头/页脚模块，以及用于控制时钟的电源和时钟门控控制模块门控模块和页眉/页脚模块。

83. 发明授权

US07458051B2 ECO cell for reducing leakage power 有权
标题翻译： ECO电池用于减少泄漏电力
公开(公告)号：US07458051B2
公开(公告)日：2008-11-25
申请号：US11281035
申请日：2005-11-17
申请人： Yung-Chin Hou , Lee-Chung Lu , Chu-Ping Wang , Li-Chun Tien
发明人： Yung-Chin Hou , Lee-Chung Lu , Chu-Ping Wang , Li-Chun Tien
IPC分类号： G06F17/50
CPC分类号： G11C5/063 , H01L27/0207
摘要： A semiconductor structure including at least one spare cell is disclosed. The semiconductor structure includes a first conductive line coupled to a power supply, and a second conductive line coupled to a complementary power supply. At least one spare cell is decoupled from the first or second conductive line for being selectively connected to at least one normally functioning electronic components, the first conductive line and the second conductive line only during a rerouting process for reducing leakage power of the semiconductor structure.
摘要翻译：公开了包括至少一个备用单元的半导体结构。半导体结构包括耦合到电源的第一导线和耦合到互补电源的第二导线。至少一个备用单元与第一或第二导线分离，以便仅在用于减小半导体结构的泄漏功率的重新路由过程中选择性地连接到至少一个正常工作的电子部件，第一导线和第二导线。

84. 发明申请

US20080115024A1 System and method for testing state retention circuits 有权
标题翻译：用于测试状态保持电路的系统和方法
公开(公告)号：US20080115024A1
公开(公告)日：2008-05-15
申请号：US11595143
申请日：2006-11-10
申请人： Chung-Hsing Wang , Lee-Chung Lu
发明人： Chung-Hsing Wang , Lee-Chung Lu
IPC分类号： G06F11/25 , G06F11/27
CPC分类号： G01R31/318544 , G01R31/318536
摘要： This invention discloses a system and method for testing a plurality of state retention circuits in an integrated circuit (IC) chip, that comprises a built-in test circuit configured to invoke a clock, a save and a restore signal, and a plurality of serially connected data latches receiving the clock, save and restore signals, wherein each data latch employs one of the plurality of state retention circuits, wherein the plurality of data latches save their existing data in their corresponding state retention circuits upon an assertion of the save signal, restore the data from the plurality of state retention circuits back to their corresponding data latches upon an assertion of the restore signal, and shifting the existing data along the series of the data latches one latch a cycle of the clock signal.
摘要翻译：本发明公开了一种用于测试集成电路（IC）芯片中的多个状态保持电路的系统和方法，该系统和方法包括被配置为调用时钟，保存和还原信号以及多个串行的内置测试电路接收时钟的连接数据锁存器，保存和恢复信号，其中每个数据锁存器采用多个状态保持电路中的一个，其中多个数据锁存器在保存信号被断言时将其现有数据保存在其相应的状态保持电路中，在断言恢复信号时，将数据从多个状态保持电路恢复回相应的数据锁存器，并且沿数据锁存器序列移位现有数据一个锁存器是时钟信号的周期。

85. 发明申请

US20070152745A1 System and method for reducing leakage current of an integrated circuit 审中-公开
标题翻译：降低集成电路泄漏电流的系统和方法
公开(公告)号：US20070152745A1
公开(公告)日：2007-07-05
申请号：US11322723
申请日：2005-12-30
申请人： Yung-Chin Hou , Carlos Diaz , Chung-Hsing Wang , Lee-Chung Lu
发明人： Yung-Chin Hou , Carlos Diaz , Chung-Hsing Wang , Lee-Chung Lu
IPC分类号： G05F1/10
CPC分类号： G05F3/205
摘要： The present invention discloses a system for reducing a leakage current of an integrated circuit coupled to a supply voltage source. The system includes a bias module, and a switch device serially coupled between the bias module and the integrated circuit. The bias module generates a bias voltage and the switch device is turned off for reducing the leakage current of the integrated circuit when the integrated circuit is in a sleep mode.
摘要翻译：本发明公开了一种用于减小耦合到电源电压源的集成电路的漏电流的系统。该系统包括偏置模块和串联耦合在偏置模块和集成电路之间的开关装置。偏置模块产生偏置电压，并且当集成电路处于睡眠模式时，开关装置关闭以减小集成电路的漏电流。

86. 发明申请

US20060225007A1 Antenna effect prevention by model extraction in a circuit design for advanced processes 审中-公开
标题翻译：通过模型提取在电路设计中进行高级处理的天线效应预防
公开(公告)号：US20060225007A1
公开(公告)日：2006-10-05
申请号：US11100105
申请日：2005-04-05
申请人： Chung-Hsing Wang , Shou-Yi Lee , Lee-Chung Lu
发明人： Chung-Hsing Wang , Shou-Yi Lee , Lee-Chung Lu
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A method is disclosed for determining an antenna ratio for an interconnect in a circuit. The interconnect may be routed through one or more connection layers and may be electrically coupled to one or more gate oxide areas. A cumulative antenna ratio for all components on each connection layer is determined by considering an antenna effect caused by each component on a predetermined connection layer with regard to the gate oxide areas coupled thereto and any components on one or more connection layers coupled between the component of the present connection layer and the gate oxide areas. In the same fashion, a top layer cumulative antenna ratio for the interconnect is determined based on the cumulative antenna ratios for the connection layers below the top layer.
摘要翻译：公开了一种用于确定电路中互连的天线比率的方法。互连可以被路由穿过一个或多个连接层并且可以电耦合到一个或多个栅极氧化物区域。通过考虑由耦合到其上的栅极氧化物区域的预定连接层上的每个分量引起的天线效应，以及耦合在一个或多个连接层上的组件之间的任何组件来确定每个连接层上的所有组件的累积天线比本连接层和栅极氧化物区域。以相同的方式，基于顶层下面的连接层的累积天线比来确定互连的顶层累积天线比。

87. 发明授权

US09553043B2 Interconnect structure having smaller transition layer via 有权
标题翻译：互连结构具有较小的过渡层通孔
公开(公告)号：US09553043B2
公开(公告)日：2017-01-24
申请号：US13438565
申请日：2012-04-03
申请人： Lee-Chung Lu , Wen-Hao Chen , Yuan-Te Hou , Fang-Yu Fan , Yu-Hsiang Kao , Dian-Hau Chen , Shyue-Shyh Lin , Chii-Ping Chen
发明人： Lee-Chung Lu , Wen-Hao Chen , Yuan-Te Hou , Fang-Yu Fan , Yu-Hsiang Kao , Dian-Hau Chen , Shyue-Shyh Lin , Chii-Ping Chen
IPC分类号： H01L23/522 , H01L23/528
CPC分类号： H01L23/5226 , H01L23/5283 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure including a bottom layer over a substrate, where the bottom layer includes at least one bottom layer line and at least one bottom layer via. The interconnect structure further includes a transition layer over the bottom layer, where the transition layer includes at least one transition layer line and at least one transition layer via. The interconnect structure further includes a top layer over the transition layer, where the top layer includes at least one top layer line and at least one top layer via. The at least one transition layer via has a cross sectional area at least 30% less than a cross sectional area of the at least one top layer via.
摘要翻译：一种互连结构，其包括在衬底上的底层，其中底层包括至少一个底层线和至少一个底层通孔。互连结构还包括在底层上的过渡层，其中过渡层包括至少一个过渡层线和至少一个过渡层通孔。互连结构还包括过渡层上的顶层，其中顶层包括至少一个顶层线和至少一个顶层通孔。所述至少一个过渡层通孔具有比所述至少一个顶层通孔的横截面面积小至少30％的横截面面积。

88. 发明授权

US09337290B2 Layout architecture for performance improvement 有权
标题翻译：布局架构，提升性能
公开(公告)号：US09337290B2
公开(公告)日：2016-05-10
申请号：US13537804
申请日：2012-06-29
申请人： Lee-Chung Lu , Li-Chun Tien , Hui-Zhong Zhuang
发明人： Lee-Chung Lu , Li-Chun Tien , Hui-Zhong Zhuang
IPC分类号： H01L29/423 , H01L29/417 , H01L27/32 , H01L27/02 , H01L21/768
CPC分类号： H01L21/823475 , H01L21/32055 , H01L21/76802 , H01L21/76895 , H01L21/823418 , H01L27/0207 , H01L27/326 , H01L29/0649 , H01L29/41725 , H01L29/41775 , H01L29/4238
摘要： An integrated circuit is provided. The integrated circuit includes a first contact disposed over a first source/drain region, a second contact disposed over a second source/drain region, a polysilicon disposed over a gate, the polysilicon interposed between the first contact and the second contact, a first polysilicon contact bridging the polysilicon and the first contact within an active region, and an output structure electrically coupled to the first polysilicon contact.
摘要翻译：提供集成电路。集成电路包括设置在第一源极/漏极区域上的第一触点，设置在第二源极/漏极区域上的第二触点，设置在栅极上的多晶硅，插入在第一触点和第二触点之间的多晶硅，第一多晶硅在有源区内桥接多晶硅和第一接触，以及电耦合到第一多晶硅接触的输出结构。

89. 发明授权

US08671367B2 Integrated circuit design in optical shrink technology node 有权
标题翻译：光收缩技术节点集成电路设计
公开(公告)号：US08671367B2
公开(公告)日：2014-03-11
申请号：US12340294
申请日：2008-12-19
申请人： Chung-Hsing Wang , Lee-Chung Lu , Yung-Chin Hou , Lie-Szu Juang
发明人： Chung-Hsing Wang , Lee-Chung Lu , Yung-Chin Hou , Lie-Szu Juang
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F17/505
摘要： Disclosed is a system, method, and computer-readable medium for designing a circuit and/or IC chip to be provided using an optical shrink technology node. Initial design data may be provided in a first technology node and through the use of embedding scaling factors in one or more EDA tools of the design flow, a design (e.g., mask data) can be generated for the circuit in an optical shrink technology node. Examples of EDA tools in which embedded scaling factors may be provided are simulation models and extraction tools including LPE decks and RC extraction technology files.
摘要翻译：公开了一种用于设计使用光收缩技术节点提供的电路和/或IC芯片的系统，方法和计算机可读介质。可以在第一技术节点中提供初始设计数据，并且通过在设计流程的一个或多个EDA工具中使用嵌入缩放因子，可以为光收缩技术节点中的电路生成设计（例如，掩模数据）。可以提供嵌入式缩放因子的EDA工具的示例是包括LPE卡片和RC提取技术文件的模拟模型和提取工具。

90. 发明授权

US08431968B2 Electromigration resistant standard cell device 有权
公开(公告)号：US08431968B2
公开(公告)日：2013-04-30
申请号：US12845162
申请日：2010-07-28
申请人： Lee-Chung Lu , Wen-Hao Chen , Yuan-Te Hou , Shen-Feng Chen , Meng-Fu You
发明人： Lee-Chung Lu , Wen-Hao Chen , Yuan-Te Hou , Shen-Feng Chen , Meng-Fu You
IPC分类号： H01L23/52
CPC分类号： G06F17/5077 , G06F17/5036 , G06F17/5045 , G06F17/5072 , G06F17/5081 , G06F2217/82 , H01L23/5286 , H01L27/10 , H01L2924/0002 , H01L2924/00
摘要： A standard cell semiconductor integrated circuit device design provides a standard cell semiconductor device that includes first standard cells and user-defined target standard cells which consume more power or include other operational characteristics that differ from the operational characteristics of the first standard cells. The standard cells are routed to ground and power wires using one power rail and the target cells are routed to the ground and power lines using the first power rail and a second power rail to alleviate electromigration in either of the power rails. The two power rails include an upper power rail and a lower power rail. An intermediate conductive layer may be disposed between the upper and lower power rails to provide for signal routing by lateral interconnection between cells.

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