专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20070152745A1 System and method for reducing leakage current of an integrated circuit 审中-公开
标题翻译：降低集成电路泄漏电流的系统和方法
公开(公告)号：US20070152745A1
公开(公告)日：2007-07-05
申请号：US11322723
申请日：2005-12-30
申请人： Yung-Chin Hou , Carlos Diaz , Chung-Hsing Wang , Lee-Chung Lu
发明人： Yung-Chin Hou , Carlos Diaz , Chung-Hsing Wang , Lee-Chung Lu
IPC分类号： G05F1/10
CPC分类号： G05F3/205
摘要： The present invention discloses a system for reducing a leakage current of an integrated circuit coupled to a supply voltage source. The system includes a bias module, and a switch device serially coupled between the bias module and the integrated circuit. The bias module generates a bias voltage and the switch device is turned off for reducing the leakage current of the integrated circuit when the integrated circuit is in a sleep mode.
摘要翻译：本发明公开了一种用于减小耦合到电源电压源的集成电路的漏电流的系统。该系统包括偏置模块和串联耦合在偏置模块和集成电路之间的开关装置。偏置模块产生偏置电压，并且当集成电路处于睡眠模式时，开关装置关闭以减小集成电路的漏电流。

2. 发明授权

US08671367B2 Integrated circuit design in optical shrink technology node 有权
标题翻译：光收缩技术节点集成电路设计
公开(公告)号：US08671367B2
公开(公告)日：2014-03-11
申请号：US12340294
申请日：2008-12-19
申请人： Chung-Hsing Wang , Lee-Chung Lu , Yung-Chin Hou , Lie-Szu Juang
发明人： Chung-Hsing Wang , Lee-Chung Lu , Yung-Chin Hou , Lie-Szu Juang
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F17/505
摘要： Disclosed is a system, method, and computer-readable medium for designing a circuit and/or IC chip to be provided using an optical shrink technology node. Initial design data may be provided in a first technology node and through the use of embedding scaling factors in one or more EDA tools of the design flow, a design (e.g., mask data) can be generated for the circuit in an optical shrink technology node. Examples of EDA tools in which embedded scaling factors may be provided are simulation models and extraction tools including LPE decks and RC extraction technology files.
摘要翻译：公开了一种用于设计使用光收缩技术节点提供的电路和/或IC芯片的系统，方法和计算机可读介质。可以在第一技术节点中提供初始设计数据，并且通过在设计流程的一个或多个EDA工具中使用嵌入缩放因子，可以为光收缩技术节点中的电路生成设计（例如，掩模数据）。可以提供嵌入式缩放因子的EDA工具的示例是包括LPE卡片和RC提取技术文件的模拟模型和提取工具。

3. 发明申请

US20090326873A1 INTEGRATED CIRCUIT DESIGN IN OPTICAL SHRINK TECHNOLOGY NODE 有权
标题翻译：光收缩技术节点集成电路设计
公开(公告)号：US20090326873A1
公开(公告)日：2009-12-31
申请号：US12340294
申请日：2008-12-19
申请人： Chung-Hsing Wang , Lee-Chung Lu , Yung-Chin Hou , Lie-Szu Juang
发明人： Chung-Hsing Wang , Lee-Chung Lu , Yung-Chin Hou , Lie-Szu Juang
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F17/505
摘要： Disclosed is a system, method, and computer-readable medium for designing a circuit and/or IC chip to be provided using an optical shrink technology node. Initial design data may be provided in a first technology node and through the use of embedding scaling factors in one or more EDA tools of the design flow, a design (e.g., mask data) can be generated for the circuit in an optical shrink technology node. Examples of EDA tools in which embedded scaling factors may be provided are simulation models and extraction tools including LPE decks and RC extraction technology files.
摘要翻译：公开了一种用于设计使用光收缩技术节点提供的电路和/或IC芯片的系统，方法和计算机可读介质。可以在第一技术节点中提供初始设计数据，并且通过在设计流程的一个或多个EDA工具中使用嵌入缩放因子，可以为光收缩技术节点中的电路生成设计（例如，掩模数据）。可以提供嵌入式缩放因子的EDA工具的示例是包括LPE卡片和RC提取技术文件的模拟模型和提取工具。

4. 发明授权

US07913141B2 Power gating in integrated circuits for leakage reduction 有权
标题翻译：集成电路中的电源门控用于泄漏减少
公开(公告)号：US07913141B2
公开(公告)日：2011-03-22
申请号：US11505113
申请日：2006-08-16
申请人： Lee-Chung Yu , Chung-Hsing Wang , Yung-Chin Hou
发明人： Lee-Chung Yu , Chung-Hsing Wang , Yung-Chin Hou
IPC分类号： G01R31/3187 , G01R31/40
CPC分类号： G01R31/31721
摘要： A system is disclosed for reducing current leakages in an integrated circuit (IC), the system comprises one or more separated power supply lines connecting between one or more power sources and an isolated circuitry, one or more switches on the separated power supply lines for controlling the connections between the power sources and the isolated circuitry, and one or more controllers for turning the switches on or off according to one or more predetermined conditions.
摘要翻译：公开了一种用于减少集成电路（IC）中的电流泄漏的系统，该系统包括连接在一个或多个电源和隔离电路之间的一个或多个分开的电源线，分离的电源线上的一个或多个开关用于控制电源和隔离电路之间的连接，以及根据一个或多个预定条件打开或关闭开关的一个或多个控制器。

5. 发明授权

US08504965B2 Method for non-shrinkable IP integration 有权
标题翻译：不收缩IP集成方法
公开(公告)号：US08504965B2
公开(公告)日：2013-08-06
申请号：US12895264
申请日：2010-09-30
申请人： Hung-Yi Liu , Chung-Hsing Wang , Yung-Chin Hou , Lie-Szu Juang
发明人： Hung-Yi Liu , Chung-Hsing Wang , Yung-Chin Hou , Lie-Szu Juang
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F2217/66
摘要： A method of designing integrated circuits includes providing a design of an integrated circuit at a first scale, wherein the integrated circuit includes a shrinkable circuit including a first intellectual property (IP); and a non-shrinkable circuit including a second IP having a hierarchical structure. A marker layer is formed to cover the non-shrinkable circuit, wherein the shrinkable circuit is not covered by the marker layer. The electrical performance of the non-shrinkable circuit is simulated using a simulation tool, wherein the simulated non-shrinkable circuit is at a second scale smaller than the first scale.
摘要翻译：设计集成电路的方法包括以第一标度提供集成电路的设计，其中该集成电路包括包括第一知识产权（IP）的可收缩电路; 以及包括具有分层结构的第二IP的不可收缩电路。形成标记层以覆盖不可收缩电路，其中可收缩电路不被标记层覆盖。使用仿真工具模拟不可收缩电路的电气性能，其中模拟的不可收缩电路的尺寸比第一刻度小。

6. 发明申请

US20120084745A1 Design Method for Non-Shrinkable IP Integration 有权
标题翻译：不可收缩的IP集成设计方法
公开(公告)号：US20120084745A1
公开(公告)日：2012-04-05
申请号：US12895264
申请日：2010-09-30
申请人： Hung-Yi Liu , Chung-Hsing Wang , Yung-Chin Hou , Lie-Szu Juang
发明人： Hung-Yi Liu , Chung-Hsing Wang , Yung-Chin Hou , Lie-Szu Juang
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F2217/66
摘要： A method of designing integrated circuits includes providing a design of an integrated circuit at a first scale, wherein the integrated circuit includes a shrinkable circuit including a first intellectual property (IP); and a non-shrinkable circuit including a second IP having a hierarchical structure. A marker layer is formed to cover the non-shrinkable circuit, wherein the shrinkable circuit is not covered by the marker layer. The electrical performance of the non-shrinkable circuit is simulated using a simulation tool, wherein the simulated non-shrinkable circuit is at a second scale smaller than the first scale.
摘要翻译：设计集成电路的方法包括以第一标度提供集成电路的设计，其中该集成电路包括包括第一知识产权（IP）的可收缩电路; 以及包括具有分层结构的第二IP的不可收缩电路。形成标记层以覆盖不可收缩电路，其中可收缩电路不被标记层覆盖。使用仿真工具模拟不可收缩电路的电气性能，其中模拟的不可收缩电路的尺寸比第一刻度小。

7. 发明申请

US20080082876A1 Power gating in integrated circuits for leakage reduction 有权
标题翻译：集成电路中的电源门控用于泄漏减少
公开(公告)号：US20080082876A1
公开(公告)日：2008-04-03
申请号：US11505113
申请日：2006-08-16
申请人： Lee-Chung Yu , Chung-Hsing Wang , Yung-Chin Hou
发明人： Lee-Chung Yu , Chung-Hsing Wang , Yung-Chin Hou
IPC分类号： G01R31/28
CPC分类号： G01R31/31721
摘要： A system is disclosed for reducing current leakages in an integrated circuit (IC), the system comprises one or more separated power supply lines connecting between one or more power sources and an isolated circuitry, one or more switches on the separated power supply lines for controlling the connections between the power sources and the isolated circuitry, and one or more controllers for turning the switches on or off according to one or more predetermined conditions.
摘要翻译：公开了一种用于减少集成电路（IC）中的电流泄漏的系统，该系统包括连接在一个或多个电源和隔离电路之间的一个或多个分开的电源线，分离的电源线上的一个或多个开关用于控制电源和隔离电路之间的连接，以及根据一个或多个预定条件打开或关闭开关的一个或多个控制器。

8. 发明授权

US07640520B2 Design flow for shrinking circuits having non-shrinkable IP layout 有权
标题翻译：具有不可收缩IP布局的收缩电路的设计流程
公开(公告)号：US07640520B2
公开(公告)日：2009-12-29
申请号：US11807640
申请日：2007-05-30
申请人： Chung-Hsing Wang , Lee-Chung Lu , Cliff Hou , Lie-Szu Juang
发明人： Chung-Hsing Wang , Lee-Chung Lu , Cliff Hou , Lie-Szu Juang
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F17/5045
摘要： A method for processing an integrated circuit is provided. The method includes providing a first integrated circuit having a first scale, wherein the first integrated circuit comprises a shrinkable circuit comprising a first intellectual property (IP) layout, and a non-shrinkable circuit comprising a second IP layout; and generating a second integrated circuit having a second scale smaller than the first scale. The step of generating the second integrated circuit includes shrinking the shrinkable integrated circuit to the second scale. The method further includes merging the second IP layout with the non-shrinkable circuit to generate a final integrated circuit.
摘要翻译：提供了一种用于处理集成电路的方法。该方法包括提供具有第一标度的第一集成电路，其中第一集成电路包括包含第一知识产权（IP）布局的可收缩电路和包括第二IP布局的不可收缩电路; 以及生成具有小于所述第一刻度的第二刻度的第二集成电路。产生第二集成电路的步骤包括将可收缩集成电路收缩到第二刻度。该方法还包括将第二IP布局与不可收缩电路合并以产生最终集成电路。

9. 发明申请

US20080270813A1 Mother/daughter switch design with self power-up control 有权
标题翻译：母/子开关设计具有自上电控制功能
公开(公告)号：US20080270813A1
公开(公告)日：2008-10-30
申请号：US11789721
申请日：2007-04-24
申请人： Shih-Hsien Yang , Chung-Hsing Wang , Lee-Chung Lu , Chun-Hui Tai , Cliff Hou
发明人： Shih-Hsien Yang , Chung-Hsing Wang , Lee-Chung Lu , Chun-Hui Tai , Cliff Hou
IPC分类号： G06F1/32
CPC分类号： G06F1/3203
摘要： System and method for providing power to integrated circuitry with good power-on responsive time and reduced power-on transient glitches. A preferred embodiment comprises a daughter switch coupled to a circuit block, a first control circuit coupled to the daughter circuit, a second control circuit coupled to the first control circuit, and a mother circuit coupled to the circuit block and to the second control circuit. After the daughter switch is turned on by a control signal, the mother switch is not turned on until the daughter switch has discharged (charged) the voltage potential across power rails of the mother circuit to a point where glitches are minimized. The second control circuit turns on the mother circuit when the reduced voltage potential is reached, with a signal produced by the first control circuit reflects the voltage potential. Furthermore, a bypass circuit can be used to reduce leakage current.
摘要翻译：为集成电路提供电源的系统和方法具有良好的上电响应时间和减少的上电瞬态毛刺。优选实施例包括耦合到电路块的子开关，耦合到子电路的第一控制电路，耦合到第一控制电路的第二控制电路以及耦合到电路块和第二控制电路的母电路。在通过控制信号接通子开关之后，母开关直到子开关已经将母电路的电源轨上的电压放电（充电）到毛刺最小化的位置为止。当达到降低的电压电位时，第二控制电路接通母电路，由第一控制电路产生的信号反映电压电位。此外，可以使用旁路电路来减少泄漏电流。

10. 发明授权

US07793130B2 Mother/daughter switch design with self power-up control 有权
标题翻译：母/子开关设计具有自上电控制功能
公开(公告)号：US07793130B2
公开(公告)日：2010-09-07
申请号：US11789721
申请日：2007-04-24
申请人： Shih-Hsien Yang , Chung-Hsing Wang , Lee-Chung Lu , Chun-Hui Tai , Cliff Hou
发明人： Shih-Hsien Yang , Chung-Hsing Wang , Lee-Chung Lu , Chun-Hui Tai , Cliff Hou
IPC分类号： G06F1/26
CPC分类号： G06F1/3203
摘要： System and method for providing power to integrated circuitry with good power-on responsive time and reduced power-on transient glitches. A preferred embodiment comprises a daughter switch coupled to a circuit block, a first control circuit coupled to the daughter circuit, a second control circuit coupled to the first control circuit, and a mother circuit coupled to the circuit block and to the second control circuit. After the daughter switch is turned on by a control signal, the mother switch is not turned on until the daughter switch has discharged (charged) the voltage potential across power rails of the mother circuit to a point where glitches are minimized. The second control circuit turns on the mother circuit when the reduced voltage potential is reached, with a signal produced by the first control circuit reflects the voltage potential. Furthermore, a bypass circuit can be used to reduce leakage current.
摘要翻译：为集成电路提供电源的系统和方法具有良好的上电响应时间和减少的上电瞬态毛刺。优选实施例包括耦合到电路块的子开关，耦合到子电路的第一控制电路，耦合到第一控制电路的第二控制电路和耦合到电路块和第二控制电路的母电路。在通过控制信号接通子开关之后，母开关直到子开关已经将母电路的电源轨上的电压放电（充电）到毛刺最小化的位置为止。当达到降低的电压电位时，第二控制电路接通母电路，由第一控制电路产生的信号反映电压电位。此外，可以使用旁路电路来减少泄漏电流。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式