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81. 发明授权

US07057225B2 Semiconductor memory circuitry 失效
标题翻译：半导体存储器电路
公开(公告)号：US07057225B2
公开(公告)日：2006-06-06
申请号：US10304804
申请日：2002-11-26
申请人： Brent Keeth , Pierre C Fazan
发明人： Brent Keeth , Pierre C Fazan
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L27/105 , H01L27/108 , H01L27/10811 , Y10T29/49121
摘要： Processes are disclosed which facilitate improved high-density memory circuitry, most preferably dynamic random access memory (DRAM) circuitry. An integrated circuit includes a semiconductor die, a plurality of functional and operably addressable memory cells arranged in at least one array formed on the semiconductor die, and circuitry formed on the semiconductor die and coupled to the memory cells for permitting data to be written to and read from the memory cells. The memory cells are formed with a minimum capable photolithographic feature dimension. A single memory cell consumes an area of no more than eight times the square of the minimum capable photolithographic feature dimension.
摘要翻译：公开了促进改进的高密度存储器电路，最优选动态随机存取存储器（DRAM）电路的方法。集成电路包括半导体管芯，布置在形成在半导体管芯上的至少一个阵列中的多个功能和可操作地寻址的存储器单元，以及形成在半导体管芯上并耦合到存储器单元的电路，用于允许数据被写入到从内存单元读取。存储单元由最小能力的光刻特征尺寸形成。单个存储器单元消耗的面积不超过最小能力光刻特征尺寸的平方的八倍。

82. 发明授权

US06987702B2 Method and apparatus for data compression in memory devices 失效
公开(公告)号：US06987702B2
公开(公告)日：2006-01-17
申请号：US10879935
申请日：2004-06-28
申请人： Brent Keeth
发明人： Brent Keeth
IPC分类号： G11C11/00
CPC分类号： G11C29/1201 , G11C29/40
摘要： A test circuit for a memory device having a pair of arrays each of which includes a plurality of memory cells arranged in rows and columns. A pair of complementary digit lines is provided for each column of each array. The digit lines are selectively coupled to a pair of I/O lines for each array which are, in turn, coupled to a pair of complementary data lines. The data lines are coupled to respective inputs of a DC sense amplifier, one of which is provided for each array. A multiplexer connects the pair of I/O lines for either one of the arrays to the data lines in a normal operating mode. Thus, in the normal operating mode, data are selectively coupled to the inputs of the DC sense amplifier from the complementary digit lines for an addressed column. In a test mode, the multiplexer connects the I/O lines for both arrays to the data lines to compress the data from the two arrays. Combinatorial logic then determines if both of the data lines have the same logical value, indicating disagreement between the data from the memory arrays that may indicate the presence of a defective memory cell in one or the other array. Thus, in the test mode, data are simultaneously coupled to the inputs of the DC sense amplifier from respective digit lines coupled to two different memory cells, thereby increasing the rate at which background data that has been written to the arrays can be read from the arrays.

83. 发明申请

US20050286326A1 Method and apparatus for data compression in memory devices 有权
公开(公告)号：US20050286326A1
公开(公告)日：2005-12-29
申请号：US11218038
申请日：2005-08-31
申请人： Brent Keeth
发明人： Brent Keeth
IPC分类号： G11C29/00 , G11C29/40
CPC分类号： G11C29/1201 , G11C29/40
摘要： A test circuit for a memory device having a pair of arrays each of which includes a plurality of memory cells arranged in rows and columns. A pair of complementary digit lines is provided for each column of each array. The digit lines are selectively coupled to a pair of I/O lines for each array which are, in turn, coupled to a pair of complementary data lines. The data lines are coupled to respective inputs of a DC sense amplifier, one of which is provided for each array. A multiplexer connects the pair of I/O lines for either one of the arrays to the data lines in a normal operating mode. Thus, in the normal operating mode, data are selectively coupled to the inputs of the DC sense amplifier from the complementary digit lines for an addressed column. In a test mode, the multiplexer connects the I/O lines for both arrays to the data lines to compress the data from the two arrays. Combinatorial logic then determines if both of the data lines have the same logical value, indicating disagreement between the data from the memory arrays that may indicate the presence of a defective memory cell in one or the other array. Thus, in the test mode, data are simultaneously coupled to the inputs of the DC sense amplifier from respective digit lines coupled to two different memory cells, thereby increasing the rate at which background data that has been written to the arrays can be read from the arrays.

84. 发明申请

US20050142703A1 Dual-gate transistor device and method of forming a dual-gate transistor device 有权
标题翻译：双栅极晶体管器件和形成双栅极晶体管器件的方法
公开(公告)号：US20050142703A1
公开(公告)日：2005-06-30
申请号：US10932192
申请日：2004-09-01
申请人： John Zahurak , Brent Keeth , Charles Dennison
发明人： John Zahurak , Brent Keeth , Charles Dennison
IPC分类号： H01L21/336 , H01L21/84 , H01L27/12 , H01L29/786 , H01L21/00 , H01L27/01 , H01L31/0392
CPC分类号： H01L29/66772 , H01L21/76897 , H01L21/76898 , H01L21/84 , H01L27/1203 , H01L29/78621 , H01L29/78645 , H01L29/78648
摘要： Embodiments in accordance with the present invention provide methods of forming a dual gated semiconductor-on-insulator (SOI) device. Such methods encompass forming a first transistor structure operatively adjacent a first side of the semiconductor layer of an SOI substrate. Insulator layer material is removed from the second side of the semiconductor layer, between the source/drain contact structures of the first transistor structure and a second transistor structure there formed operatively adjacent the second side of the semiconductor layer and aligned to the first transistor structure.
摘要翻译：根据本发明的实施例提供了形成双门限半导体绝缘体（SOI）器件的方法。这样的方法包括形成与SOI衬底的半导体层的第一侧可操作地相邻的第一晶体管结构。绝缘体层材料从第一晶体管结构的源极/漏极接触结构和第二晶体管结构之间的半导体层的第二侧被去除，第二晶体管结构可操作地邻近半导体层的第二侧并与第一晶体管结构对准。

85. 发明授权

US06889357B1 Timing calibration pattern for SLDRAM 失效
公开(公告)号：US06889357B1
公开(公告)日：2005-05-03
申请号：US09568155
申请日：2000-05-10
申请人： Brent Keeth , Brian Johnson , Terry R. Lee , Paul M. Fuller
发明人： Brent Keeth , Brian Johnson , Terry R. Lee , Paul M. Fuller
IPC分类号： G11B27/00 , G11C7/10 , G11C8/02 , H03L7/081 , H04L7/00 , H04L7/04 , H04L7/10
CPC分类号： G11C7/222 , G11C7/1072 , G11C2207/2254 , H03L7/0812 , H04L7/0041 , H04L7/043 , H04L7/10
摘要： Disclosed is an improved start-up/reset calibration apparatus and method for use in an SLDRAM memory device A 2N bit calibration pattern which is based on a pseudo random sequence is used to calibrate the relative timing of data and a latching clock signal to ensure optimal operation of the memory device. In addition, during calibration of one data path, other nearby data paths may receive in phase, out of phase and/or both in phase and out of phase versions of the calibration pattern so that the data path under calibration is calibrated under conditions which more closely approximate random operating conditions.

86. 发明授权

US06847100B2 High speed IC package configuration 失效
标题翻译：高速IC封装配置
公开(公告)号：US06847100B2
公开(公告)日：2005-01-25
申请号：US10457869
申请日：2003-06-10
申请人： David J. Corisis , Brent Keeth
发明人： David J. Corisis , Brent Keeth
IPC分类号： H01L23/64 , H01L23/66 , H01L23/02
CPC分类号： H01L23/66 , H01L23/645 , H01L24/48 , H01L24/49 , H01L2224/48247 , H01L2224/49111 , H01L2224/49171 , H01L2924/00014 , H01L2924/01023 , H01L2924/01047 , H01L2924/14 , H01L2924/181 , H01L2924/30107 , H01L2924/3011 , H01L2924/00 , H01L2224/45099 , H01L2224/05599
摘要： Devices and methods are provided for reducing lead inductance in integrated circuit (IC) packages. An integrated circuit package configuration is provided for high speed applications where the inductance of the leads is reduced or minimized in high capacity semiconductor device packages. The integrated circuit package assembly comprises a substrate, semiconductor device, insulating covering or coating, if desired, a semiconductor device retainer, lead frame, and wire bond interconnections.
摘要翻译：提供的装置和方法用于减少集成电路（IC）封装中的引线电感。为高速应用提供集成电路封装配置，其中引线的电感在大容量半导体器件封装中减小或最小化。集成电路封装组件包括衬底，半导体器件，绝缘覆盖物或涂层，如果需要，半导体器件保持器，引线框架和引线接合互连。

87. 发明授权

US06842398B2 Multi-mode synchronous memory device and methods of operating and testing same 失效
公开(公告)号：US06842398B2
公开(公告)日：2005-01-11
申请号：US10703275
申请日：2003-11-07
申请人： Brian Johnson , Brent Keeth , Jeffrey W. Janzen , Troy A. Manning , Chris G. Martin
发明人： Brian Johnson , Brent Keeth , Jeffrey W. Janzen , Troy A. Manning , Chris G. Martin
IPC分类号： G01R31/28 , G11C7/10 , G11C7/22 , G11C11/401 , G11C11/407 , G11C29/14 , G11C8/00
CPC分类号： G11C29/12015 , G11C7/1078 , G11C7/109 , G11C7/22 , G11C7/222 , G11C29/14
摘要： A synchronous semiconductor memory device is operable in a normal mode and an alternative mode. The semiconductor device has a command bus for receiving a plurality of synchronously captured input signals, and a plurality of asynchronous input terminals for receiving a plurality of asynchronous input signals. The device further has a clock input for receiving an external clock signal thereon, with the device being specified by the manufacturer to be operated in the normal mode using an external clock signal having a frequency no less than a predetermined minimum frequency. An internal delay locked loop (DLL) clocking circuit is coupled to the clock input terminal and is responsive in normal operating mode to be responsive to the external clock signal to generate at least one internal clock signal. control circuitry in the device is responsive to a predetermined sequence of asynchronous signals applied to the device's asynchronous input terminals to place the device in an alternative mode of operation in which the internal clocking circuit is disabled, such that the device may be operated in the alternative mode using an external clock signal having a frequency less than the predetermined minimum frequency. The alternative mode of operation facilitates testing of the device at a speed less than the minimum frequency specified for the normal mode of operation.

88. 发明授权

US06762974B1 Method and apparatus for establishing and maintaining desired read latency in high-speed DRAM 失效
标题翻译：用于在高速DRAM中建立和维持期望的读延迟的方法和装置
公开(公告)号：US06762974B1
公开(公告)日：2004-07-13
申请号：US10389807
申请日：2003-03-18
申请人： Brian Johnson , Brent Keeth , Feng Lin
发明人： Brian Johnson , Brent Keeth , Feng Lin
IPC分类号： G11C800
CPC分类号： G11C7/222 , G11C7/1072 , G11C11/4076
摘要： A method and apparatus for managing the variable timing of internal clock signals derived from an external clock signal in order to compensate for uncertainty and variations in the amount of read clock back timing relative to data flow to achieve a specified read latency. A reset signal is generated at DRAM initialization and starts an first counter, which counts external clock cycles, and is also passed through the slave delay line of the delay lock loop to start a second counter. The counters run continuously once started and the difference in count values represent the internal delay as an external clock signal passes through the delay lock loop to produce an internal read clock signal. An internal read latency value is used to offset either counter to account for the internal read latency of the DRAM circuit. Once the non-offset counter is equivalent to the offset counter, read data is placed on an output line with a specified read latency and synchronized with the external read clock.
摘要翻译：一种用于管理从外部时钟信号导出的内部时钟信号的可变定时的方法和装置，以便补偿相对于数据流的读取时钟反馈时序的不确定性和变化，以实现指定的读取等待时间。在DRAM初始化时产生复位信号，并启动计数外部时钟周期的第一计数器，并且还通过延迟锁定循环的从延迟线来启动第二个计数器。一旦启动，计数器连续运行，当外部时钟信号通过延迟锁定环路以产生内部读取时钟信号时，计数值的差异代表内部延迟。内部读延迟值用于抵消DRAM电路的内部读延迟。一旦非偏移计数器等效于偏移计数器，读取数据将放置在具有指定读延迟并与外部读时钟同步的输出线上。

89. 发明授权

US06703656B2 Semiconductor memory circuitry including die sites sized for 256M to 275M memory cells in a 12″ wafer 失效
标题翻译：半导体存储器电路包括尺寸为12英寸晶圆中的256M至275M存储单元的模具位置
公开(公告)号：US06703656B2
公开(公告)日：2004-03-09
申请号：US09917844
申请日：2001-07-26
申请人： Brent Keeth , Pierre C. Fazan
发明人： Brent Keeth , Pierre C. Fazan
IPC分类号： H01L2708
CPC分类号： H01L27/105 , H01L27/108 , H01L27/10811 , Y10T29/49121
摘要： Processes are disclosed which facilitate improved high-density memory circuitry, most preferably dynamic random access memory (DRAM) circuitry. In accordance with aspects of the invention, considerably greater numbers of die sites per wafer are achieved for 6-inch, 8-inch and 12-inch wafers for 4M, 16M, 64M and 256M integration levels. Further, a semiconductor memory device includes i) a plurality of functional and operably addressable memory cells arranged in multiple memory arrays formed on a semiconductor die; and ii) circuitry formed on the semiconductor die permitting data to be written to and read from one or more of the memory cells, at least one of the memory arrays containing at least 100 square microns of continuous die surface area having at least 170 of the functional and operably addressable memory cells.
摘要翻译：公开了促进改进的高密度存储器电路，最优选动态随机存取存储器（DRAM）电路的方法。根据本发明的方面，对于用于4M，16M，64M和256M积分级别的6英寸，8英寸和12英寸晶片，实现了相当大数量的每个晶片的晶片位置。此外，半导体存储器件包括：i）布置在形成在半导体管芯上的多个存储器阵列中的多个功能和可操作地寻址的存储器单元; 以及ii）形成在所述半导体管芯上的电路，允许将数据写入到所述存储器单元中的一个或多个存储单元并从其读取，所述存储器阵列中的至少一个包含至少100平方微米的连续管芯表面区域，其具有至少170个功能和可操作地寻址的存储单元。

90. 发明授权

US06696867B2 Voltage generator with stability indicator circuit 失效
标题翻译：电压发生器带稳定指示电路
公开(公告)号：US06696867B2
公开(公告)日：2004-02-24
申请号：US09907565
申请日：2001-07-18
申请人： Brent Keeth , Layne G. Bunker , Scott J. Derner
发明人： Brent Keeth , Layne G. Bunker , Scott J. Derner
IPC分类号： G01R1900
CPC分类号： G11C5/063 , G11C5/025 , G11C5/145 , G11C5/147 , G11C11/401 , G11C11/4074 , G11C11/4076 , G11C11/4097 , G11C11/4099 , G11C29/021 , G11C29/028 , G11C29/12 , G11C29/12005 , G11C29/46 , G11C29/787 , G11C2029/0407 , H01L27/10805 , H01L2224/4826 , H01L2224/73215 , H01L2924/1305 , H01L2924/13091 , H01L2924/00
摘要： A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. Sense amplifiers are positioned between adjacent rows in the individual arrays while row decoders are positioned between adjacent columns in the individual arrays. In certain of the gap cells, multiplexers are provided to transfer signals from I/O lines to data lines. A datapath is provided which, in addition to the foregoing, includes array I/O blocks, responsive to the datalines from each quadrant to output data to a data read mux, data buffers, and data driver pads. The write data path includes a data in buffer and data write muxes for providing data to the array I/O blocks. A power bus is provided which minimizes routing of externally supplied voltages, completely rings each of the array blocks, and provides gridded power distribution within each of the array blocks. A plurality of voltage supplies provide the voltages needed in the array and in the peripheral circuits. The power supplies are organized to match their power output to the power demand and to maintain a desired ratio of power production capability and decoupling capacitance. A powerup sequence circuit is provided to control the powerup of the chip. Redundant rows and columns are provided as is the circuitry necessary to logically replace defective rows and columns with operational rows and columns. Circuitry is also provided on chip to support various types of test modes.
摘要翻译：一个256兆赫动态随机存取存储器由组成单独阵列的多个单元组成，阵列被组织成32兆赫阵列阵列，它们被组织成64兆象限。感测放大器位于各个阵列中的相邻行之间，而行解码器位于各个阵列中的相邻列之间。在某些间隙单元中，提供多路复用器以将信号从I / O线传送到数据线。提供了一种数据路径，除了上述之外，还包括阵列I / O块，响应于每个象限的数据，将数据输出到数据读取多路复用器，数据缓冲器和数据驱动器焊盘。写数据路径包括用于向阵列I / O块提供数据的缓冲器和数据写入多路复用器中的数据。提供电源总线，其最小化外部提供的电压的路由，完全环绕每个阵列块，并且在每个阵列块内提供网格化的功率分配。多个电压源提供阵列和外围电路中所需的电压。电源组合以将其功率输出与功率需求相匹配，并保持所需的功率生产能力和去耦电容的比例。提供上电序列电路以控制芯片的上电。提供了冗余的行和列，就像使用操作行和列逻辑地替换有缺陷的行和列所需的电路一样。芯片上还提供电路以支持各种类型的测试模式。

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