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1. 发明申请

US20110024762A1 Method of Forming a Thin Film Transistor 审中-公开
标题翻译：形成薄膜晶体管的方法
公开(公告)号：US20110024762A1
公开(公告)日：2011-02-03
申请号：US12901981
申请日：2010-10-11
申请人： Gurtej S. Sandhu , Shubneesh Batra , Pierre C. Fazan
发明人： Gurtej S. Sandhu , Shubneesh Batra , Pierre C. Fazan
IPC分类号： H01L29/66
CPC分类号： H01L29/78678 , H01L27/1214 , H01L27/127 , H01L29/04 , H01L29/6675 , H01L29/66757 , H01L29/66765 , H01L29/78672 , H01L29/78675
摘要： A method of forming a thin film transistor relative to a substrate includes, a) providing a thin film transistor layer of polycrystalline material on a substrate, the polycrystalline material comprising grain boundaries; b) providing a fluorine containing layer adjacent the polycrystalline thin film layer; c) annealing the fluorine containing layer at a temperature and for a time period which in combination are effective to drive fluorine from the fluorine containing layer into the polycrystalline thin film layer and incorporate fluorine within the grain boundaries to passivate said grain boundaries; and d) providing a transistor gate operatively adjacent the thin film transistor layer. The thin film transistor can be fabricated to be bottom gated or top gated. A buffering layer can be provided intermediate the thin film transistor layer and the fluorine containing layer, with the buffering layer being transmissive of fluorine from the fluorine containing layer during the annealing. Preferably, the annealing temperature is both sufficiently high to drive fluorine from the fluorine containing layer into the polycrystalline thin film layer and incorporate fluorine within the grain boundaries to passivate said grain boundaries, but sufficiently low to prevent chemical reaction of the fluorine containing layer with the polycrystalline thin film layer.
摘要翻译：相对于衬底形成薄膜晶体管的方法包括：a）在衬底上提供多晶材料的薄膜晶体管层，所述多晶材料包括晶界; b）在多晶薄膜层附近提供含氟层; c）在一段温度和一段时间内退火含氟层，所述时间段有效地将氟从含氟层驱动到多晶薄膜层中，并且在晶界内引入氟以钝化所述晶界; 以及d）提供与所述薄膜晶体管层可操作地相邻的晶体管栅极。薄膜晶体管可以被制造为底部门控或顶部门控。可以在薄膜晶体管层和含氟层之间设置缓冲层，缓冲层在退火期间从含氟层透过氟。优选地，退火温度足够高以将氟从含氟层驱动到多晶薄膜层中并且在晶界内引入氟以使所述晶界钝化，但是足够低以防止含氟层与多晶薄膜层。

2. 发明授权

US07705383B2 Integrated circuitry for semiconductor memory 失效
标题翻译：半导体存储器的集成电路
公开(公告)号：US07705383B2
公开(公告)日：2010-04-27
申请号：US08530661
申请日：1995-09-20
申请人： Brent Keeth , Pierre C. Fazan
发明人： Brent Keeth , Pierre C. Fazan
IPC分类号： H01L27/108
CPC分类号： H01L27/10888 , H01L27/105 , H01L27/108 , H01L27/10811
摘要： Processes are disclosed which facilitate improved high-density memory circuitry, most preferably dynamic random access memory (DRAM) circuitry. A semiconductor memory device includes i) a total of no more than 68,000,000 functional and operably addressable memory cells arranged in multiple memory arrays formed on a semiconductor die; and ii) circuitry formed on the semiconductor die permitting data to be written to and read from one or more of the memory cells, at least one of the memory arrays containing at least 100-square microns of continuous die surface area having at least 128 of the functional and operably addressable memory cells, more preferably, at least 100 square microns of continuous die surface area having at least 170 of the functional and operably addressable memory cells.
摘要翻译：公开了促进改进的高密度存储器电路，最优选动态随机存取存储器（DRAM）电路的方法。半导体存储器件包括i）总共不超过68,000,000个功能和可操作地寻址的存储器单元，布置在形成在半导体管芯上的多个存储器阵列中; 以及ii）形成在所述半导体管芯上的电路，允许将数据写入到所述存储器单元中的一个或多个存储单元并从其读取，所述存储器阵列中的至少一个包含至少100平方微米的连续管芯表面区域，功能和可操作寻址的存储器单元，更优选至少100平方微米的具有至少170个功能和可操作寻址的存储单元的连续管芯表面区域。

3. 发明授权

US07398595B2 Method for forming a storage cell capacitor compatible with high dielectric constant materials 有权
标题翻译：用于形成与高介电常数材料兼容的存储单元电容器的方法
公开(公告)号：US07398595B2
公开(公告)日：2008-07-15
申请号：US11458072
申请日：2006-07-17
申请人： Pierre C. Fazan , Viju K. Mathews
发明人： Pierre C. Fazan , Viju K. Mathews
IPC分类号： H01K3/10
CPC分类号： H01L27/11502 , H01L21/7687 , H01L27/10817 , H01L27/10852 , H01L27/10855 , H01L27/10885 , H01L27/11507 , H01L28/40 , H01L28/55 , H01L28/60 , H01L28/65 , H01L28/75 , H01L28/91 , Y10T29/435 , Y10T29/49165
摘要： An integrated circuit structure includes a digit line and an electrode adapted to be part of a storage cell capacitor and includes a barrier layer interposed between a conductive plug and an oxidation resistant layer. An insulative layer protects sidewalls of the barrier layer during deposition and anneal of a dielectric layer. The method includes forming the conductive plug recessed in an insulative layer. The barrier layer is formed in the recess and the top layer. An oxidation resistant conductive layer and a further oxide layer are formed in the recess. The conductive layer is planarized to expose the oxide or oxide/nitride layer. The oxide layers are then etched to expose the top surface and vertical portions of the conductive layer. A dielectric layer is formed to overlie the storage node electrode. A cell plate electrode is fabricated to overlie the dielectric layer.
摘要翻译：集成电路结构包括数字线和适于作为存储单元电容器的一部分的电极，并且包括介于导电插塞和抗氧化层之间的阻挡层。绝缘层在电介质层的沉积和退火期间保护阻挡层的侧壁。该方法包括形成凹入绝缘层中的导电插塞。阻挡层形成在凹部和顶层中。在凹部中形成抗氧化导电层和另外的氧化物层。将导电层平坦化以暴露氧化物或氧化物/氮化物层。然后蚀刻氧化物层以暴露导电层的顶表面和垂直部分。形成介电层以覆盖存储节点电极。制造电池板电极以覆盖电介质层。

4. 发明授权

US07385240B2 Storage cell capacitor compatible with high dielectric constant materials 有权
标题翻译：存储单元电容与高介电常数材料兼容
公开(公告)号：US07385240B2
公开(公告)日：2008-06-10
申请号：US11276639
申请日：2006-03-08
申请人： Pierre C. Fazan , Viju K. Mathews
发明人： Pierre C. Fazan , Viju K. Mathews
IPC分类号： H01L27/108
CPC分类号： H01L27/11502 , H01L21/7687 , H01L27/10817 , H01L27/10852 , H01L27/10855 , H01L27/10885 , H01L27/11507 , H01L28/40 , H01L28/55 , H01L28/60 , H01L28/65 , H01L28/75 , H01L28/91 , Y10T29/435 , Y10T29/49165
摘要： An integrated circuit structure includes a digit line and an electrode adapted to be part of a storage cell capacitor and includes a barrier layer interposed between a conductive plug and an oxidation resistant layer. An insulative layer protects sidewalls of the barrier layer during deposition and anneal of a dielectric layer. The method includes forming the conductive plug recessed in an insulative layer. The barrier layer is formed in the recess and the top layer. An oxidation resistant conductive layer and a further oxide layer are formed in the recess. The conductive layer is planarized to expose the oxide or oxide/nitride layer. The oxide layers are then etched to expose the top surface and vertical portions of the conductive layer. A dielectric layer is formed to overlie the storage node electrode. A cell plate electrode is fabricated to overlie the dielectric layer.
摘要翻译：集成电路结构包括数字线和适于作为存储单元电容器的一部分的电极，并且包括介于导电插塞和抗氧化层之间的阻挡层。绝缘层在电介质层的沉积和退火期间保护阻挡层的侧壁。该方法包括形成凹入绝缘层中的导电插塞。阻挡层形成在凹部和顶层中。在凹部中形成抗氧化导电层和另外的氧化物层。将导电层平坦化以暴露氧化物或氧化物/氮化物层。然后蚀刻氧化物层以暴露导电层的顶表面和垂直部分。形成介电层以覆盖存储节点电极。制造电池板电极以覆盖电介质层。

5. 发明授权

US06861726B2 Apparatus having trench isolation structure with reduced isolation pad height and edge spacer 失效
标题翻译：具有沟槽隔离结构的设备具有降低的隔离垫高度和边缘间隔件
公开(公告)号：US06861726B2
公开(公告)日：2005-03-01
申请号：US09386646
申请日：1999-08-31
申请人： Pierre C. Fazan , Gurtej S. Sandhu
发明人： Pierre C. Fazan , Gurtej S. Sandhu
IPC分类号： H01L21/762 , H01L21/8234 , H01L29/00 , H01L29/76
CPC分类号： H01L21/823481 , H01L21/76224
摘要： A microelectronic device includes a field oxide isolation pad which extends from a trench formed in a microelectronic substrate by a height which is less than approximately two times the height of a gate structure formed on the microelectronic substrate. Spacers are formed around the gate structures, although little or no spacer forms around the isolation pad. The microelectronic device is fabricated by forming a gate oxide layer on a microelectronic substrate, depositing a first gate layer on the gate oxide layer, forming a trench extending through the gate layer, the gate oxide layer and into the substrate, filling the trench with a field oxide, planarizing the field oxide, recessing the field oxide to a level above the microelectronic substrate and below an upper level of the first gate layer, forming a second gate layer over the recessed field oxide and the first gate layer, forming a conductive layer over the second gate layer, forming gate structures in the conductive layer, the first and second gate layers, and the gate oxide layer, and forming spacers adjacent the gate structures.
摘要翻译：微电子器件包括场氧化物隔离垫，其从在微电子衬底中形成的沟槽延伸的高度小于形成在微电子衬底上的栅极结构的高度的大约两倍。隔板形成在栅极结构周围，尽管在隔离垫周围几乎没有或没有间隔件形成。微电子器件通过在微电子衬底上形成栅极氧化层，在栅极氧化层上淀积第一栅极层，形成延伸穿过栅极层的沟槽，栅极氧化层并进入衬底，并用场氧化物，使场氧化物平坦化，使场氧化物凹陷到微电子衬底上方的水平并且低于第一栅极层的上电平，在凹陷场氧化物和第一栅极层上形成第二栅极层，形成导电层在第二栅极层上形成导电层中的栅极结构，第一和第二栅极层以及栅极氧化物层，以及在栅极结构附近形成间隔物。

6. 发明授权

US06835634B1 Streamlined field isolation process 失效
标题翻译：流线型现场隔离流程
公开(公告)号：US06835634B1
公开(公告)日：2004-12-28
申请号：US09037945
申请日：1998-03-10
申请人： Pierre C. Fazan , Viju K. Mathews , Nanseng Jeng
发明人： Pierre C. Fazan , Viju K. Mathews , Nanseng Jeng
IPC分类号： H01L21762
CPC分类号： H01L21/76202
摘要： A field isolation process performed on a silicon wafer is carried out by high pressure oxidation. Using oxygen rather than water vapor as the oxidant substantially eliminates nitride inclusions via the Kooi effect. Preferred high pressure field oxidation processes simplify all CMOS flows by eliminating the need for sacrificial oxide growth and removal steps.
摘要翻译：通过高压氧化进行在硅晶片上进行的场隔离处理。使用氧气而不是水蒸气作为氧化剂，基本上消除了通过Kooi效应的氮化物夹杂物。优选的高压场氧化工艺通过消除对牺牲氧化物生长和去除步骤的需要来简化所有CMOS流程。

7. 发明授权

US06214687B1 Method of forming a capacitor and a capacitor construction 有权
公开(公告)号：US06214687B1
公开(公告)日：2001-04-10
申请号：US09251387
申请日：1999-02-17
申请人： Gurtej Sandhu , Pierre C. Fazan
发明人： Gurtej Sandhu , Pierre C. Fazan
IPC分类号： H01L2120
CPC分类号： H01L28/87 , H01L21/3185
摘要： A method of forming a capacitor includes, a) providing a node to which electrical connection to a first capacitor plate is to be made; b) then, providing a finned lower capacitor plate in ohmic electrical connection with the node using no more than one photomasking step; and c) providing a capacitor dielectric layer and a conductive second capacitor plate layer over the conductive layer. Such is preferably accomplished by, i) providing a layer of conductive material outwardly of the node; ii) providing a first masking layer over the conductive material layer; iii) etching a first opening into the first masking layer over the node; iv) providing a second masking layer over the first masking layer to a thickness which less than completely fills the first opening; v) anisotropically etching the second masking layer to define a spacer received laterally within the first opening and thereby defining a second opening relative to the first masking layer which is smaller than the first opening; vi) after said anisotropically etching, etching unmasked first masking layer material away; vii) after said anisotropically etching, etching through the conductive material layer to extend the second opening to the node, the node and conductive layer being electrically isolated from one another after the conductive material layer etching; viii) plugging the extended second opening with an electrically conductive plugging material, the plugging material electrically interconnecting the node and conductive layer. Novel capacitor constructions are also disclosed.

8. 发明授权

US06198124B1 Method of forming a Ta2O5 dielectric layer, method of forming a capacitor having a Ta2O5 dielectric layer, and capacitor construction 失效
标题翻译：形成Ta 2 O 5介电层的方法，形成具有Ta 2 O 5介电层的电容器的方法和电容器结构
公开(公告)号：US06198124B1
公开(公告)日：2001-03-06
申请号：US09086389
申请日：1998-05-28
申请人： Gurtej S. Sandhu , Pierre C. Fazan
发明人： Gurtej S. Sandhu , Pierre C. Fazan
IPC分类号： H01L2972
CPC分类号： H01L28/56 , H01L28/40
摘要： A method of forming a dielectric layer includes, a) chemical vapor depositing a dielectric layer of Ta2O5 atop a substrate; and b) providing a predominately amorphous diffusion barrier layer over the Ta2O5 dielectric layer. A method of forming a capacitor includes, a) providing a node to which electrical connection to a capacitor is to be made; b) providing a first electrically conductive capacitor plate over the node; c) chemical vapor depositing a capacitor dielectric layer of Ta2O5 over the first electrically conductive capacitor plate; and d) providing a predominately amorphous diffusion barrier layer over the Ta2O5 dielectric layer. A capacitor construction is also disclosed. The preferred amorphous diffusion barrier layer is electrically conductive and constitutes a metal organic chemical vapor deposited TiCxNy Dz, where “x” is in the range of from 0.01 to 0.5, and “y” is in the range of from 0.99 to 0.5, and “z” is in the range of from 0 to 0.3, with the sum of “x”, “y” and “z” equalling about 1.0. Such is preferably deposited by utilizing a gaseous titanium organometallic precursor of the formula Ti(NR2)4, where R is selected from the group consisting of H and a carbon containing radical, and utilizing deposition conditions of from 200° C. to 600° C. and from 0.1 to 100 Torr.
摘要翻译：形成电介质层的方法包括：a）在衬底顶部化学气相沉积Ta 2 O 5的介电层; 和b）在Ta 2 O 5介电层上方提供主要的无定形扩散阻挡层。形成电容器的方法包括：a）提供与电容器进行电连接的节点; b）在节点上提供第一导电电容器板; c）在第一导电电容器板上化学气相沉积Ta 2 O 5的电容器电介质层; 以及d）在Ta 2 O 5介电层上提供主要的非晶扩散阻挡层。还公开了一种电容器结构。优选的非晶扩散阻挡层是导电的并且构成金属有机化学气相沉积TiC x N y D z，其中“x”在0.01至0.5的范围内，“y”在0.99至0.5的范围内，而“ z“在0至0.3的范围内，”x“，”y“和”z“之和等于约1.0。优选通过利用式Ti（NR 2）4的气态钛有机金属前体沉积，其中R选自H和含碳基团，并且利用200℃至600℃的沉积条件和0.1至100乇。

9. 发明授权

US6093615A Method of fabricating a contact structure having a composite barrier layer between a platinum layer and a polysilicon plug 失效
标题翻译：制造在铂层和多晶硅插塞之间具有复合阻挡层的接触结构的方法
公开(公告)号：US6093615A
公开(公告)日：2000-07-25
申请号：US290655
申请日：1994-08-15
申请人： Paul J. Schuele , Pierre C. Fazan
发明人： Paul J. Schuele , Pierre C. Fazan
IPC分类号： H01L21/8242 , H01L23/522 , H01L21/20
CPC分类号： H01L27/10852 , H01L23/5226 , H01L2924/0002
摘要： This invention is a process for forming an effective titanium nitride barrier layer between the upper surface of a polysilicon plug formed in thick dielectric layer and a platinum lower capacitor plate in a dynamic random access memory which is being fabricated on a silicon wafer. The barrier layer process begins by etching the upper surface of the polysilicon plug using a selective polysilicon etch until it is recessed at least 1000 .ANG. below the upper surface of the thick dielectric layer. Using a collimated sputter source, a titanium layer having a thickness of 100-500 .ANG. is deposited over the surface of the in-process wafer, thus covering the upper surfaces of the polysilicon plugs. A layer of amorphous titanium carbonitride having a thickness of 100-300 .ANG. is then deposited via low-pressure chemical vapor deposition. This is followed by the deposition of a reactively sputtered titanium nitride layer having a thickness of 1000-2000 .ANG.. The wafer is then planarized to remove the titanium, titanium carbonitride and titanium nitride, except that which is in the recesses on top of the silicon plugs. The wafer is then annealed in nitrogen to react the titanium layer with the silicon on the upper surfaces of the plugs to form titanium silicide. A platinum layer is then deposited and patterned to form lower capacitor electrodes which are electrically coupled to the polysilicon plugs through the titanium silicide, titanium nitride and titanium carbonitride layers.
摘要翻译：本发明是一种在制造在硅晶片上的动态随机存取存储器中形成厚电介质层形成的多晶硅插塞的上表面和铂下电容器板之间形成有效的氮化钛阻挡层的工艺。阻挡层工艺通过使用选择性多晶硅蚀刻蚀刻多晶硅插塞的上表面开始，直到其在厚电介质层的上表面下方至少凹入1000个ANGSTROM。使用准直的溅射源，在工作晶片的表面上沉积厚度为100-500的钛层，从而覆盖多晶硅插塞的上表面。然后通过低压化学气相沉积沉积厚度为100-300安培的无定形碳氮化钛层。随后沉积厚度为1000-2000安培的反应溅射的氮化钛层。然后将晶片平坦化以除去钛，碳氮化钛和氮化钛，除了位于硅插头顶部的凹槽中。然后将晶片在氮气中退火以使钛层与插塞的上表面上的硅反应形成硅化钛。然后沉积铂层并图案化以形成较低电容器电极，其通过硅化钛，氮化钛和碳氮化钛层电耦合到多晶硅插塞。

10. 发明授权

US6001675A Method of forming a thin film transistor 失效
公开(公告)号：US6001675A
公开(公告)日：1999-12-14
申请号：US872789
申请日：1997-06-10
申请人： Gurtej S. Sandhu , Shubneesh Batra , Pierre C. Fazan
发明人： Gurtej S. Sandhu , Shubneesh Batra , Pierre C. Fazan
IPC分类号： H01L21/336 , H01L21/77 , H01L21/84 , H01L29/04 , H01L29/786
CPC分类号： H01L29/78678 , H01L27/1214 , H01L29/04 , H01L29/6675 , H01L29/66757 , H01L29/66765 , H01L29/78672 , H01L29/78675
摘要： A method of forming a thin film transistor relative to a substrate includes, a) providing a thin film transistor layer of polycrystalline material on a substrate, the polycrystalline material comprising grain boundaries; b) providing a fluorine containing layer adjacent the polycrystalline thin film layer; c) annealing the fluorine containing layer at a temperature and for a time period which in combination are effective to drive fluorine from the fluorine containing layer into the polycrystalline thin film layer and incorporate fluorine within the grain boundaries to passivate said grain boundaries; and d) providing a transistor gate operatively adjacent the thin film transistor layer. The thin film transistor can be fabricated to be bottom gated or top gated. A buffering layer can be provided intermediate the thin film transistor layer and the fluorine containing layer, with the buffering layer being transmissive of fluorine from the fluorine containing layer during the annealing. Preferably, the annealing temperature is both sufficiently high to drive fluorine from the fluorine containing layer into the polycrystalline thin film layer and incorporate fluorine within the grain boundaries to passivate said grain boundaries, but sufficiently low to prevent chemical reaction of the fluorine containing layer with the polycrystalline thin film layer.

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