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1. 发明授权

US07705383B2 Integrated circuitry for semiconductor memory 失效
标题翻译：半导体存储器的集成电路
公开(公告)号：US07705383B2
公开(公告)日：2010-04-27
申请号：US08530661
申请日：1995-09-20
申请人： Brent Keeth , Pierre C. Fazan
发明人： Brent Keeth , Pierre C. Fazan
IPC分类号： H01L27/108
CPC分类号： H01L27/10888 , H01L27/105 , H01L27/108 , H01L27/10811
摘要： Processes are disclosed which facilitate improved high-density memory circuitry, most preferably dynamic random access memory (DRAM) circuitry. A semiconductor memory device includes i) a total of no more than 68,000,000 functional and operably addressable memory cells arranged in multiple memory arrays formed on a semiconductor die; and ii) circuitry formed on the semiconductor die permitting data to be written to and read from one or more of the memory cells, at least one of the memory arrays containing at least 100-square microns of continuous die surface area having at least 128 of the functional and operably addressable memory cells, more preferably, at least 100 square microns of continuous die surface area having at least 170 of the functional and operably addressable memory cells.
摘要翻译：公开了促进改进的高密度存储器电路，最优选动态随机存取存储器（DRAM）电路的方法。半导体存储器件包括i）总共不超过68,000,000个功能和可操作地寻址的存储器单元，布置在形成在半导体管芯上的多个存储器阵列中; 以及ii）形成在所述半导体管芯上的电路，允许将数据写入到所述存储器单元中的一个或多个存储单元并从其读取，所述存储器阵列中的至少一个包含至少100平方微米的连续管芯表面区域，功能和可操作寻址的存储器单元，更优选至少100平方微米的具有至少170个功能和可操作寻址的存储单元的连续管芯表面区域。

2. 发明授权

US06703656B2 Semiconductor memory circuitry including die sites sized for 256M to 275M memory cells in a 12″ wafer 失效
标题翻译：半导体存储器电路包括尺寸为12英寸晶圆中的256M至275M存储单元的模具位置
公开(公告)号：US06703656B2
公开(公告)日：2004-03-09
申请号：US09917844
申请日：2001-07-26
申请人： Brent Keeth , Pierre C. Fazan
发明人： Brent Keeth , Pierre C. Fazan
IPC分类号： H01L2708
CPC分类号： H01L27/105 , H01L27/108 , H01L27/10811 , Y10T29/49121
摘要： Processes are disclosed which facilitate improved high-density memory circuitry, most preferably dynamic random access memory (DRAM) circuitry. In accordance with aspects of the invention, considerably greater numbers of die sites per wafer are achieved for 6-inch, 8-inch and 12-inch wafers for 4M, 16M, 64M and 256M integration levels. Further, a semiconductor memory device includes i) a plurality of functional and operably addressable memory cells arranged in multiple memory arrays formed on a semiconductor die; and ii) circuitry formed on the semiconductor die permitting data to be written to and read from one or more of the memory cells, at least one of the memory arrays containing at least 100 square microns of continuous die surface area having at least 170 of the functional and operably addressable memory cells.
摘要翻译：公开了促进改进的高密度存储器电路，最优选动态随机存取存储器（DRAM）电路的方法。根据本发明的方面，对于用于4M，16M，64M和256M积分级别的6英寸，8英寸和12英寸晶片，实现了相当大数量的每个晶片的晶片位置。此外，半导体存储器件包括：i）布置在形成在半导体管芯上的多个存储器阵列中的多个功能和可操作地寻址的存储器单元; 以及ii）形成在所述半导体管芯上的电路，允许将数据写入到所述存储器单元中的一个或多个存储单元并从其读取，所述存储器阵列中的至少一个包含至少100平方微米的连续管芯表面区域，其具有至少170个功能和可操作地寻址的存储单元。

3. 发明申请

US20120044752A1 HIGH DENSITY INTEGRATED CIRCUITRY FOR SEMICONDUCTOR MEMORY 失效
标题翻译：高密度集成电路用于半导体存储器
公开(公告)号：US20120044752A1
公开(公告)日：2012-02-23
申请号：US13285182
申请日：2011-10-31
申请人： Brent Keeth , Pierre C. Fazan
发明人： Brent Keeth , Pierre C. Fazan
IPC分类号： G11C11/24
CPC分类号： H01L27/10888 , H01L27/105 , H01L27/108 , H01L27/10811
摘要： Processes are disclosed which facilitate improved high-density memory circuitry, most preferably dynamic random access memory (DRAM) circuitry. A semiconductor memory device includes i) a total of no more than 68,000,000 functional and operably addressable memory cells arranged in multiple memory arrays formed on a semiconductor die; and ii) circuitry formed on the semiconductor die permitting data to be written to and read from one or more of the memory cells. At least one of the memory arrays contains at least 100-square microns of continuous die surface area having at least 128 of the functional and operably addressable memory cells. More preferably, at least 100 square microns of continuous die surface area have at least 170 of the functional and operably addressable memory cells.
摘要翻译：公开了促进改进的高密度存储器电路，最优选动态随机存取存储器（DRAM）电路的方法。半导体存储器件包括i）总共不超过68,000,000个功能和可操作地寻址的存储器单元，布置在形成在半导体管芯上的多个存储器阵列中; 以及ii）形成在所述半导体管芯上的电路，允许将数据写入到所述存储器单元中的一个或多个存储单元并从其读取。存储器阵列中的至少一个包含至少100平方微米的具有至少128个功能和可操作寻址的存储器单元的连续管芯表面区域。更优选地，至少100平方微米的连续管芯表面区域具有至少170个功能和可操作寻址的存储器单元。

4. 发明申请

US20100149855A1 INTEGRATED CIRCUITRY FOR SEMICONDUCTOR MEMORY 失效
标题翻译：集成电路用于半导体存储器
公开(公告)号：US20100149855A1
公开(公告)日：2010-06-17
申请号：US12713673
申请日：2010-02-26
申请人： Brent Keeth , Pierre C. Fazan
发明人： Brent Keeth , Pierre C. Fazan
IPC分类号： G11C11/24 , G11C7/00
CPC分类号： H01L27/10888 , H01L27/105 , H01L27/108 , H01L27/10811
摘要： Processes are disclosed which facilitate improved high-density memory circuitry, most preferably dynamic random access memory (DRAM) circuitry. A semiconductor memory device includes i) a total of no more than 68,000,000 functional and operably addressable memory cells arranged in multiple memory arrays formed on a semiconductor die; and ii) circuitry formed on the semiconductor die permitting data to be written to and read from one or more of the memory cells, at least one of the memory arrays containing at least 100-square microns of continuous die surface area having at least 128 of the functional and operably addressable memory cells, more preferably, at least 100 square microns of continuous die surface area having at least 170 of the functional and operably addressable memory cells.
摘要翻译：公开了促进改进的高密度存储器电路，最优选动态随机存取存储器（DRAM）电路的方法。半导体存储器件包括i）总共不超过68,000,000个功能和可操作地寻址的存储器单元，布置在形成在半导体管芯上的多个存储器阵列中; 以及ii）形成在所述半导体管芯上的电路，允许将数据写入到所述存储器单元中的一个或多个存储单元并从其读取，所述存储器阵列中的至少一个包含至少100平方微米的连续管芯表面区域，功能和可操作寻址的存储器单元，更优选至少100平方微米的具有至少170个功能和可操作寻址的存储单元的连续管芯表面区域。

5. 发明授权

US07009232B2 Semiconductor memory circuitry including die sites sized for 256M to 275M memory cells in an 8-inch wafer 失效
标题翻译：半导体存储器电路包括尺寸为8英寸晶圆中的256M至275M存储单元的模具座
公开(公告)号：US07009232B2
公开(公告)日：2006-03-07
申请号：US09915508
申请日：2001-07-26
申请人： Brent Keeth , Pierre C. Fazan
发明人： Brent Keeth , Pierre C. Fazan
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L27/105 , H01L27/108 , H01L27/10811 , Y10T29/49121
摘要： Processes are disclosed which facilitate improved high-density memory circuitry, most preferably dynamic random access memory (DRAM) circuitry. In accordance with aspects of the invention, considerably greater numbers of die sites per wafer are achieved for 6-inch, 8-inch and 12-inch wafers for 4M, 16M, 64M and 256M integration levels. Further, a semiconductor memory device includes i) a plurality of functional and operably addressable memory cells arranged in multiple memory arrays formed on a semiconductor die; and ii) circuitry formed on the semiconductor die permitting data to be written to and read from one or more of the memory cells, at least one of the memory arrays containing at least 100 square microns of continuous die surface area having at least 170 of the functional and operably addressable memory cells.
摘要翻译：公开了促进改进的高密度存储器电路，最优选动态随机存取存储器（DRAM）电路的方法。根据本发明的方面，对于用于4M，16M，64M和256M积分级别的6英寸，8英寸和12英寸晶片，实现了相当大数量的每个晶片的晶片位置。此外，半导体存储器件包括：i）布置在形成在半导体管芯上的多个存储器阵列中的多个功能和可操作地寻址的存储器单元; 以及ii）形成在所述半导体管芯上的电路，允许将数据写入到所述存储器单元中的一个或多个存储单元并从其读取，所述存储器阵列中的至少一个包含至少100平方微米的连续管芯表面区域，其具有至少170个功能和可操作地寻址的存储单元。

6. 发明授权

US06900493B2 Semiconductor memory circuitry 失效
标题翻译：半导体存储器电路
公开(公告)号：US06900493B2
公开(公告)日：2005-05-31
申请号：US10305312
申请日：2002-11-26
申请人： Brent Keeth , Pierre C. Fazan
发明人： Brent Keeth , Pierre C. Fazan
IPC分类号： H01L27/105 , H01L27/108
CPC分类号： H01L27/105 , H01L27/108 , H01L27/10811 , Y10T29/49121
摘要： Processes are disclosed which facilitate improved high-density memory circuitry, most preferably dynamic random access memory (DRAM) circuitry. Considerably greater numbers of die sites per wafer are achieved for 6-inch, 8-inch and 12-inch wafers for 4M, 16M, 64M, and 256M integration levels. Further, an integrated circuit includes a semiconductor die, a plurality of functional and operably addressable memory cells arranged in at least one array formed on the semiconductor die, and circuitry formed on the semiconductor die and coupled to the memory cells for permitting data to be written to and read from the memory cells, wherein at least one area of 100 square microns of continuous surface area of the die has at least 170 of the memory cells.
摘要翻译：公开了促进改进的高密度存储器电路，最优选动态随机存取存储器（DRAM）电路的方法。对于4M，16M，64M和256M集成度的6英寸，8英寸和12英寸晶圆，可实现每片晶圆数量更多的裸片。此外，集成电路包括半导体管芯，布置在形成在半导体管芯上的至少一个阵列中的多个功能和可操作地寻址的存储器单元，以及形成在半导体管芯上并耦合到存储器单元以允许写入数据的电路从存储器单元读取并且从存储器单元读取，其中模具的100平方微米的连续表面积的至少一个区域具有至少170个存储单元。

7. 发明授权

US6107137A Method of forming a capacitor 有权
标题翻译：形成电容器的方法
公开(公告)号：US6107137A
公开(公告)日：2000-08-22
申请号：US205580
申请日：1998-12-04
申请人： Pierre C. Fazan , Brent Keeth
发明人： Pierre C. Fazan , Brent Keeth
IPC分类号： H01L21/02 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10852 , H01L27/10817 , H01L28/40 , Y10S438/919
摘要： A method of forming a capacitor includes, a) providing a series of alternating first and second layers of semiconductive material over a node location, a first of the first and second layers having an average conductivity enhancing dopant concentration of greater than about 5.times.10.sup.19 ions/cm.sup.3, a second of the first and second layers having an average conductivity enhancing dopant concentration from 0 ions/cm.sup.3 to about 5.times.10.sup.19 ions/cm.sup.3, at least one of the first and second layers being selectively etchable relative to the other of the first and second layers; b) providing a contact opening through the first and second ii layers of semiconductive material to the node location; c) providing an electrically conductive within the contact opening; d) masking and etching the conductive layer and the series of alternating layers to form a first capacitor plate; e) etching the one of the first and second layers at a faster rate than the other of the first and second layers to define lateral projections of the other of the first and second layers relative to the one of the first and second layers, the electrically conductive layer being in ohmic electrical connection with the first and second layers and lateral projections thereof; the conductive layer, the first and second layers and lateral projections thereof comprising the first capacitor plate; f) providing a capacitor dielectric layer over the conductive layer and the lateral projections; and g) providing a second capacitor plate over the capacitor dielectric layer.
摘要翻译：形成电容器的方法包括：a）在节点位置上提供一系列交替的交替的半导体材料层，所述第一和第二层中的第一层具有大于约5×1019离子/ cm3的平均导电性增强掺杂剂浓度所述第一和第二层中的第二层具有从0离子/ cm 3至约5×10 19离子/ cm 3的平均导电性增强掺杂剂浓度，所述第一层和第二层中的至少一个相对于所述第一层和第二层中的另一层可选择性地蚀刻 ; b）提供通过半导体材料的第一和第二ii层的接触开口到节点位置; c）在接触开口内提供导电的; d）掩蔽和蚀刻导电层和一系列交替层以形成第一电容器板; e）以比第一和第二层中的另一层更快的速率蚀刻第一层和第二层中的一个以限定第一和第二层中的另一层相对于第一层和第二层之一的横向突起，电导电层与第一和第二层及其横向突起欧姆电连接; 所述导电层，所述第一和第二层及其横向突起包括所述第一电容器板; f）在导电层和横向突起上提供电容器电介质层; 以及g）在所述电容器介电层上方提供第二电容器板。

8. 发明授权

US06288421B1 Semiconductor memory circuitry including die sites for 16M to 17M memory cells in an 8″ wafer 失效
标题翻译：半导体存储器电路包括用于8“晶圆中的16M至17M存储单元的裸片位置
公开(公告)号：US06288421B1
公开(公告)日：2001-09-11
申请号：US08929585
申请日：1997-09-15
申请人： Brent Keeth , Pierre C. Fazan
发明人： Brent Keeth , Pierre C. Fazan
IPC分类号： H01L27108
CPC分类号： H01L27/105 , H01L27/108 , H01L27/10811 , Y10T29/49121
摘要： Processes are disclosed which facilitate improved high density memory circuitry, most preferably dynamic random access memory (DRAM) circuitry. In accordance with aspects of the invention, considerably greater numbers of die sites per wafer are achieved for 6 inch, 8 inch and 12 inch wafers for 4 M, 16 M, 64 M and 256 M integration levels. Further, a semiconductor memory device includes, i) a plurality of functional and operably addressable memory cells arranged in multiple memory arrays formed on a semiconductor die; and ii) circuitry formed on the semiconductor die permitting data to be written to and read from one or more of the memory cells, at least one of the memory arrays containing at least 100 square microns of continuous die surface area having at least 170 of the functional and operably addressable memory cells.
摘要翻译：公开了促进改进的高密度存储器电路，最优选动态随机存取存储器（DRAM）电路的方法。根据本发明的方面，对于6M，16M，64M和256M积分级别的6英寸，8英寸和12英寸晶片，实现了相当大数量的每个晶片的晶片位置。此外，半导体存储器件包括：i）布置在形成在半导体管芯上的多个存储器阵列中的多个功能和可操作地寻址的存储单元; 以及ii）形成在所述半导体管芯上的电路，允许将数据写入到所述存储器单元中的一个或多个存储单元并从其读取，所述存储器阵列中的至少一个包含至少100平方微米的连续管芯表面区域，其具有至少170个功能和可操作地寻址的存储单元。

9. 发明授权

US06967369B1 Semiconductor memory circuitry 失效
标题翻译：半导体存储器电路
公开(公告)号：US06967369B1
公开(公告)日：2005-11-22
申请号：US08603471
申请日：1996-02-20
申请人： Brent Keeth , Pierre C. Fazan
发明人： Brent Keeth , Pierre C. Fazan
IPC分类号： H01L27/105 , H01L27/108
CPC分类号： H01L27/105 , H01L27/108 , H01L27/10811 , Y10T29/49121
摘要： Processes are disclosed which facilitate improved high-density memory circuitry, most preferably dynamic random access memory (DRAM) circuitry. In accordance with aspects of the invention, considerably greater numbers of die sites per wafer are achieved for 6-inch, 8-inch and 12-inch wafers for 4 M, 16 M, 64 M and 256 M integration levels. Further, a semiconductor memory device includes i) a plurality of functional and operably addressable memory cells arranged in multiple memory arrays formed on a semiconductor die; and ii) circuitry formed on the semiconductor die permitting data to be written to and read from one or more of the memory cells, at least one of the memory arrays containing at least 100 square microns of continuous die surface area having at least 170 of the functional and operably addressable memory cells.
摘要翻译：公开了促进改进的高密度存储器电路，最优选动态随机存取存储器（DRAM）电路的方法。根据本发明的方面，对于6M，16M，64M和256M积分级别的6英寸，8英寸和12英寸晶片，实现了相当大数量的每个晶片的晶片位置。此外，半导体存储器件包括：i）布置在形成在半导体管芯上的多个存储器阵列中的多个功能和可操作地寻址的存储器单元; 以及ii）形成在所述半导体管芯上的电路，允许将数据写入到所述存储器单元中的一个或多个存储单元并从其读取，所述存储器阵列中的至少一个包含至少100平方微米的连续管芯表面区域，其具有至少170个功能和可操作地寻址的存储单元。

10. 发明授权

US5869367A Method of forming a capacitor 失效
标题翻译：形成电容器的方法
公开(公告)号：US5869367A
公开(公告)日：1999-02-09
申请号：US820267
申请日：1997-03-17
申请人： Pierre C. Fazan , Brent Keeth
发明人： Pierre C. Fazan , Brent Keeth
IPC分类号： H01L21/02 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10852 , H01L27/10817 , H01L28/40 , Y10S438/919
摘要： A method of forming a capacitor includes, a) providing a series of alternating first and second layers of semiconductive material over a node location, a first of the first and second layers having an average conductivity enhancing dopant concentration of greater than about 5.times.10.sup.19 ions/cm.sup.3, a second of the first and second layers having an average conductivity enhancing dopant concentration from 0 ions/cm.sup.3 to about 5.times.10.sup.19 ions/cm.sup.3, at least one of the first and second layers being selectively etchable relative to the other of the first and second layers; b) providing a contact opening through the first and second layers of semiconductive material to the node location; c) providing an electrically conductive within the contact opening; d) masking and etching the conductive layer and the series of alternating layers to form a first capacitor plate; e) etching the one of the first and second layers at a faster rate than the other of the first and second layers to define lateral projections of the other of the first and second layers relative to the one of the first and second layers, the electrically conductive layer being in ohmic electrical connection with the first and second layers and lateral projections thereof; the conductive layer, the first and second layers and lateral projections thereof comprising the first capacitor plate; f) providing a capacitor dielectric layer over the conductive layer and the lateral projections; and g) providing a second capacitor plate over the capacitor dielectric layer.
摘要翻译：形成电容器的方法包括：a）在节点位置上提供一系列交替的交替的半导体材料层，所述第一和第二层中的第一层具有大于约5×1019离子/ cm3的平均导电性增强掺杂剂浓度所述第一和第二层中的第二层具有从0离子/ cm 3至约5×10 19离子/ cm 3的平均导电性增强掺杂剂浓度，所述第一层和第二层中的至少一个相对于所述第一层和第二层中的另一层可选择性地蚀刻 ; b）提供穿过半导体材料的第一和第二层的接触开口到节点位置; c）在接触开口内提供导电的; d）掩蔽和蚀刻导电层和一系列交替层以形成第一电容器板; e）以比第一和第二层中的另一层更快的速率蚀刻第一层和第二层中的一个以限定第一和第二层中的另一层相对于第一层和第二层之一的横向突起，电导电层与第一和第二层及其横向突起欧姆电连接; 所述导电层，所述第一和第二层及其横向突起包括所述第一电容器板; f）在导电层和横向突起上提供电容器电介质层; 以及g）在所述电容器介电层上方提供第二电容器板。

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