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1. 发明授权

US07245548B2 Techniques for reducing leakage current in memory devices 有权
标题翻译：降低存储器件泄漏电流的技术
公开(公告)号：US07245548B2
公开(公告)日：2007-07-17
申请号：US10900246
申请日：2004-07-27
申请人： Scott J. Derner , Venkatraghavan Bringivijayaraghavan , Abhay S. Dixit , Scot M. Graham , Stephen R. Porter , Ethan A. Williford
发明人： Scott J. Derner , Venkatraghavan Bringivijayaraghavan , Abhay S. Dixit , Scot M. Graham , Stephen R. Porter , Ethan A. Williford
IPC分类号： G11C7/00
CPC分类号： G11C11/412 , G11C11/4085
摘要： Techniques for reducing gate induced drain leakage (GIDL) in memory devices utilizing negative wordline architectures. More specifically, a method and apparatus are provided to determine whether any of the word lines in a section of a memory array are active. If any one of the plurality of word lines is active, each of the inactive word lines in the section are coupled to a negative voltage level. If none of the plurality of word lines is active, each of the plurality of word lines is coupled to ground to reduce GIDL.
摘要翻译：利用负字线架构降低存储器件漏极漏极泄漏（GIDL）的技术。更具体地，提供了一种方法和装置，用于确定存储器阵列的一部分中的任何字线是否是活动的。如果多个字线中的任一个是活动的，则该部分中的每个非活动字线被耦合到负电压电平。如果多个字线中没有一个是有效的，则多个字线中的每个字线被耦合到地来减少GIDL。

2. 发明授权

US06678186B2 Row decoded biasing of sense amplifier for improved one's margin 有权
标题翻译：读出放大器的行解码偏置，提高了余量
公开(公告)号：US06678186B2
公开(公告)日：2004-01-13
申请号：US10216990
申请日：2002-08-12
申请人： Patrick J. Mullarkey , Scott J. Derner
发明人： Patrick J. Mullarkey , Scott J. Derner
IPC分类号： G11C700
CPC分类号： G11C7/065
摘要： A structure and method to improve sense amplifier operation in memory circuits is provided. An illustrative method of the present invention includes taking the predecoded the row address signals (i.e. RA123 , LPHe , LPHo ) that run down the rowdriver seams in a memory array (peripheral circuitry), and decoding those address signals in the sense amplifier gaps. The decoding is done to fire a signal that runs up the sense amplifier gap and biases the sense amplifier to fire in one direction or the other.
摘要翻译：提供了一种用于改善存储器电路中的读出放大器操作的结构和方法。本发明的说明性方法包括对在存储器阵列（外围电路）中的行驱动器接缝运行的行地址信号（即，RA123 ，LPHe ，LPHo ）进行预解码，并对其进行解码读出放大器间隙中的地址信号。完成解码以激发上升读出放大器间隙的信号，并将读出放大器偏置在一个方向或另一个方向上发射。

3. 发明授权

US06611165B1 Antifuse circuit with improved gate oxide reliabilty 有权
标题翻译：防腐电路具有改善的栅极氧化物可靠性
公开(公告)号：US06611165B1
公开(公告)日：2003-08-26
申请号：US10178961
申请日：2002-06-25
申请人： Scott J. Derner , Casey R. Kurth
发明人： Scott J. Derner , Casey R. Kurth
IPC分类号： H01H3776
CPC分类号： G11C17/18
摘要： An apparatus and method for improving the gate oxide reliability of an antifuse circuit is provided by coupling the gate input of a protection device of the antifuse circuit to a voltage converter circuit. In a program mode, a first voltage is applied through the voltage converter circuit to the gate input of the protection device to limit the voltage passed to internal transistor devices, thus increasing their gate oxide reliability. In a normal operation mode, however, a second, lower voltage is applied through the voltage converter to the gate input of the protection device to remove the large voltage stress placed across the gate oxide of the protection device itself. The voltage converter may attenuate the first voltage to create the second voltage or it may switch its output between the first and second voltage levels.
摘要翻译：通过将反熔丝电路的保护装置的栅极输入耦合到电压转换器电路来提供用于提高反熔丝电路的栅极氧化可靠性的装置和方法。在编程模式中，通过电压转换器电路将第一电压施加到保护装置的栅极输入，以限制传递到内部晶体管器件的电压，从而增加其栅极氧化可靠性。然而，在正常操作模式中，通过电压转换器将第二较低电压施加到保护装置的栅极输入，以消除跨过保护装置本身的栅极氧化物放置的大的电压应力。电压转换器可以衰减第一电压以产生第二电压，或者它可以在第一和第二电压电平之间切换其输出。

4. 发明授权

US06556065B1 256 Meg dynamic random access memory 失效
公开(公告)号：US06556065B1
公开(公告)日：2003-04-29
申请号：US09621560
申请日：2000-07-21
申请人： Brent Keeth , Layne G. Bunker , Scott J. Derner
发明人： Brent Keeth , Layne G. Bunker , Scott J. Derner
IPC分类号： G05F1100
CPC分类号： G11C5/063 , G11C5/025 , G11C5/145 , G11C5/147 , G11C11/401 , G11C11/4074 , G11C11/4076 , G11C11/4097 , G11C11/4099 , G11C29/021 , G11C29/028 , G11C29/12 , G11C29/12005 , G11C29/46 , G11C29/787 , G11C2029/0407 , H01L27/10805 , H01L2224/4826 , H01L2224/73215 , H01L2924/1305 , H01L2924/13091 , H01L2924/00
摘要： A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. Sense amplifiers are positioned between adjacent rows in the individual arrays while row decoders are positioned between adjacent columns in the individual arrays. In certain of the gap cells, multiplexers are provided to transfer signals from I/O lines to data lines. A datapath is provided which, in addition to the foregoing, includes array I/O blocks, responsive to the datalines from each quadrant to output data to a data read mux, data buffers, and data driver pads. The write data path includes a data in buffer and data write muxes for providing data to the array I/O blocks. A power bus is provided which minimizes routing of externally supplied voltages, completely rings each of the array blocks, and provides gridded power distribution within each of the array blocks. A plurality of voltage supplies provide the voltages needed in the array and in the peripheral circuits. The power supplies are organized to match their power output to the power demand and to maintain a desired ratio of power production capability and decoupling capacitance. A powerup sequence circuit is provided to control the powerup of the chip. Redundant rows and columns are provided as is the circuitry necessary to logically replace defective rows and columns with operational rows and columns. Circuitry is also provided on chip to support various types of test modes.

5. 发明授权

US06400595B1 256 meg dynamic access memory 有权
标题翻译： 256兆动态存取存储器
公开(公告)号：US06400595B1
公开(公告)日：2002-06-04
申请号：US09620606
申请日：2000-07-20
申请人： Brent Keeth , Layne G. Bunker , Scott J. Derner
发明人： Brent Keeth , Layne G. Bunker , Scott J. Derner
IPC分类号： G11C502
CPC分类号： G11C5/063 , G11C5/025 , G11C5/145 , G11C5/147 , G11C11/401 , G11C11/4074 , G11C11/4076 , G11C11/4097 , G11C11/4099 , G11C29/021 , G11C29/028 , G11C29/12 , G11C29/12005 , G11C29/46 , G11C29/787 , G11C2029/0407 , H01L27/10805 , H01L2224/4826 , H01L2224/73215 , H01L2924/1305 , H01L2924/13091 , H01L2924/00
摘要： A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. A power bus is provided which minimizes routing of externally supplied voltages, completely rings each of the array blocks, and provides gridded power distribution within each of the array blocks. A plurality of voltage supplies provide the voltages needed in the array and in the peripheral circuits. The power supplies are organized to match their power output to the power demand and to maintain a desired ratio of power production capability and decoupling capacitance. Sense amplifiers are positioned between adjacent rows in the individual arrays while row decoders are positioned between adjacent columns in the individual arrays. A powerup sequence circuit is provided to control the powerup of the chip.
摘要翻译：一个256兆赫动态随机存取存储器由组成单独阵列的多个单元组成，阵列被组织成32兆赫阵列阵列，它们被组织成64兆象限。提供电源总线，其最小化外部提供的电压的路由，完全环绕每个阵列块，并且在每个阵列块内提供网格化的功率分配。多个电压源提供阵列和外围电路中所需的电压。电源组合以将其功率输出与功率需求相匹配，并保持所需的功率生产能力和去耦电容的比例。感测放大器位于各个阵列中的相邻行之间，而行解码器位于各个阵列中的相邻列之间。提供上电序列电路以控制芯片的上电。

6. 发明授权

US06236606B1 Row decoded biasing of sense amplifier for improved one's margin 有权
公开(公告)号：US06236606B1
公开(公告)日：2001-05-22
申请号：US09517028
申请日：2000-03-02
申请人： Patrick J. Mullarkey , Scott J. Derner
发明人： Patrick J. Mullarkey , Scott J. Derner
IPC分类号： G11C702
CPC分类号： G11C7/065
摘要： A structure and method to improve sense amplifier operation in memory circuits is provided. An illustrative method of the present invention includes taking the predecoded the row address signals (i.e. RA123 , LPHe , LPHo ) that run down the rowdriver seams in a memory array (peripheral circuitry), and decoding those address signals in the sense amplifier gaps. The decoding is done to fire a signal that runs up the sense amplifier gap and biases the sense amplifier to fire in one direction or the other. Exemplary embodiments of the present invention are as follows. One method of the present invention includes putting two small n-channel transistors in parallel with each of the cross-coupled n-channel transistors in the n-sense amplifier. The gates of the two small n-channel transistors are initially low. Then, depending on the intended direction for biasing the sense amplifier, the gate of one of the small n-channel transistors would go to DVC2 until the p-sense amplifier fires. The reference digitline (DIG*) coupled in parallel with the fired small n-channel is pulled to ground harder, or assisted to ground faster than the other digitline (DIG) with the effect of favoring a “sensed” logical “1” on the latter. The biasing of the sense amplifier is set so that a zero can still be read out correctly. In result, where a detected signal voltage difference between the digitline (DIG) and the reference digitline (DIG*) is small, e.g., to the point where a normal sense amplifier will read either toward a logical “1” or a logical “0,” the biasing will cause the sense amplifier to read a logical “1”. A second method of the present invention includes using two separate n-sense amplifier bus lines (RNL*s) in each individual sense amplifier gap. One n-sense amplifier bus line (RNL*) is connected to each of the cross-coupled n-channel transistors in the n-sense amplifier. One of the separate n-sense amplifier bus lines (RNL*s) is biased greater than the other. When the n-sense amplifier fires, the digitline (DIG) favors sensing a logical “1”.

7. 发明授权

US07466618B2 Current limiting antifuse programming path 有权
标题翻译：限流反熔丝编程路径
公开(公告)号：US07466618B2
公开(公告)日：2008-12-16
申请号：US10930517
申请日：2004-08-31
申请人： Stephen R. Porter , Scott J. Derner
发明人： Stephen R. Porter , Scott J. Derner
IPC分类号： G11C17/18
CPC分类号： H01L23/5252 , G11C17/18 , H01L2924/0002 , H01L2924/00
摘要： Method and apparatus are provided for regulating an antifuse programming current by lightly doping an electrically connected region so that the resistance of the region responds in a non-linear manner to changes in voltage. In this way a variable resistor or a variably resistive transistor may be created which vary their resistance in response to an applied voltage and which may thereby limit a programming current while not limiting a lesser, reading current to a serially connected antifuse.
摘要翻译：提供了通过轻掺杂电连接区域来调节反熔丝编程电流的方法和装置，使得该区域的电阻以非线性方式响应电压变化。以这种方式，可以产生可变电阻器或可变电阻晶体管，其响应于施加的电压而改变其电阻，并且因此可限制编程电流，而不限制对串行连接的反熔丝的较小的读取电流。

8. 发明授权

US06859408B2 Current limiting antifuse programming path 有权
标题翻译：限流反熔丝编程路径
公开(公告)号：US06859408B2
公开(公告)日：2005-02-22
申请号：US10230637
申请日：2002-08-29
申请人： Stephen R. Porter , Scott J. Derner
发明人： Stephen R. Porter , Scott J. Derner
IPC分类号： G11C5/00 , G11C7/00 , G11C11/00 , G11C17/18 , H01L21/82 , H01L23/525
CPC分类号： H01L23/5252 , G11C17/18 , H01L2924/0002 , H01L2924/00
摘要： Method and apparatus for regulating an antifuse programming current by lightly doping an electrically connected region so that the resistance of the region responds in a non-linear manner to changes in voltage. In this way a variable resistor or a variably resistive transistor may be created which vary their resistance in response to an applied voltage and which may thereby limit a programming current while not limiting a lesser, reading current to a serially connected antifuse.
摘要翻译：用于通过轻掺杂电连接区域来调节反熔丝编程电流的方法和装置，使得该区域的电阻以非线性方式响应于电压变化。以这种方式，可以产生可变电阻器或可变电阻晶体管，其响应于施加的电压而改变其电阻，并且因此可限制编程电流，而不限制对串行连接的反熔丝的较小的读取电流。

9. 发明授权

US06834022B2 Partial array self-refresh 失效
标题翻译：部分阵列自刷新
公开(公告)号：US06834022B2
公开(公告)日：2004-12-21
申请号：US10717862
申请日：2003-11-18
申请人： Scott J. Derner , Casey R. Kurth , Daryl L. Habersetzer
发明人： Scott J. Derner , Casey R. Kurth , Daryl L. Habersetzer
IPC分类号： G11C700
CPC分类号： G11C11/40622 , G11C11/406
摘要： A memory device includes an address selection circuit to store addresses of selected rows of memory cells. During a refresh mode, only the memory cells of the selected rows are refreshed. The addresses of the selected rows can be stored automatically by the memory device during a memory operation mode or manually by a user during a programming mode.
摘要翻译：存储器件包括地址选择电路，用于存储存储器单元的选定行的地址。在刷新模式下，只刷新所选行的存储单元。所选择的行的地址可以在存储器操作模式期间由存储器设备自动存储，或者在编程模式期间由用户手动存储。

10. 发明授权

US06724238B2 Antifuse circuit with improved gate oxide reliability 有权
标题翻译：防腐电路具有改善的栅极氧化可靠性
公开(公告)号：US06724238B2
公开(公告)日：2004-04-20
申请号：US10449217
申请日：2003-05-29
申请人： Scott J. Derner , Casey R. Kurth
发明人： Scott J. Derner , Casey R. Kurth
IPC分类号： H01H3776
CPC分类号： G11C17/18
摘要： An apparatus and method for improving the gate oxide reliability of an antifuse circuit is provided by coupling the gate input of a protection device of the antiftise circuit to a voltage converter circuit. In a program mode, a first voltage is applied through the voltage converter circuit to the gate input of the protection device to limit the voltage passed to internal transistor devices, thus increasing their gate oxide reliability. In a normal operation mode, however, a second, lower voltage is applied through the voltage converter to the gate input of the protection device to remove the large voltage stress placed across the gate oxide of the protection device itself. The voltage converter may attenuate the first voltage to create the second voltage or it may switch its output between the first and second voltage levels.
摘要翻译：通过将反熔丝电路的保护装置的栅极输入耦合到电压转换器电路来提供用于提高反熔丝电路的栅极氧化可靠性的装置和方法。在编程模式中，通过电压转换器电路将第一电压施加到保护装置的栅极输入，以限制传递到内部晶体管器件的电压，从而增加其栅极氧化可靠性。然而，在正常操作模式中，通过电压转换器将第二较低电压施加到保护装置的栅极输入，以消除跨过保护装置本身的栅极氧化物放置的大的电压应力。电压转换器可以衰减第一电压以产生第二电压，或者它可以在第一和第二电压电平之间切换其输出。

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