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81. 发明授权

US08044448B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08044448B2
公开(公告)日：2011-10-25
申请号：US12508904
申请日：2009-07-24
申请人： Takeshi Kamigaichi , Fumitaka Arai
发明人： Takeshi Kamigaichi , Fumitaka Arai
IPC分类号： H01L27/108
CPC分类号： H01L27/0207 , G11C5/025 , G11C5/063 , H01L27/115 , H01L27/11519 , H01L27/11526 , H01L27/11551 , H01L27/11556 , H01L27/1203
摘要： A nonvolatile semiconductor memory device includes: a memory cell array region having memory cells connected in series; a control circuit region disposed below the memory cell array region; and an interconnection portion electrically connecting the control circuit region and the memory cell array region. The memory cell array region includes: a plurality of first memory cell regions having the memory cells; and a plurality of connection regions. The interconnection portion is provided in the connection regions. The first memory cell regions are provided at a first pitch in a first direction orthogonal to a lamination direction of the memory cell array region and the control circuit region. The connection regions are provided between the first memory cell regions mutually adjacent in the first direction, and at a second pitch in a second direction orthogonal to the lamination direction and the first direction.
摘要翻译：非易失性半导体存储器件包括：具有串联连接的存储单元的存储单元阵列区域; 设置在所述存储单元阵列区域下方的控制电路区域; 以及电连接控制电路区域和存储单元阵列区域的互连部分。存储单元阵列区域包括：具有存储单元的多个第一存储单元区域; 和多个连接区域。互连部分设置在连接区域中。第一存储单元区域在与存储单元阵列区域和控制电路区域的层叠方向正交的第一方向上以第一间距设置。连接区域设置在与第一方向相互相邻的第一存储单元区域和与层叠方向和第一方向正交的第二方向上的第二间距处。

82. 发明申请

US20110215473A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110215473A1
公开(公告)日：2011-09-08
申请号：US12886133
申请日：2010-09-20
申请人： Mitsuhiko Noda , Mitsuhiro Noguchi , Kenichi Fujii , Fumitaka Arai
发明人： Mitsuhiko Noda , Mitsuhiro Noguchi , Kenichi Fujii , Fumitaka Arai
IPC分类号： H01L23/532 , H01L21/768
CPC分类号： H01L21/768 , H01L23/532 , H01L2924/0002 , H01L2924/00
摘要： According to one embodiment, a semiconductor device includes a first contact, a second contact, and an intermediate interconnection. The first contact is made of a first conductive material. The second contact is made of a second conductive material. A lower end portion of the second contact is connected to an upper end portion of the first contact. The intermediate interconnection is made of a third conductive material and isolated from the first contact and the second contact. A lower face of the intermediate interconnection is positioned higher than a lower face of the first contact. An upper face of the intermediate interconnection is positioned lower than an upper face of the second contact. A diffusion coefficient of the first conductive material with respect to the second conductive material is lower than a diffusion coefficient of the third conductive material with respect to the second conductive material.
摘要翻译：根据一个实施例，半导体器件包括第一触点，第二触点和中间互连。第一接触由第一导电材料制成。第二接触由第二导电材料制成。第二触点的下端部连接到第一触点的上端部。中间互连由第三导电材料制成并且与第一接触和第二接触隔离。中间互连的下表面定位成高于第一触点的下表面。中间互连的上表面定位成低于第二触点的上表面。第一导电材料相对于第二导电材料的扩散系数低于第三导电材料相对于第二导电材料的扩散系数。

83. 发明授权

US08009474B2 Semiconductor storage device and read voltage correction method 失效
标题翻译：半导体存储器件和读取电压校正方法
公开(公告)号：US08009474B2
公开(公告)日：2011-08-30
申请号：US12775221
申请日：2010-05-06
申请人： Kiyohito Nishihara , Fumitaka Arai
发明人： Kiyohito Nishihara , Fumitaka Arai
IPC分类号： G11C11/34
CPC分类号： H01L27/105 , G11C16/0483 , G11C16/26 , G11C16/3427 , H01L27/115 , H01L27/11502 , H01L27/11509 , H01L27/11526
摘要： A semiconductor memory device comprises a semiconductor memory, a corrected voltage storage circuit which stores a corrected voltage produced by correcting a read voltage of the semiconductor memory, and a memory controller which reads the corrected voltage from the corrected voltage storage circuit and performs a read operation of the semiconductor memory using the corrected voltage.
摘要翻译：半导体存储器件包括：半导体存储器，存储通过校正半导体存储器的读取电压产生的校正电压的校正电压存储电路;以及从校正后的电压存储电路读取校正电压并进行读取操作的存储器控制器的半导体存储器。

84. 发明申请

US20100127320A1 NONVOLATILE SEMICONDUCTOR MEMORY 失效
标题翻译：非易失性半导体存储器
公开(公告)号：US20100127320A1
公开(公告)日：2010-05-27
申请号：US12618058
申请日：2009-11-13
申请人： Kiyohito Nishihara , Fumitaka Arai
发明人： Kiyohito Nishihara , Fumitaka Arai
IPC分类号： H01L29/792
CPC分类号： H01L29/42336 , H01L21/764 , H01L27/11521 , H01L27/11524 , H01L29/7881
摘要： Two diffusion layers are provided in an element area. A tunnel insulating film is provided on the surface of the element area between the two diffusion layers. A charge storage layer is provided on the tunnel insulating film. A first insulator provided on the upper surface of the charge storage layer. An inter-electrode insulating film provided on the first insulator, on the side surface of the charge storage layer in a first direction and on the isolation insulating film. And a control gate electrode extends in the first direction and covers the charge storage layer via the first insulator and the inter-electrode insulating film. The first insulator is thicker than the inter-electrode insulating film, and the inter-electrode insulating film has a first slit on the first insulator.
摘要翻译：在元件区域中设置两个扩散层。隧道绝缘膜设置在两个扩散层之间的元件区域的表面上。电荷存储层设置在隧道绝缘膜上。设置在电荷存储层的上表面上的第一绝缘体。一种电极间绝缘膜，设置在第一绝缘体上，在电荷存储层的第一方向的侧表面上以及隔离绝缘膜上。并且控制栅极电极沿第一方向延伸并且经由第一绝缘体和电极间绝缘膜覆盖电荷存储层。第一绝缘体比电极间绝缘膜厚，并且电极间绝缘膜在第一绝缘体上具有第一狭缝。

85. 发明申请

US20100052017A1 SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20100052017A1
公开(公告)日：2010-03-04
申请号：US12553496
申请日：2009-09-03
申请人： Atsuhiro SATO , Hiroyuki Nitta , Fumitaka Arai
发明人： Atsuhiro SATO , Hiroyuki Nitta , Fumitaka Arai
IPC分类号： H01L29/66 , H01L21/4763
CPC分类号： H01L27/11524 , H01L21/76816 , H01L27/11521
摘要： A semiconductor memory device includes a first block having first memory cells and first select transistors, a second block having second memory cells and second select transistors, and arranged adjacent to the first block in a first direction, the second select transistor being arranged to face the first select transistor and commonly having a diffusion region with the first select transistor, a first interconnection layer provided on the diffusion region between the first and second blocks and extending in a second direction, and a second interconnection layer having a first portion provided in contact with an upper portion of the first interconnection layer and extending to a portion outside the first interconnection layer, and a second portion extending in the second direction and connected to the first portion in a portion outside a portion on the first interconnection layer.
摘要翻译：半导体存储器件包括具有第一存储器单元和第一选择晶体管的第一块，具有第二存储单元和第二选择晶体管的第二块，并且沿第一方向布置成与第一块相邻，第二选择晶体管被布置为面对第一选择晶体管，并且通常具有与第一选择晶体管的扩散区，第一互连层，设置在第一和第二块之间的扩散区上并沿第二方向延伸;第二互连层，具有设置成与第一选择晶体管接触的第一部分第一互连层的上部并且延伸到第一互连层外部的部分，以及第二部分，其在第二方向上延伸并且在第一互连层上的部分外部的部分连接到第一部分。

86. 发明申请

US20100020608A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20100020608A1
公开(公告)日：2010-01-28
申请号：US12508904
申请日：2009-07-24
申请人： Takeshi KAMIGAICHI , Fumitaka Arai
发明人： Takeshi KAMIGAICHI , Fumitaka Arai
IPC分类号： G11C16/04 , G11C11/34
CPC分类号： H01L27/0207 , G11C5/025 , G11C5/063 , H01L27/115 , H01L27/11519 , H01L27/11526 , H01L27/11551 , H01L27/11556 , H01L27/1203
摘要： A nonvolatile semiconductor memory device includes: a memory cell array region having memory cells connected in series; a control circuit region disposed below the memory cell array region; and an interconnection portion electrically connecting the control circuit region and the memory cell array region. The memory cell array region includes: a plurality of first memory cell regions having the memory cells; and a plurality of connection regions. The interconnection portion is provided in the connection regions. The first memory cell regions are provided at a first pitch in a first direction orthogonal to a lamination direction of the memory cell array region and the control circuit region. The connection regions are provided between the first memory cell regions mutually adjacent in the first direction, and at a second pitch in a second direction orthogonal to the lamination direction and the first direction.
摘要翻译：非易失性半导体存储器件包括：具有串联连接的存储单元的存储单元阵列区域; 设置在所述存储单元阵列区域下方的控制电路区域; 以及电连接控制电路区域和存储单元阵列区域的互连部分。存储单元阵列区域包括：具有存储单元的多个第一存储单元区域; 和多个连接区域。互连部分设置在连接区域中。第一存储单元区域在与存储单元阵列区域和控制电路区域的层叠方向正交的第一方向上以第一间距设置。连接区域设置在与第一方向相互相邻的第一存储单元区域和与层叠方向和第一方向正交的第二方向上的第二间距处。

87. 发明授权

US07649777B2 Nonvolatile semiconductor memory cell matrix with divided write/erase, a method for operating the same, monolithic integrated circuits and systems 失效
标题翻译：具有划分写/擦除的非易失性半导体存储单元矩阵，其操作方法，单片集成电路和系统
公开(公告)号：US07649777B2
公开(公告)日：2010-01-19
申请号：US10903015
申请日：2004-08-02
申请人： Masayuki Ichige , Fumitaka Arai , Kikuko Sugimae
发明人： Masayuki Ichige , Fumitaka Arai , Kikuko Sugimae
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： H01L27/11568 , G11C11/005 , G11C16/0483 , G11C16/10 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A nonvolatile semiconductor memory includes a plurality of word lines WL; a plurality of bit lines BL; memory cell transistors having a charge storage layer arranged in the column whose charge storage state is controlled by one of the word lines; memory cell transistor rows MSGm, MSGn functioning as select gate lines by injecting a charge into the charge storage layer of a memory cell transistor to form an enhancement mode transistor. Any one of a first select gate transistor or a second transistor, or both may be formed by a memory cell transistor functioning as a select gate transistor.
摘要翻译：非易失性半导体存储器包括多个字线WL; 多个位线BL; 存储单元晶体管，具有布置在列中的电荷存储层，其电荷存储状态由一条字线控制; 存储单元晶体管行MSGm，MSGn通过将电荷注入到存储单元晶体管的电荷存储层中而用作选择栅极线，以形成增强型晶体管。第一选择晶体管或第二晶体管中的任何一个或两者可以由用作选择栅极晶体管的存储单元晶体管形成。

88. 发明授权

US07501678B2 Nonvolatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US07501678B2
公开(公告)日：2009-03-10
申请号：US11550636
申请日：2006-10-18
申请人： Fumitaka Arai , Masayuki Ichige
发明人： Fumitaka Arai , Masayuki Ichige
IPC分类号： H01L29/788 , H01L29/76
CPC分类号： H01L27/115 , G11C16/0408 , G11C16/26 , H01L27/11519
摘要： A nonvolatile semiconductor memory device includes a semiconductor substrate. Active regions are formed on the surface of the substrate, separated from one another by element separating regions and extend in a first direction. A first word line and a second word line extend in a second direction crossing the first direction. A pair of first select gate lines extend in the second direction between the first and second word lines. Memory cell transistors are each provided at each of intersections of the first and second word lines and the active regions on the surface of the substrate. First select gate transistors are each provided at each of intersections of the pair of first select gate lines and the active regions on the surface of the substrate. A first contact is provided between the pair of first select gate lines and contacts adjacent two of the active regions.
摘要翻译：非易失性半导体存储器件包括半导体衬底。活性区域形成在基板的表面上，通过元件分离区域彼此分开并沿第一方向延伸。第一字线和第二字线在与第一方向交叉的第二方向上延伸。一对第一选择栅极线在第一和第二字线之间沿第二方向延伸。存储单元晶体管分别设置在基板的表面上的第一和第二字线以及有源区的交点处。第一选择栅极晶体管分别设置在该对第一选择栅极线和基板表面上的有源区的交点处。在一对第一选择栅极线和邻近两个有源区之间的触点之间提供第一触点。

89. 发明授权

US07393748B2 Method of fabricating a semiconductor memory device 失效
标题翻译：制造半导体存储器件的方法
公开(公告)号：US07393748B2
公开(公告)日：2008-07-01
申请号：US11609614
申请日：2006-12-12
申请人： Fumitaka Arai , Toshiyuki Enda , Hiroyoshi Tanimoto , Naoki Kusunoki , Nobutoshi Aoki , Riichiro Shirota , Hiroshi Watanabe , Takamitsu Ishihara
发明人： Fumitaka Arai , Toshiyuki Enda , Hiroyoshi Tanimoto , Naoki Kusunoki , Nobutoshi Aoki , Riichiro Shirota , Hiroshi Watanabe , Takamitsu Ishihara
IPC分类号： H01L21/33
CPC分类号： H01L27/115 , H01L27/11519 , H01L27/11526 , H01L27/11529
摘要： A NAND cell unit is formed with an advanced gate forming process on a semiconductor layer of a first conductivity type, which is formed on a semiconductor substrate of the first conductivity type with an insulating film interposed therebetween. First impurity-doped layers of a second conductivity type are formed on the semiconductor layer, which serve as channel regions of the select gate transistors Bit line contact- and source line contact-use second impurity-doped layers of the first conductivity type are formed at bit line and source line contact portions, sidewalls of which are covered with an insulating film.
摘要翻译： NAND单元单元在第一导电类型的半导体层上形成有先进的栅极形成工艺，该第一导电类型的半导体层形成在第一导电类型的半导体衬底上，绝缘膜插入其间。第一导电类型的第一杂质掺杂层形成在用作选择栅晶体管的沟道区的半导体层上。第一导电类型的位线接触和源极接触用第二杂质掺杂层形成在位线和源极线接触部分，其侧壁被绝缘膜覆盖。

90. 发明授权

US07387934B2 Nonvolatile semiconductor memory and manufacturing method for the same 有权
标题翻译：非易失性半导体存储器及其制造方法相同
公开(公告)号：US07387934B2
公开(公告)日：2008-06-17
申请号：US11267331
申请日：2005-11-07
申请人： Yoshio Ozawa , Masayuki Tanaka , Fumitaka Arai
发明人： Yoshio Ozawa , Masayuki Tanaka , Fumitaka Arai
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115 , H01L27/11524 , H01L29/42324 , H01L29/7883
摘要： The memory cell matrix encompasses (a) a plurality device isolation films running along column direction, (b) first conductive layers arranged along row and column-directions, adjacent groups of the first conductive layers are isolated from each other by the device isolation film disposed between the adjacent groups, (c) lower inter-electrode dielectrics arranged respectively on crests of the corresponding first conductive layers, (d) an upper inter-electrode dielectric arranged on the lower inter-electrode dielectric made of insulating material different from the lower inter-electrode dielectrics, and (e) second conductive layers running along the row-direction, arranged on the upper inter-electrode dielectric.
摘要翻译：存储单元矩阵包括（a）沿着列方向延伸的多个器件隔离膜，（b）沿着行和列方向布置的第一导电层，相邻的第一导电层组通过设置隔离膜彼此隔离（c）分别布置在相应的第一导电层的顶部上的下部电极间电介质，（d）布置在由绝缘材料制成的下部电极间电介质上的上部电极间电介质， - 电极介质，和（e）布置在上部电极间电介质上的沿着行方向延伸的第二导电层。

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