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1. 发明授权

US08009474B2 Semiconductor storage device and read voltage correction method 失效
标题翻译：半导体存储器件和读取电压校正方法
公开(公告)号：US08009474B2
公开(公告)日：2011-08-30
申请号：US12775221
申请日：2010-05-06
申请人： Kiyohito Nishihara , Fumitaka Arai
发明人： Kiyohito Nishihara , Fumitaka Arai
IPC分类号： G11C11/34
CPC分类号： H01L27/105 , G11C16/0483 , G11C16/26 , G11C16/3427 , H01L27/115 , H01L27/11502 , H01L27/11509 , H01L27/11526
摘要： A semiconductor memory device comprises a semiconductor memory, a corrected voltage storage circuit which stores a corrected voltage produced by correcting a read voltage of the semiconductor memory, and a memory controller which reads the corrected voltage from the corrected voltage storage circuit and performs a read operation of the semiconductor memory using the corrected voltage.
摘要翻译：半导体存储器件包括：半导体存储器，存储通过校正半导体存储器的读取电压产生的校正电压的校正电压存储电路;以及从校正后的电压存储电路读取校正电压并进行读取操作的存储器控制器的半导体存储器。

2. 发明申请

US20100127320A1 NONVOLATILE SEMICONDUCTOR MEMORY 失效
标题翻译：非易失性半导体存储器
公开(公告)号：US20100127320A1
公开(公告)日：2010-05-27
申请号：US12618058
申请日：2009-11-13
申请人： Kiyohito Nishihara , Fumitaka Arai
发明人： Kiyohito Nishihara , Fumitaka Arai
IPC分类号： H01L29/792
CPC分类号： H01L29/42336 , H01L21/764 , H01L27/11521 , H01L27/11524 , H01L29/7881
摘要： Two diffusion layers are provided in an element area. A tunnel insulating film is provided on the surface of the element area between the two diffusion layers. A charge storage layer is provided on the tunnel insulating film. A first insulator provided on the upper surface of the charge storage layer. An inter-electrode insulating film provided on the first insulator, on the side surface of the charge storage layer in a first direction and on the isolation insulating film. And a control gate electrode extends in the first direction and covers the charge storage layer via the first insulator and the inter-electrode insulating film. The first insulator is thicker than the inter-electrode insulating film, and the inter-electrode insulating film has a first slit on the first insulator.
摘要翻译：在元件区域中设置两个扩散层。隧道绝缘膜设置在两个扩散层之间的元件区域的表面上。电荷存储层设置在隧道绝缘膜上。设置在电荷存储层的上表面上的第一绝缘体。一种电极间绝缘膜，设置在第一绝缘体上，在电荷存储层的第一方向的侧表面上以及隔离绝缘膜上。并且控制栅极电极沿第一方向延伸并且经由第一绝缘体和电极间绝缘膜覆盖电荷存储层。第一绝缘体比电极间绝缘膜厚，并且电极间绝缘膜在第一绝缘体上具有第一狭缝。

3. 发明授权

US07505312B2 Nonvolatile semiconductor memory device capable of controlling proximity effect due to coupling between adjacent charge storage layers 有权
标题翻译：能够通过相邻电荷存储层之间的耦合来控制邻近效应的非易失性半导体存储器件
公开(公告)号：US07505312B2
公开(公告)日：2009-03-17
申请号：US11447963
申请日：2006-06-07
申请人： Yasuhiko Matsunaga , Fumitaka Arai , Atsuhiro Sato , Makoto Sakuma , Masato Endo , Kiyohito Nishihara , Keiji Shuto , Naohisa Iino
发明人： Yasuhiko Matsunaga , Fumitaka Arai , Atsuhiro Sato , Makoto Sakuma , Masato Endo , Kiyohito Nishihara , Keiji Shuto , Naohisa Iino
IPC分类号： G11C16/10
CPC分类号： G11C16/3418 , G11C16/3427
摘要： There is disclosed a semiconductor integrated circuit device including a memory cell array having a plurality of blocks, a first non-volatile semiconductor memory cell which is arranged in the memory cell array and has an electric charge storage layer, and a second non-volatile semiconductor memory cell which is arranged in the memory cell array to be adjacent to the first non-volatile semiconductor memory cell and has an electric charge storage layer. Regular data writing is performed with respect to the second non-volatile semiconductor memory cell after regular data writing is carried out with respect to the first non-volatile semiconductor memory cell. Additional data writing is performed with respect to the first non-volatile semiconductor memory cell after regular data writing is carried out with respect to the second non-volatile semiconductor memory cell.
摘要翻译：公开了一种包括具有多个块的存储单元阵列的半导体集成电路器件，布置在存储单元阵列中并具有电荷存储层的第一非易失性半导体存储单元和第二非易失性半导体存储单元，布置在与第一非易失性半导体存储单元相邻的存储单元阵列中，并具有电荷存储层。在相对于第一非易失性半导体存储单元执行常规数据写入之后，相对于第二非易失性半导体存储单元执行正常数据写入。在相对于第二非易失性半导体存储单元执行常规数据写入之后，相对于第一非易失性半导体存储单元执行附加数据写入。

4. 发明申请

US20070177431A1 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US20070177431A1
公开(公告)日：2007-08-02
申请号：US11447963
申请日：2006-06-07
申请人： Yasuhiko Matsunaga , Fumitaka Arai , Atsuhiro Sato , Makoto Sakuma , Masato Endo , Kiyohito Nishihara , Keiji Shuto , Naohisa Iino
发明人： Yasuhiko Matsunaga , Fumitaka Arai , Atsuhiro Sato , Makoto Sakuma , Masato Endo , Kiyohito Nishihara , Keiji Shuto , Naohisa Iino
IPC分类号： G11C16/04
CPC分类号： G11C16/3418 , G11C16/3427
摘要： There is disclosed a semiconductor integrated circuit device including a memory cell array having a plurality of blocks, a first non-volatile semiconductor memory cell which is arranged in the memory cell array and has an electric charge storage layer, and a second non-volatile semiconductor memory cell which is arranged in the memory cell array to be adjacent to the first non-volatile semiconductor memory cell and has an electric charge storage layer. Regular data writing is performed with respect to the second non-volatile semiconductor memory cell after regular data writing is carried out with respect to the first non-volatile semiconductor memory cell. Additional data writing is performed with respect to the first non-volatile semiconductor memory cell after regular data writing is carried out with respect to the second non-volatile semiconductor memory cell.
摘要翻译：公开了一种包括具有多个块的存储单元阵列的半导体集成电路器件，布置在存储单元阵列中并具有电荷存储层的第一非易失性半导体存储单元和第二非易失性半导体存储单元，布置在与第一非易失性半导体存储单元相邻的存储单元阵列中，并具有电荷存储层。在相对于第一非易失性半导体存储单元执行常规数据写入之后，相对于第二非易失性半导体存储单元执行正常数据写入。在相对于第二非易失性半导体存储单元执行常规数据写入之后，相对于第一非易失性半导体存储单元执行附加数据写入。

5. 发明授权

US08072025B2 Non-volatile semiconductor storage device and method of manufacturing the same 有权
标题翻译：非易失性半导体存储装置及其制造方法
公开(公告)号：US08072025B2
公开(公告)日：2011-12-06
申请号：US12244174
申请日：2008-10-02
申请人： Kiyohito Nishihara , Fumitaka Arai
发明人： Kiyohito Nishihara , Fumitaka Arai
IPC分类号： H01L29/792
CPC分类号： H01L27/1203 , H01L27/11565 , H01L27/11568 , H01L27/11578 , H01L27/11582 , H01L29/792 , H01L29/7926
摘要： A first lamination part includes: a charge accumulation layer provided on the respective sidewalls of laminated first conductive layers and accumulating charges; and a first semiconductor layer provided in contact with the fourth insulation layer and formed to extend to the lamination direction. A second lamination part includes a second semiconductor layer provided in contact with the first semiconductor layer. A third lamination part includes: a plurality of first contact layers formed in contact with the respective second lamination part, extending to a first direction perpendicular to the lamination direction, and in line with each other along a second direction perpendicular to the first direction; and a plurality of contact plug layers formed in contact with any one of the first contact layers and extending to the lamination direction. The contact plug layers are arranged at different positions relative to each other in the first direction.
摘要翻译：第一层压部件包括：电荷累积层，设置在层叠的第一导电层的各个侧壁上并积累电荷; 以及第一半导体层，设置成与所述第四绝缘层接触并形成为向层叠方向延伸。第二层压部件包括与第一半导体层接触设置的第二半导体层。第三层压部件包括：多个第一接触层，其形成为与相应的第二层压部分接触，延伸到垂直于层叠方向的第一方向，并且沿着垂直于第一方向的第二方向彼此成直线; 以及多个接触塞层，其形成为与所述第一接触层中的任一个接触并延伸到层叠方向。接触塞层在第一方向上相对于彼此设置在不同的位置。

6. 发明申请

US20100214847A1 SEMICONDUCTOR STORAGE DEVICE AND READ VOLTAGE CORRECTION METHOD 失效
标题翻译：半导体存储器件和读取电压校正方法
公开(公告)号：US20100214847A1
公开(公告)日：2010-08-26
申请号：US12775221
申请日：2010-05-06
申请人： Kiyohito Nishihara , Fumitaka Arai
发明人： Kiyohito Nishihara , Fumitaka Arai
IPC分类号： G11C16/02 , G11C16/06
CPC分类号： H01L27/105 , G11C16/0483 , G11C16/26 , G11C16/3427 , H01L27/115 , H01L27/11502 , H01L27/11509 , H01L27/11526
摘要： A semiconductor memory device comprises a semiconductor memory, a corrected voltage storage circuit which stores a corrected voltage produced by correcting a read voltage of the semiconductor memory, and a memory controller which reads the corrected voltage from the corrected voltage storage circuit and performs a read operation of the semiconductor memory using the corrected voltage.
摘要翻译：半导体存储器件包括：半导体存储器，存储通过校正半导体存储器的读取电压产生的校正电压的校正电压存储电路;以及从校正后的电压存储电路读取校正电压并进行读取操作的存储器控制器的半导体存储器。

7. 发明授权

US07781807B2 Non-volatile semiconductor storage device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US07781807B2
公开(公告)日：2010-08-24
申请号：US11947008
申请日：2007-11-29
申请人： Kiyohito Nishihara , Fumitaka Arai
发明人： Kiyohito Nishihara , Fumitaka Arai
IPC分类号： H01L29/80
CPC分类号： H01L27/0688 , H01L21/8221 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11551
摘要： A three-dimensional non-volatile semiconductor storage device which realizes both increased packing density and improved performance is disclosed. According to one aspect, there is provided a non-volatile semiconductor storage device comprising a first non-volatile memory cell provided on a first insulator, which includes a first semiconductor layer, and a first gate stack provided above the first semiconductor layer and including a first charge storage layer and a first control gate electrode, and a second non-volatile memory cell provided above the first non-volatile memory cell, which includes a second semiconductor layer, and a second gate stack provided above the second semiconductor layer and including a second charge storage layer and a second control gate electrode, the second gate stack being positioned to be aligned with the first gate stack, and wherein the first control gate electrode functions as a back gate electrode to the second non-volatile memory cell.
摘要翻译：公开了一种三维非易失性半导体存储装置，其实现了增加的封装密度和改进的性能。根据一个方面，提供了一种非易失性半导体存储装置，包括设置在第一绝缘体上的第一非易失性存储单元，第一绝缘体包括第一半导体层，以及设置在第一半导体层上方的第一栅极堆叠，第一电荷存储层和第一控制栅电极，以及设置在第一非易失性存储单元上方的第二非易失性存储单元，其包括第二半导体层，以及设置在第二半导体层上方的第二栅极堆叠，第二电荷存储层和第二控制栅电极，第二栅极堆叠被定位成与第一栅极堆叠对准，并且其中第一控制栅电极用作到第二非易失性存储单元的背栅电极。

8. 发明授权

US08212308B2 Nonvolatile semiconductor flash memory 失效
标题翻译：非易失性半导体闪存
公开(公告)号：US08212308B2
公开(公告)日：2012-07-03
申请号：US12618058
申请日：2009-11-13
申请人： Kiyohito Nishihara , Fumitaka Arai
发明人： Kiyohito Nishihara , Fumitaka Arai
IPC分类号： H01L29/788
CPC分类号： H01L29/42336 , H01L21/764 , H01L27/11521 , H01L27/11524 , H01L29/7881
摘要： Two diffusion layers are provided in an element area. A tunnel insulating film is provided on the surface of the element area between the two diffusion layers. A charge storage layer is provided on the tunnel insulating film. A first insulator provided on the upper surface of the charge storage layer. An inter-electrode insulating film provided on the first insulator, on the side surface of the charge storage layer in a first direction and on the isolation insulating film. And a control gate electrode extends in the first direction and covers the charge storage layer via the first insulator and the inter-electrode insulating film. The first insulator is thicker than the inter-electrode insulating film, and the inter-electrode insulating film has a first slit on the first insulator.
摘要翻译：在元件区域中设置两个扩散层。隧道绝缘膜设置在两个扩散层之间的元件区域的表面上。电荷存储层设置在隧道绝缘膜上。设置在电荷存储层的上表面上的第一绝缘体。一种电极间绝缘膜，设置在第一绝缘体上，在电荷存储层的第一方向的侧表面上以及隔离绝缘膜上。并且控制栅极电极沿第一方向延伸并且经由第一绝缘体和电极间绝缘膜覆盖电荷存储层。第一绝缘体比电极间绝缘膜厚，并且电极间绝缘膜在第一绝缘体上具有第一狭缝。

9. 发明申请

US20090090959A1 NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：非挥发性半导体存储器件及其制造方法
公开(公告)号：US20090090959A1
公开(公告)日：2009-04-09
申请号：US12244174
申请日：2008-10-02
申请人： Kiyohito Nishihara , Fumitaka Arai
发明人： Kiyohito Nishihara , Fumitaka Arai
IPC分类号： H01L29/423 , H01L21/28
CPC分类号： H01L27/1203 , H01L27/11565 , H01L27/11568 , H01L27/11578 , H01L27/11582 , H01L29/792 , H01L29/7926
摘要： A first lamination part includes: a charge accumulation layer provided on the respective sidewalls of laminated first conductive layers and accumulating charges; and a first semiconductor layer provided in contact with the fourth insulation layer and formed to extend to the lamination direction. A second lamination part includes a second semiconductor layer provided in contact with the first semiconductor layer. A third lamination part includes: a plurality of first contact layers formed in contact with the respective second lamination part, extending to a first direction perpendicular to the lamination direction, and in line with each other along a second direction perpendicular to the first direction; and a plurality of contact plug layers formed in contact with any one of the first contact layers and extending to the lamination direction. The contact plug layers are arranged at different positions relative to each other in the first direction.
摘要翻译：第一层压部件包括：电荷累积层，设置在层叠的第一导电层的各个侧壁上并积累电荷; 以及第一半导体层，设置成与所述第四绝缘层接触并形成为向层叠方向延伸。第二层压部件包括与第一半导体层接触设置的第二半导体层。第三层压部件包括：多个第一接触层，其形成为与相应的第二层压部分接触，延伸到垂直于层叠方向的第一方向，并且沿着垂直于第一方向的第二方向彼此成直线; 以及多个接触塞层，其形成为与所述第一接触层中的任一个接触并延伸到层叠方向。接触塞层在第一方向上相对于彼此设置在不同的位置。

10. 发明申请

US20090003071A1 SEMICONDUCTOR STORAGE DEVICE AND READ VOLTAGE CORRECTION METHOD 审中-公开
标题翻译：半导体存储器件和读取电压校正方法
公开(公告)号：US20090003071A1
公开(公告)日：2009-01-01
申请号：US11850390
申请日：2007-09-05
申请人： Kiyohito NISHIHARA , Fumitaka Arai
发明人： Kiyohito NISHIHARA , Fumitaka Arai
IPC分类号： G11C16/06
CPC分类号： H01L27/105 , G11C16/0483 , G11C16/26 , G11C16/3427 , H01L27/115 , H01L27/11502 , H01L27/11509 , H01L27/11526
摘要： A semiconductor memory device comprises a semiconductor memory, a corrected voltage storage circuit which stores a corrected voltage produced by correcting a read voltage of the semiconductor memory, and a memory controller which reads the corrected voltage from the corrected voltage storage circuit and performs a read operation of the semiconductor memory using the corrected voltage.
摘要翻译：半导体存储器件包括：半导体存储器，存储通过校正半导体存储器的读取电压产生的校正电压的校正电压存储电路;以及从校正后的电压存储电路读取校正电压并进行读取操作的存储器控制器的半导体存储器。

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