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1. 发明申请

US20110303958A1 NONVOLATILE SEMICONDUCTOR MEMORY 有权
标题翻译：非易失性半导体存储器
公开(公告)号：US20110303958A1
公开(公告)日：2011-12-15
申请号：US13156702
申请日：2011-06-09
申请人： Kouji MATSUO , Toshiyuki Enda , Nobutoshi Aoki , Toshihiko Iinuma
发明人： Kouji MATSUO , Toshiyuki Enda , Nobutoshi Aoki , Toshihiko Iinuma
IPC分类号： H01L29/792 , H03K19/08 , H01L21/336
CPC分类号： H01L29/7926 , G11C13/0004 , G11C13/0007 , G11C13/0023 , G11C13/003 , G11C2213/18 , G11C2213/71 , G11C2213/75 , H01L27/11565 , H01L27/11568 , H01L27/24
摘要： According to one embodiment, a nonvolatile semiconductor memory includes control gates provided in an array form, the control gates passing through the first semiconductor layer, data recording layers between the first semiconductor layer and the control gates, two first conductive-type diffusion layers at two ends in the first direction of the first semiconductor layer, two second conductive-type diffusion layers at two ends in the second direction of the first semiconductor layer, select gate lines extending in the first direction on the first semiconductor layer, and word lines extending in the second direction on the select gate lines. The select gate lines function as select gates shared by select transistors connected between the control gates and the word lines arranged in the first direction. Each of the word lines is commonly connected to the control gates arranged in the second direction.
摘要翻译：根据一个实施例，非易失性半导体存储器包括以阵列形式提供的控制栅极，通过第一半导体层的控制栅极，第一半导体层和控制栅极之间的数据记录层，两个第一导电型扩散层在第一半导体层的第一方向上结束，在第一半导体层的第二方向上的两端处的两个第二导电型扩散层，在第一半导体层上沿第一方向延伸的选择栅极线，选择栅极线上的第二个方向。选择栅极线用作连接在控制栅极和沿第一方向布置的字线之间的选择晶体管共享的选择栅极。每条字线通常连接到沿第二方向布置的控制门。

2. 发明授权

US07956408B2 Nonvolatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US07956408B2
公开(公告)日：2011-06-07
申请号：US12021003
申请日：2008-01-28
申请人： Toshiyuki Enda , Hirosyoshi Tanimoto , Takashi Izumida
发明人： Toshiyuki Enda , Hirosyoshi Tanimoto , Takashi Izumida
IPC分类号： H01L27/115
CPC分类号： H01L27/115 , H01L27/11568 , H01L27/11578 , H01L27/11582 , H01L29/792 , H01L29/7926
摘要： A nonvolatile semiconductor memory device relating to one embodiment of this invention includes a substrate, a plurality of memory strings formed on said substrate, said memory string having a first select gate transistor, a plurality of memory cells and a second select gate transistor, said first select gate transistor having a first pillar semiconductor, a first gate insulation layer formed around said first pillar semiconductor and a first gate electrode being formed around said first gate insulation layer; said memory cell having a second pillar semiconductor, a first insulation layer formed around said second pillar semiconductor, a storage layer formed around said first insulation layer, a second insulation layer formed around said storage layer and first to nth electrodes (n is a natural number 2 or more) being formed around said second insulation layer, said first to nth electrodes being spread in two dimensions respectively, said second select gate transistor having a third pillar semiconductor, a second gate insulation layer formed around said third pillar semiconductor and a second gate electrode being formed around said second gate insulation layer, and a channel region of at least either said first select gate transistor or said second select gate transistor formed by an opposite conductive type semiconductor to a source region and a drain region.
摘要翻译：关于本发明的一个实施例的非易失性半导体存储器件包括衬底，形成在所述衬底上的多个存储器串，所述存储器串具有第一选择栅晶体管，多个存储单元和第二选择栅晶体管，所述第一选择具有第一柱状半导体的栅极晶体管，形成在所述第一柱状半导体周围的第一栅极绝缘层和围绕所述第一栅极绝缘层形成的第一栅极电极; 所述存储单元具有第二柱状半导体，围绕所述第二柱状半导体形成的第一绝缘层，围绕所述第一绝缘层形成的存储层，形成在所述存储层和第一至第n电极周围的第二绝缘层（n为自然数） 2个或更多个），所述第一至第n电极分别以两维扩展，所述第二选择栅晶体管具有第三柱半导体，围绕所述第三柱半导体形成的第二栅绝缘层和第二栅极形成在所述第二栅极绝缘层周围的电极，以及至少所述第一选择栅极晶体管或所述第二选择栅极晶体管的沟道区域，所述沟道区域由相对的导电型半导体形成为源极区域和漏极区域。

3. 发明授权

US06784006B2 Semiconductor device, method of manufacturing semiconductor device, and system for evaluating electrical characteristics of semiconductor device 失效
标题翻译：半导体器件，制造半导体器件的方法以及用于评估半导体器件的电特性的系统
公开(公告)号：US06784006B2
公开(公告)日：2004-08-31
申请号：US10001977
申请日：2001-12-05
申请人： Hiroyoshi Tanimoto , Toshiyuki Enda
发明人： Hiroyoshi Tanimoto , Toshiyuki Enda
IPC分类号： H01L2166
CPC分类号： H01L22/20 , G01R31/2642
摘要： A method of manufacturing a semiconductor device, comprises: forming a semiconductor element in a semiconductor active region, and calculating the generation rate of electron hole pairs generated due to impact ionization caused in the semiconductor element; calculating a volume integral of the generation rate at least in an area where the impact ionization is caused; evaluating time-dependent degradations of electrical characteristics of the semiconductor element on the basis of the volume integral; and manufacturing a semiconductor device on the basis of the evaluation.
摘要翻译：一种制造半导体器件的方法，包括：在半导体有源区中形成半导体元件，并计算由于在半导体元件中引起的冲击电离产生的电子空穴对的产生速率; 至少在造成碰撞电离的区域中计算发电率的体积积分; 基于体积积分来评估半导体元件的电特性的时间依赖性降低; 并在评估的基础上制造半导体器件。

4. 发明授权

US06195790B1 Electrical parameter evaluation system, electrical parameter evaluation method, and computer-readable recording medium for recording electrical parameter evaluation program 失效
标题翻译：电气参数评估系统，电气参数评估方法以及用于记录电气参数评估程序的计算机可读记录介质
公开(公告)号：US06195790B1
公开(公告)日：2001-02-27
申请号：US09061866
申请日：1998-04-17
申请人： Hiroyoshi Tanimoto , Toshiyuki Enda , Naoyuki Shigyo , Kazuya Matsuzawa
发明人： Hiroyoshi Tanimoto , Toshiyuki Enda , Naoyuki Shigyo , Kazuya Matsuzawa
IPC分类号： G06F760
CPC分类号： G06F17/5018 , G06F2217/16
摘要： A &Dgr;Z calculator calculates difference between an inversion layer capacitance by a classical theory and an inversion layer capacitance by a quantum theory, calculates &Dgr;Z which is a thickness of a semiconductor substrate equivalent to the difference in inversion layer capacitance. A discretization mesh generator generates a Delaunay discretization mesh for a structure of the semiconductor device to be evaluated. An electrical parameter calculator calculates electrical parameters of the semiconductor device under constraint that a charge density of channel conductivity type of the semiconductor device is set to zero at discretization mesh points of the discretization mesh on an interface between an insulating film and the semiconductor substrate and at discretization mesh points of the discretization mesh in the semiconductor substrate which are located within a distance less than the stored &Dgr;Z from the interface between the insulating film and the semiconductor substrate.
摘要翻译： DELTAZ计算器通过经典理论计算反演层电容与量子理论的反演层电容之间的差异，计算作为反转层电容差异的半导体衬底的厚度的DELTAZ。离散网格生成器为要评估的半导体器件的结构生成Delaunay离散化网格。电参数计算器在绝缘膜和半导体衬底之间的界面上的离散网格的离散网格点处以及半导体衬底的沟道导电类型的电荷密度设置为零的条件下计算半导体器件的电参数，并且在半导体衬底中离散网格的离散网格点位于比绝缘膜和半导体衬底之间的界面上的存储的DELTAZ小的距离内。

5. 发明申请

US20070102749A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME 失效
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20070102749A1
公开(公告)日：2007-05-10
申请号：US11549770
申请日：2006-10-16
申请人： Riichiro Shirota , Fumitaka Arai , Toshiyuki Enda , Hiroyoshi Tanimoto , Naoki Kusunokii , Nobutoshi Aoki , Makoto Mizukami , Kiyotaka Miyano , Ichiro Mizushima
发明人： Riichiro Shirota , Fumitaka Arai , Toshiyuki Enda , Hiroyoshi Tanimoto , Naoki Kusunokii , Nobutoshi Aoki , Makoto Mizukami , Kiyotaka Miyano , Ichiro Mizushima
IPC分类号： H01L29/76
CPC分类号： H01L27/115 , G11C16/0483 , H01L27/11519 , H01L27/11526 , H01L27/11529
摘要： A semiconductor memory device includes: a semiconductor substrate; a semiconductor layer formed on the semiconductor substrate with an insulating film interposed therebetween, the semiconductor layer being in contact with the semiconductor substrate via an opening formed in the insulating film; and a NAND cell unit formed on the semiconductor layer with a plurality of electrically rewritable and non-volatile memory cells connected in series and first and second select gate transistors disposed at both ends thereof.
摘要翻译：半导体存储器件包括：半导体衬底; 在半导体衬底上形成有绝缘膜的半导体层，所述半导体层经由形成在所述绝缘膜中的开口与所述半导体衬底接触; 以及在半导体层上形成有串联连接的多个电可重写和非易失性存储单元的NAND单元单元，以及设置在其两端的第一和第二选择栅晶体管。

6. 发明授权

US5889687A Simulator, simulation and fabrication methods of semiconductor device and storage medium storing program for executing the simulation method 失效
公开(公告)号：US5889687A
公开(公告)日：1999-03-30
申请号：US61867
申请日：1998-04-17
申请人： Toshiyuki Enda
发明人： Toshiyuki Enda
IPC分类号： H01L29/00 , G06F17/00 , G06F17/50 , H01L21/00 , H01L21/02
CPC分类号： G06F17/5036
摘要： The present invention provides a device simulation method comprising at least the steps of: inputting a geometry of a semiconductor device, a donor and an acceptor impurity concentrations at each point inside the semiconductor device and also terminal voltages of the semiconductor device (step S101); setting initial values by obtaining electron concentrations n, and n.sub.J and also hole concentrations p.sub.I and p.sub.J with respect to given points I and J respectively inside the semiconductor device and also a potential at each point (step S102); obtaining a voltage difference .PSI..sub.dd across a prescribed segment dd along a segment IJ connecting the points I and J (step S103); calculating an electron current density J.sub.eIJ of the segment IJ by an equation J.sub.eLJ =C.sub.eI .multidot.A(.PHI..sub.edd)-C.sub.eJ .multidot.A(-.PHI..sub.edd) using a constant C.sub.eI dependent on the electron concentration n.sub.J, a constant C.sub.eJ dependent on the electron concentration n.sub.J, and a voltage difference (.PHI..sub.edd =.PSI..sub.dd /NV.sub.e) across the segment dd normalized by an electron's thermal voltage (NV.sub.e =k.multidot.T.sub.e /(-q)) (step S104); calculating a hole current density J.sub.hIJ of the segment IJ by an equation J.sub.hIJ =C.sub.hI .multidot.A(.PHI..sub.hdd)-C.sub.hJ .multidot.A(-.PHI..sub.hdd) using a constant C.sub.hI dependent on the hole concentration p.sub.I, a constant C.sub.hJ dependent on the hole concentration p.sub.J, and a voltage difference ((.PHI..sub.hdd =.PSI..sub.dd /NV.sub.h) across the segment dd normalized by a hole's thermal voltage (NV.sub.h =k.multidot.T.sub.h /q) (step S105); and outputting a terminal current, where A(.PHI.)=1/(exp(.PHI.)+1). The present invention provides also a device simulator that can perform this device simulation method for fabricating semiconductor devices, and a storage medium storing the program to perform this device simulation method. The present invention further provides a device fabrication method employing the device simulation method.

7. 发明授权

US07755134B2 Nonvolatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US07755134B2
公开(公告)日：2010-07-13
申请号：US11765881
申请日：2007-06-20
申请人： Masaru Kito , Nobutoshi Aoki , Masaru Kidoh , Ryota Katsumata , Masaki Kondo , Naoki Kusunoki , Toshiyuki Enda , Sanae Ito , Hiroyoshi Tanimoto , Hideaki Aochi , Akihiro Nitayama , Riichiro Shirota
发明人： Masaru Kito , Nobutoshi Aoki , Masaru Kidoh , Ryota Katsumata , Masaki Kondo , Naoki Kusunoki , Toshiyuki Enda , Sanae Ito , Hiroyoshi Tanimoto , Hideaki Aochi , Akihiro Nitayama , Riichiro Shirota
IPC分类号： H01L27/115
CPC分类号： H01L29/7881 , H01L21/84 , H01L27/115 , H01L27/11521 , H01L27/11568 , H01L27/1203 , H01L29/42336
摘要： A nonvolatile semiconductor memory device includes: a semiconductor region; device isolation regions placed in the semiconductor region and extending in a column direction; a semiconductor layer placed on the semiconductor region and between the device isolation regions, and having a convex shape in cross section along a row direction; source/drain regions placed in the semiconductor layer and spaced from each other; a gate insulating film placed on the semiconductor layer between the source/drain regions; a floating gate electrode layer placed on the gate insulating film; an intergate insulating film placed on the floating gate electrode layer and upper surfaces of the device isolation regions; and a control gate electrode layer placed on the intergate insulating film and extending in the row direction.
摘要翻译：非易失性半导体存储器件包括：半导体区域; 器件隔离区域放置在半导体区域中并沿列方向延伸; 放置在半导体区域和器件隔离区之间的半导体层，沿着行方向具有凸形的横截面; 源极/漏极区域放置在半导体层中并彼此间隔开; 位于源极/漏极区之间的半导体层上的栅极绝缘膜; 放置在栅极绝缘膜上的浮栅电极层; 布置在浮栅电极层和器件隔离区的上表面上的隔间绝缘膜; 以及控制栅极电极层，其设置在所述隔间绝缘膜上并沿行方向延伸。

8. 发明申请

US20100169061A1 SIMULATION APPARATUS FOR A SEMICONDUCTOR DEVICE 有权
标题翻译：一种半导体器件的仿真设备
公开(公告)号：US20100169061A1
公开(公告)日：2010-07-01
申请号：US12563517
申请日：2009-09-21
申请人： Toshiyuki ENDA
发明人： Toshiyuki ENDA
IPC分类号： G06F17/12
CPC分类号： G06F17/5018 , G06F2217/78
摘要： A simulation apparatus of semiconductor device includes a first calculator, a second calculator, a third calculator, a fourth calculator, and a controller. The first calculator applies a voltage to an area which functions as a virtual electrode, and setting a pseudo-Fermi level of a first carrier in the area functioning as the virtual electrode to calculate a first carrier density. The second calculator analyzes continuous equation of a second carrier to calculate a second carrier density. The third calculator uses the first carrier density as a function of an electrostatic potential, and solving a first equation of the function and a Poisson's equation to calculate an electrostatic potential and the first carrier density expressed by the function. The fourth calculator calculates a current density of the first carrier to calculate a current flowing. The controller controls the voltage applied to the virtual electrode.
摘要翻译：半导体器件的模拟装置包括第一计算器，第二计算器，第三计算器，第四计算器和控制器。第一计算器将电压施加到用作虚拟电极的区域，并且在用作虚拟电极的区域中设置第一载体的伪费米能级以计算第一载流子密度。第二计算器分析第二载波的连续方程式来计算第二载流子密度。第三计算器使用第一载流子密度作为静电势的函数，并且求解函数的第一方程和泊松方程来计算由该函数表达的静电势和第一载流子密度。第四计算器计算第一载波的电流密度以计算电流流动。控制器控制施加到虚拟电极的电压。

9. 发明授权

US07459748B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US07459748B2
公开(公告)日：2008-12-02
申请号：US11549770
申请日：2006-10-16
申请人： Riichiro Shirota , Fumitaka Arai , Toshiyuki Enda , Hiroyoshi Tanimoto , Naoki Kusunoki , Nobutoshi Aoki , Makoto Mizukami , Kiyotaka Miyano , Ichiro Mizushima
发明人： Riichiro Shirota , Fumitaka Arai , Toshiyuki Enda , Hiroyoshi Tanimoto , Naoki Kusunoki , Nobutoshi Aoki , Makoto Mizukami , Kiyotaka Miyano , Ichiro Mizushima
IPC分类号： H01L29/76
CPC分类号： H01L27/115 , G11C16/0483 , H01L27/11519 , H01L27/11526 , H01L27/11529
摘要： A semiconductor memory device includes: a semiconductor substrate; a semiconductor layer formed on the semiconductor substrate with an insulating film interposed therebetween, the semiconductor layer being in contact with the semiconductor substrate via an opening formed in the insulating film; and a NAND cell unit formed on the semiconductor layer with a plurality of electrically rewritable and non-volatile memory cells connected in series and first and second select gate transistors disposed at both ends thereof.
摘要翻译：半导体存储器件包括：半导体衬底; 在半导体衬底上形成有绝缘膜的半导体层，所述半导体层经由形成在所述绝缘膜中的开口与所述半导体衬底接触; 以及在半导体层上形成有串联连接的多个电可重写和非易失性存储单元的NAND单元单元，以及设置在其两端的第一和第二选择栅晶体管。

10. 发明申请

US20080253181A1 METHOD FOR PROGRAMMING A SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：用于编程半导体存储器件的方法
公开(公告)号：US20080253181A1
公开(公告)日：2008-10-16
申请号：US12061105
申请日：2008-04-02
申请人： Toshiaki Edahiro , Takuya Futatsuyama , Toshiyuki Enda
发明人： Toshiaki Edahiro , Takuya Futatsuyama , Toshiyuki Enda
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/3418 , G11C16/3427
摘要： A method for programming a semiconductor memory device including such a program sequence as to program target threshold levels constituting multi-level data into multiple memory cells, which are simultaneously selected, wherein the program sequence is controlled to finish programming the multiple memory cells in order of height of the target threshold levels.
摘要翻译：一种编程半导体存储器件的方法，该半导体存储器件包括这样的程序序列，将构成多级数据的程序目标阈值水平同时选择为多个存储器单元，其中控制该程序序列以完成对多个存储器单元的编程，目标阈值水平的高度。

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