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81. 发明授权

US06730930B2 Memory element and method for fabricating a memory element 失效
标题翻译：用于制造存储元件的存储元件和方法
公开(公告)号：US06730930B2
公开(公告)日：2004-05-04
申请号：US10275598
申请日：2003-04-21
申请人： Franz Hofmann , Richard Johannes Luyken , Wolfgang Rösner
发明人： Franz Hofmann , Richard Johannes Luyken , Wolfgang Rösner
IPC分类号： H01L3524
CPC分类号： H01L27/28 , B82Y10/00 , G11C13/0014 , G11C13/0016 , G11C2213/77 , H01L51/0575
摘要： A memory element with organic material comprises two metallized layers, arranged one on top of the other, with first lines and second lines which are arranged to intersect with each other. A channel is formed at the intersections between the first line and the second line, which overlaps the first line partially and completely overlaps the second line. The channels are filled with a filling material, the electrical conductivity of which may be altered by an applied electrical voltage.
摘要翻译：具有有机材料的存储元件包括两个金属化层，其一个在另一个的顶部上，第一线和第二线被布置为彼此相交。在第一线和第二线之间的交叉处形成通道，其与第一线重叠，并且与第二线完全重叠。通道填充有填充材料，其电导率可以通过施加的电压而改变。

82. 发明授权

US06707098B2 Electronic device and method for fabricating an electronic device 有权
标题翻译：用于制造电子设备的电子设备和方法
公开(公告)号：US06707098B2
公开(公告)日：2004-03-16
申请号：US09882882
申请日：2001-06-15
申请人： Franz Hofmann , Franz Kreupl , Richard Johannes Luyken , Till Schloesser
发明人： Franz Hofmann , Franz Kreupl , Richard Johannes Luyken , Till Schloesser
IPC分类号： H01L29792
CPC分类号： G11C13/025 , B82Y10/00 , G11C11/5671 , G11C2213/71 , G11C2213/77 , G11C2213/81 , G11C2216/08 , H01L51/0048 , Y10S438/962 , Y10S977/943
摘要： An electronic device has a plurality of electrically conductive first nanowires, a layer system applied on the first nanowires, and also second nanowires applied on the layer system. The first and second nanowires are arranged skew with respect to one another. The layer system is set up in such a way that charge carriers generated by the nanowires can be stored in the layer system.
摘要翻译：电子器件具有多个导电的第一纳米线，施加在第一纳米线上的层系统，以及施加在层系统上的第二纳米线。第一和第二纳米线相对于彼此倾斜布置。层系统的设置使得由纳米线产生的电荷载流子可以存储在层系统中。

83. 发明授权

US06608340B1 Substrate assembly having a depression suitable for an integrated circuit configuration and method for its fabrication 有权
标题翻译：具有适于集成电路结构的凹陷的衬底组件及其制造方法
公开(公告)号：US06608340B1
公开(公告)日：2003-08-19
申请号：US09821853
申请日：2001-03-30
申请人： Franz Hofmann , Till Schlösser , Josef Willer
发明人： Franz Hofmann , Till Schlösser , Josef Willer
IPC分类号： H01L2972
CPC分类号： H01L27/10864
摘要： A depression extends from a main surface of the substrate to the inside of said substrate and has an upper area and an adjacent lower area. A cross-section of the upper area, parallel to the main surface, is provided with at least one corner. A cross-section of the lower area, parallel to the main surface, matches the cross-section of the upper area, particularly in the vicinity the upper area, with the following difference: each corner is rounded, whereby the cross section of the lower area is smaller than the cross-section of the upper area. In order to produce the indentation, the upper area is provided with an auxiliary spacer that is rounded by isotropic etching. The lower area is produced by selectively etching the substrate to form an auxiliary spacer.
摘要翻译：凹陷从基板的主表面延伸到所述基板的内部，并且具有上部区域和相邻的下部区域。平行于主表面的上部区域的横截面设置有至少一个角部。平行于主表面的下部区域的横截面与上部区域的横截面特别是在上部区域附近匹配，具有以下差异：每个角都是圆形的，由此下部区域的横截面面积小于上部区域的横截面。为了产生凹陷，上部区域设置有通过各向同性蚀刻而被圆化的辅助间隔件。通过选择性地蚀刻基板以形成辅助间隔物来产生下部区域。

84. 发明授权

US06599797B1 SOI DRAM without floating body effect 有权
标题翻译： SOI DRAM无浮体效应
公开(公告)号：US06599797B1
公开(公告)日：2003-07-29
申请号：US09980811
申请日：2002-03-11
申请人： Franz Hofmann , Josef Willer
发明人： Franz Hofmann , Josef Willer
IPC分类号： H01L218242
CPC分类号： H01L27/10873 , H01L27/10888 , H01L27/1203
摘要： The invention relates to an SOI substrate which is provided with a recess that cuts through the silicon layer and the SiO2 layer (O). An upper part of said recess (V) which is located in the range of the silicon layer (S) has cylindrical shape with a horizontal first cross-section. A lower part of the recess (V) which is located in the range of the SiO2 layer (O), compared with the upper part of the recess (V), is bulged to such an extent that it has a cylindrical shape with a horizontal second cross-section that is larger than the first cross-section. A cylinder (Z) of an insulating material is provided in the recess (V). The horizontal cross-section of said cylinder corresponds to the first cross-section and the lower part thereof is located in the lower part of the recess (V). The dent laterally surrounds the lower part of the cylinder (Z). A conducting structure (L) is located in the dent and adjoins the silicon layer (S) and the silicon substrate (1) so that the channel zone of the MOS transistors is electrically connected to the silicon substrate.
摘要翻译：本发明涉及一种SOI衬底，其具有穿过硅层和SiO 2层（O）的凹部。位于硅层（S）的范围内的所述凹部（V）的上部具有水平的第一横截面的圆筒形状。与凹部（V）的上部相比，位于SiO 2层（O）的范围内的凹部（V）的下部被凸出到具有水平的圆筒形状的程度第二横截面大于第一横截面。在凹部（V）中设置绝缘材料的圆筒（Z）。所述气缸的水平截面对应于第一横截面，其下部位于凹部（V）的下部。凹陷横向围绕气缸（Z）的下部。导电结构（L）位于凹陷中并与硅层（S）和硅衬底（1）相邻，使得MOS晶体管的沟道区电连接到硅衬底。

85. 发明授权

US06593614B1 Integrated circuit configuration having at least one transistor and one capacitor, and method for fabricating it 有权
标题翻译：具有至少一个晶体管和一个电容器的集成电路配置及其制造方法
公开(公告)号：US06593614B1
公开(公告)日：2003-07-15
申请号：US09716336
申请日：2000-11-20
申请人： Franz Hofmann , Wolfgang Krautschneider
发明人： Franz Hofmann , Wolfgang Krautschneider
IPC分类号： H01L27108
CPC分类号： H01L27/10852 , H01L27/10808 , H01L27/10823 , H01L27/10876
摘要： A patterned conductive layer and a structure via which a transistor can be driven, e.g. a word line, are disposed one above the other. A vertical conductive structure, e.g. a spacer, connects a first source/drain region of the transistor to the conductive layer, with which it forms a first capacitor electrode which has a large effective area in conjunction with a high packing density. A capacitor dielectric is disposed over the vertical conductive structure and the conductive layer, and a second capacitor electrode is disposed over the capacitor dielectric. The vertical conductive structure may be disposed on a first sidewall of the first source/drain region and a gate electrode of the transistor may be disposed on an adjoining second sidewall of the first source/drain region. The circuit configuration may form a DRAM cell configuration.
摘要翻译：图案化的导电层和可以驱动晶体管的结构，例如，一个字线，一个在另一个之上。垂直导电结构，例如间隔件将晶体管的第一源极/漏极区域连接到导电层，由此形成第一电容器电极，其具有大的有效面积并结合高的堆积密度。电容器电介质设置在垂直导电结构和导电层之上，并且第二电容器电极设置在电容器电介质上。垂直导电结构可以设置在第一源极/漏极区域的第一侧壁上，并且晶体管的栅电极可以设置在第一源极/漏极区域的相邻的第二侧壁上。电路配置可以形成DRAM单元配置。

86. 发明授权

US06518628B1 Integrated CMOS circuit configuration, and production of same 有权
标题翻译：集成CMOS电路配置，生产相同
公开(公告)号：US06518628B1
公开(公告)日：2003-02-11
申请号：US09423864
申请日：1999-11-15
申请人： Wolfgang Krautschneider , Franz Hofmann , Lothar Risch
发明人： Wolfgang Krautschneider , Franz Hofmann , Lothar Risch
IPC分类号： H01L2976
CPC分类号： H01L27/0922
摘要： An integrated CMOS circuit arrangement and a method of manufacturing same, which includes both a first MOS transistor and a second MOS transistor complementary thereto, wherein one of the MOS transistors is arranged at the floor of a trench and the other is arranged at the principal surface of a semiconductor substrate. The MOS transistors are arranged relative to one another such that a current flow through the MOS transistors respectively occurs substantially parallel to a sidewall of the trench that is arranged between the MOS transistors.
摘要翻译：一种集成CMOS电路装置及其制造方法，其包括第一MOS晶体管和与其互补的第二MOS晶体管，其中MOS晶体管中的一个布置在沟槽的底部，而另一个布置在主表面的半导体衬底。 MOS晶体管相对于彼此布置，使得流过MOS晶体管的电流分别基本上平行于布置在MOS晶体管之间的沟槽的侧壁。

87. 发明授权

US6125050A Configuration for driving parallel lines in a memory cell configuration 有权
标题翻译：用于驱动存储单元配置中的并行线的配置
公开(公告)号：US6125050A
公开(公告)日：2000-09-26
申请号：US335365
申请日：1999-06-17
申请人： Franz Hofmann , Josef Willer , Hans Reisinger , Paul-Werner Basse , Wolfgang Krautschneider
发明人： Franz Hofmann , Josef Willer , Hans Reisinger , Paul-Werner Basse , Wolfgang Krautschneider
IPC分类号： H01L27/112 , G11C5/02 , H01L21/8246
CPC分类号： H01L27/0207 , H01L27/1126 , H01L27/11293 , H01L27/11803
摘要： Parallel lines, for example bit lines in a memory cell configuration formed of doped regions in a semiconductor substrate, are driven by electrically connecting a number of the lines to one another and to a common node. A number of selection lines extend transversely to the lines. MOS transistors are arranged at the points of intersection and are connected in series along one of the lines. The gate electrode of the MOS transistors is formed by the corresponding selection line. At least one MOS transistor in each of the parallel lines has a higher threshold voltage than the others.
摘要翻译：平行线，例如由半导体衬底中的掺杂区形成的存储单元配置中的位线，通过将多个线彼此电连接并连接到公共节点来驱动。多条选择线横向延伸。 MOS晶体管布置在交点处，并沿着一条线串联连接。 MOS晶体管的栅电极由相应的选择线形成。每条并行线路中的至少一个MOS晶体管的阈值电压高于其他。

88. 发明授权

US6037209A Method for producing a DRAM cellular arrangement 有权
标题翻译：用于制造DRAM蜂窝装置的方法
公开(公告)号：US6037209A
公开(公告)日：2000-03-14
申请号：US254696
申请日：1999-03-15
申请人： Wolfgang Rosner , Lothar Risch , Franz Hofmann , Reinhard Stengl
发明人： Wolfgang Rosner , Lothar Risch , Franz Hofmann , Reinhard Stengl
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/10876 , H01L27/10823
摘要： The DRAM cell arrangement comprises, per memory cell, a vertical MOS transistor whose first source/drain region is connected to a storage node of a storage capacitor, whose channel region (3) is annularly enclosed by a gate electrode (13) and whose second source/drain region is connected to a buried bit line. The DRAM cell arrangement is produced using only two masks, with the aid of a spacer technique, with a memory cell area of 2F.sup.2, where F is the minimum structure size which can be produced using the respective technology.
摘要翻译： PCT No.PCT / DE97 / 01580 Sec。 371 1999年3月15日 102（e）1999年3月15日PCT 1997年7月28日PCT公布。出版物WO98 / 11604 日期1998年3月19日DRAM单元布置包括每个存储单元的垂直MOS晶体管，其第一源极/漏极区域连接到存储电容器的存储节点，其沟道区域（3）被栅电极环形封闭 13），并且其第二源极/漏极区域连接到掩埋位线。借助于间隔器技术，仅使用两个掩模来制造DRAM单元布置，存储单元面积为2F2，其中F是可以使用各自技术产生的最小结构尺寸。

89. 发明授权

US08258564B2 Integrated circuit with floating-gate electrodes including a transition metal and corresponding manufacturing method 有权
标题翻译：具有包括过渡金属的浮栅电极的集成电路及相应的制造方法
公开(公告)号：US08258564B2
公开(公告)日：2012-09-04
申请号：US12104750
申请日：2008-04-17
申请人： Josef Willer , Franz Hofmann , Michael Specht , Christoph Friederich , Doris Keitel-Schulz , Lars Bach , Thomas Melde
发明人： Josef Willer , Franz Hofmann , Michael Specht , Christoph Friederich , Doris Keitel-Schulz , Lars Bach , Thomas Melde
IPC分类号： H01L29/788
CPC分类号： H01L27/11521
摘要： An integrated circuit is described. The integrated circuit may comprise a multitude of floating-gate electrodes, wherein at least one of the floating-gate electrodes has a lower width and an upper width, the lower width being larger than the upper width, and wherein the at least one of the floating-gate electrodes comprises a transition metal. A corresponding manufacturing method for an integrated circuit is also described.
摘要翻译：描述了集成电路。集成电路可以包括多个浮栅电极，其中浮栅电极中的至少一个具有较低宽度和上宽度，下宽度大于上宽度，并且其中至少一个浮栅电极包括过渡金属。还描述了集成电路的相应制造方法。

90. 发明授权

US08067249B2 Method for functionalizing biosensor chips 有权
标题翻译：功能化生物传感器芯片的方法
公开(公告)号：US08067249B2
公开(公告)日：2011-11-29
申请号：US11587058
申请日：2005-03-18
申请人： Alexander Frey , Franz Hofmann , Petra Schindler-Bauer
发明人： Alexander Frey , Franz Hofmann , Petra Schindler-Bauer
IPC分类号： H01L21/00
CPC分类号： G01N33/54366 , G01N27/3277
摘要： A method is disclosed for functionalizing biosensors. The biosensors are based on semiconductor chips mounted on a finished processed wafer. They are provided with sensor fields placed thereupon, which are arranged in any array, and, to be precise, for carrying out a functionalization, for example, with organic molecules such as nucleic acids like DNA, RNA and PNA or with their derivatives, proteins, sugar molecules, or antibodies.
摘要翻译：公开了用于使生物传感器功能化的方法。生物传感器基于安装在成品加工晶片上的半导体芯片。它们设置有放置在其上的传感器场，其被布置成任何阵列，并且准确地，用于进行功能化，例如用有机分子例如核酸如DNA，RNA和PNA或其衍生物，蛋白质，糖分子或抗体。

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