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1. 发明授权

US08258564B2 Integrated circuit with floating-gate electrodes including a transition metal and corresponding manufacturing method 有权
标题翻译：具有包括过渡金属的浮栅电极的集成电路及相应的制造方法
公开(公告)号：US08258564B2
公开(公告)日：2012-09-04
申请号：US12104750
申请日：2008-04-17
申请人： Josef Willer , Franz Hofmann , Michael Specht , Christoph Friederich , Doris Keitel-Schulz , Lars Bach , Thomas Melde
发明人： Josef Willer , Franz Hofmann , Michael Specht , Christoph Friederich , Doris Keitel-Schulz , Lars Bach , Thomas Melde
IPC分类号： H01L29/788
CPC分类号： H01L27/11521
摘要： An integrated circuit is described. The integrated circuit may comprise a multitude of floating-gate electrodes, wherein at least one of the floating-gate electrodes has a lower width and an upper width, the lower width being larger than the upper width, and wherein the at least one of the floating-gate electrodes comprises a transition metal. A corresponding manufacturing method for an integrated circuit is also described.
摘要翻译：描述了集成电路。集成电路可以包括多个浮栅电极，其中浮栅电极中的至少一个具有较低宽度和上宽度，下宽度大于上宽度，并且其中至少一个浮栅电极包括过渡金属。还描述了集成电路的相应制造方法。

2. 发明授权

US08067249B2 Method for functionalizing biosensor chips 有权
标题翻译：功能化生物传感器芯片的方法
公开(公告)号：US08067249B2
公开(公告)日：2011-11-29
申请号：US11587058
申请日：2005-03-18
申请人： Alexander Frey , Franz Hofmann , Petra Schindler-Bauer
发明人： Alexander Frey , Franz Hofmann , Petra Schindler-Bauer
IPC分类号： H01L21/00
CPC分类号： G01N33/54366 , G01N27/3277
摘要： A method is disclosed for functionalizing biosensors. The biosensors are based on semiconductor chips mounted on a finished processed wafer. They are provided with sensor fields placed thereupon, which are arranged in any array, and, to be precise, for carrying out a functionalization, for example, with organic molecules such as nucleic acids like DNA, RNA and PNA or with their derivatives, proteins, sugar molecules, or antibodies.
摘要翻译：公开了用于使生物传感器功能化的方法。生物传感器基于安装在成品加工晶片上的半导体芯片。它们设置有放置在其上的传感器场，其被布置成任何阵列，并且准确地，用于进行功能化，例如用有机分子例如核酸如DNA，RNA和PNA或其衍生物，蛋白质，糖分子或抗体。

3. 发明授权

US07838925B2 Integrated circuit including a vertical transistor and method 有权
标题翻译：集成电路包括垂直晶体管和方法
公开(公告)号：US07838925B2
公开(公告)日：2010-11-23
申请号：US12173524
申请日：2008-07-15
申请人： Wolfgang Roesner , Franz Hofmann
发明人： Wolfgang Roesner , Franz Hofmann
IPC分类号： H01L29/732
CPC分类号： H01L29/7827 , H01L21/2255 , H01L27/108 , H01L27/10802 , H01L27/10876 , H01L29/0878 , H01L29/0886 , H01L29/1083 , H01L29/1095 , H01L29/41766 , H01L29/42356 , H01L29/66734 , H01L29/7813
摘要： An integrated circuit including a vertical transistor and method of manufacturing. In one embodiment a vertical transistor is formed in a pillar of a semiconductor substrate. A buried conductive line is separated from the semiconductor substrate by a first insulating layer in a first portion and is electrically coupled to a buried source/drain region of the vertical transistor through a contact structure. A second insulating layer is arranged above and adjacent to the contact structure. At least one of the first and second insulating layers includes a dopant. A doped region is formed in the semiconductor substrate at an interface to the at least one insulating layer. The doped region has a dopant concentration higher than a substrate dopant concentration.
摘要翻译：一种包括垂直晶体管和制造方法的集成电路。在一个实施例中，垂直晶体管形成在半导体衬底的柱中。埋入导线通过第一部分中的第一绝缘层与半导体衬底分离，并通过接触结构电耦合到垂直晶体管的掩埋源/漏区。第二绝缘层布置在接触结构的上方并与之相邻。第一和第二绝缘层中的至少一个包括掺杂剂。掺杂区域形成在半导体衬底中与至少一个绝缘层的界面处。掺杂区域的掺杂浓度高于衬底掺杂剂浓度。

4. 发明授权

US07829892B2 Integrated circuit including a gate electrode 有权
标题翻译：集成电路包括栅电极
公开(公告)号：US07829892B2
公开(公告)日：2010-11-09
申请号：US11926653
申请日：2007-10-29
申请人： Richard Johannes Luyken , Franz Hofmann , Lothar Risch , Dirk Manger , Wolfgang Roesner , Till Schloesser , Michael Specht
发明人： Richard Johannes Luyken , Franz Hofmann , Lothar Risch , Dirk Manger , Wolfgang Roesner , Till Schloesser , Michael Specht
IPC分类号： H01L29/12
CPC分类号： H01L27/10823 , H01L27/10808 , H01L27/10826 , H01L27/10829 , H01L27/10891 , H01L29/7851
摘要： An integrated circuit including a gate electrode is disclosed. One embodiment provides a transistor including a first source/drain electrode and a second source/drain electrode. A channel is arranged between the first and the second source/drain electrode in a semiconductor substrate. A gate electrode is arranged adjacent the channel layer and is electrically insulated from the channel layer. A semiconductor substrate electrode is provided on a rear side. The gate electrode encloses the channel layer at least two opposite sides.
摘要翻译：公开了一种包括栅电极的集成电路。一个实施例提供一种晶体管，其包括第一源极/漏极电极和第二源极/漏极电极。在半导体衬底中的第一和第二源极/漏极之间布置有沟道。栅电极被布置在沟道层附近并且与沟道层电绝缘。半导体基板电极设置在后侧。栅极电极将沟道层包围至少两个相对的侧面。

5. 发明授权

US07772580B2 Integrated circuit having a cell with a resistivity changing layer 有权
标题翻译：具有具有电阻率变化层的单元的集成电路
公开(公告)号：US07772580B2
公开(公告)日：2010-08-10
申请号：US11837380
申请日：2007-08-10
申请人： Franz Hofmann , Josef Willer
发明人： Franz Hofmann , Josef Willer
IPC分类号： H01L29/02
CPC分类号： H01L45/149 , G11C13/0004 , H01L27/2436 , H01L45/06 , H01L45/065 , H01L45/085 , H01L45/1233 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/146 , H01L45/148 , H01L45/1683
摘要： In an embodiment of the invention, an integrated circuit having a cell is provided. The cell may include a field effect transistor structure which includes a gate stack and a resistivity changing material structure disposed above the gate stack, wherein the resistivity changing material structure includes a resistivity changing material which is configured to change its resistivity in response to the application of an electrical voltage to the resistivity changing material structure.
摘要翻译：在本发明的实施例中，提供了具有单元的集成电路。电池可以包括场效应晶体管结构，其包括设置在栅极堆叠上方的栅极堆叠和电阻率变化材料结构，其中电阻率变化材料结构包括电阻率变化材料，其被配置为响应于应用对电阻率变化材料结构的电压。

6. 发明申请

US20100013005A1 INTEGRATED CIRCUIT INCLUDING A VERTICAL TRANSISTOR AND METHOD 有权
标题翻译：集成电路，包括垂直晶体管和方法
公开(公告)号：US20100013005A1
公开(公告)日：2010-01-21
申请号：US12173524
申请日：2008-07-15
申请人： Wolfgang Roesner , Franz Hofmann
发明人： Wolfgang Roesner , Franz Hofmann
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7827 , H01L21/2255 , H01L27/108 , H01L27/10802 , H01L27/10876 , H01L29/0878 , H01L29/0886 , H01L29/1083 , H01L29/1095 , H01L29/41766 , H01L29/42356 , H01L29/66734 , H01L29/7813
摘要： An integrated circuit including a vertical transistor and method of manufacturing. In one embodiment a vertical transistor is formed in a pillar of a semiconductor substrate. A buried conductive line is separated from the semiconductor substrate by a first insulating layer in a first portion and is electrically coupled to a buried source/drain region of the vertical transistor through a contact structure. A second insulating layer is arranged above and adjacent to the contact structure. At least one of the first and second insulating layers includes a dopant. A doped region is formed in the semiconductor substrate at an interface to the at least one insulating layer. The doped region has a dopant concentration higher than a substrate dopant concentration.
摘要翻译：一种包括垂直晶体管和制造方法的集成电路。在一个实施例中，垂直晶体管形成在半导体衬底的柱中。埋入导线通过第一部分中的第一绝缘层与半导体衬底分离，并通过接触结构电耦合到垂直晶体管的掩埋源/漏区。第二绝缘层布置在接触结构的上方并与之相邻。第一和第二绝缘层中的至少一个包括掺杂剂。掺杂区域形成在半导体衬底中与至少一个绝缘层的界面处。掺杂区域的掺杂浓度高于衬底掺杂剂浓度。

7. 发明授权

US07611928B2 Method for producing a substrate 有权
标题翻译：制造基板的方法
公开(公告)号：US07611928B2
公开(公告)日：2009-11-03
申请号：US10968846
申请日：2004-10-18
申请人： Franz Hofmann , Richard Johannes Luyken , Wolfgang Roesner , Michael Specht , Martin Stadele
发明人： Franz Hofmann , Richard Johannes Luyken , Wolfgang Roesner , Michael Specht , Martin Stadele
IPC分类号： H01L21/00
CPC分类号： H01L21/76254
摘要： Substrate having a first partial substrate with a carrier layer and a second partial substrate, which is bonded to the first partial substrate. The second partial substrate has an insulator layer, which is applied on the carrier layer and has at least two regions each having a different thickness, thereby forming a stepped surface of the insulator layer, and a semiconductor layer, which is applied to the stepped surface of the insulator layer and is formed at least partially epitaxially, wherein the semiconductor layer has a planar surface which is opposite to the stepped surface of the insulator layer. Transistors are formed on the semiconductor layer.
摘要翻译：衬底，具有第一部分衬底和载体层，第二部分衬底与第一部分衬底结合。第二部分基板具有绝缘体层，其被施加在载体层上并且具有至少两个各自具有不同厚度的区域，从而形成绝缘体层的台阶表面，以及施加到台阶表面的半导体层并且至少部分地外延形成，其中半导体层具有与绝缘体层的台阶表面相对的平面。在半导体层上形成晶体管。

8. 发明授权

US07598543B2 Semiconductor memory component with body region of memory cell having a depression and a graded dopant concentration 失效
标题翻译：具有存储单元体区域的半导体存储器组件具有凹陷和渐变的掺杂剂浓度
公开(公告)号：US07598543B2
公开(公告)日：2009-10-06
申请号：US11438883
申请日：2006-05-23
申请人： Franz Hofmann , Richard Johannes Luyken , Wolfgang Roesner , Michael Specht , Martin Staedele
发明人： Franz Hofmann , Richard Johannes Luyken , Wolfgang Roesner , Michael Specht , Martin Staedele
IPC分类号： H01L27/108
CPC分类号： H01L27/108 , H01L27/10802 , H01L27/1203
摘要： A semiconductor memory component comprises at least one memory cell. The memory cell comprises a semiconductor body comprised of a body region, a drain region and a source region, a gate dielectric, and a gate electrode. The body region comprises a first conductivity type and a depression between the source and drain regions, and the source and drain regions comprise a second conductivity type. The gate electrode is arranged at least partly in the depression and is insulated from the body, source, and drain regions by the gate dielectric. The body region further comprises a first continuous region with a first dopant concentration and a second continuous region with a second dopant concentration greater than the first dopant concentration. The first continuous region adjoins the drain region, the depression and the source region, and the second region is arranged below the first region and adjoins the first region.
摘要翻译：半导体存储器组件包括至少一个存储单元。存储单元包括由体区，漏区和源区组成的半导体本体，栅电介质和栅电极。主体区域包括第一导电类型和源极和漏极区域之间的凹陷，并且源极和漏极区域包括第二导电类型。栅电极至少部分地布置在凹陷中，并且通过栅极电介质与主体，源极和漏极区绝缘。体区还包括具有第一掺杂剂浓度的第一连续区域和具有大于第一掺杂剂浓度的第二掺杂剂浓度的第二连续区域。第一连续区域邻接漏极区域，凹陷部分和源极区域，并且第二区域布置在第一区域下方并与第一区域相邻。

9. 发明申请

US20080237684A1 Method of manufacturing a nanowire transistor, a nanowire transistor structure, a nanowire transistor field 审中-公开
标题翻译：制造纳米线晶体管的方法，纳米线晶体管结构，纳米线晶体管领域
公开(公告)号：US20080237684A1
公开(公告)日：2008-10-02
申请号：US11728587
申请日：2007-03-26
申请人： Michael Specht , Franz Hofmann , Andreas Kux
发明人： Michael Specht , Franz Hofmann , Andreas Kux
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L29/792 , H01L29/0665 , H01L29/0673 , H01L29/40117 , H01L29/7854
摘要： A method of manufacturing a nanowire transistor includes oxidizing at least a portion of a semiconductor carrier. The semiconductor carrier includes a first carrier portion and a second carrier portion above the first carrier portion. A portion of the oxidized portion is removed, thereby forming an oxide spacer between a portion of the second carrier portion and the first carrier portion. A gate region is formed above at least a portion of the second carrier portion, and a first source/drain region and a second source/drain region are formed.
摘要翻译：纳米线晶体管的制造方法包括氧化至少一部分半导体载体。半导体载体包括在第一载体部分上方的第一载体部分和第二载体部分。去除氧化部分的一部分，从而在第二载体部分的一部分和第一载体部分之间形成氧化物间隔物。在第二载体部分的至少一部分上方形成栅极区域，形成第一源极/漏极区域和第二源极/漏极区域。

10. 发明授权

US07400695B2 System and method for time-marking data 失效
标题翻译：时间标记数据的系统和方法
公开(公告)号：US07400695B2
公开(公告)日：2008-07-15
申请号：US10474951
申请日：2002-04-08
申请人： Daniel Murdin , Predrag Pucar , Franz Hofmann
发明人： Daniel Murdin , Predrag Pucar , Franz Hofmann
IPC分类号： H04J3/06
CPC分类号： G06F1/14
摘要： This invention concerns a system comprising processors (2, 3) arranged so as to receive and process data arriving at the system and containing time-indicating means (11, 17, 21) operatively connected to said processors and arranged so as to furnish time data to the processors for time-marking of the data. The time-indicating means (11, 17, 21) include a hardware clock arranged so as to generate a clock signal, and further arranged so as to receive second time data from at least one additional time reference and modify the clock signal from the hardware clock using the second time data in order to generate the first time data. The time-indicating means (11, 17, 21) are arranged so as to add to the clock signal, during the generation of the first time data, a compensation signal (δτi) based on said second time data. The invention also concerns a method for time-marking data.
摘要翻译：本发明涉及一种系统，包括处理器（2,3），其被布置为接收和处理到达系统的数据，并且包含可操作地连接到所述处理器的时间指示装置（11,17,21），并被布置成提供时间数据对处理器进行数据的时间标记。时间指示装置（11,17,21）包括布置成产生时钟信号的硬件时钟，并且还被布置为从至少一个附加时间基准接收第二时间数据，并修改来自硬件的时钟信号时钟使用第二次数据，以生成第一次数据。时间指示装置（11,17,21）被布置为在第一时间数据的生成期间增加基于所述第二时间数据的补偿信号（deltataui）的时钟信号。本发明还涉及用于对数据进行时间标记的方法。

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