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1. 发明授权

US07265376B2 Non-volatile memory cell, memory cell arrangement and method for production of a non-volatile memory cell 有权
标题翻译：非易失性存储单元，存储单元布置和用于生产非易失性存储单元的方法
公开(公告)号：US07265376B2
公开(公告)日：2007-09-04
申请号：US10533215
申请日：2003-10-29
申请人： Andrew Graham , Franz Hofmann , Wolfgang Hönlein , Johannes Kretz , Franz Kreupl , Erhard Landgraf , Richard Johannes Luyken , Wolfgang Rösner , Thomas Schulz , Michael Specht
发明人： Andrew Graham , Franz Hofmann , Wolfgang Hönlein , Johannes Kretz , Franz Kreupl , Erhard Landgraf , Richard Johannes Luyken , Wolfgang Rösner , Thomas Schulz , Michael Specht
IPC分类号： H01L35/24 , H01L51/00 , H01L29/788 , H01L21/336
CPC分类号： H01L29/7888 , B82Y10/00 , G11C13/025 , G11C2213/17 , H01L21/28282 , H01L21/84 , H01L27/115 , H01L27/11568 , H01L27/1203 , H01L27/28 , H01L29/66833 , H01L29/792 , H01L29/7926 , H01L51/0048 , H01L51/0052 , H01L51/057
摘要： A nonvolatile memory cell, memory cell arrangement, and method for production of a nonvolatile memory cell is disclosed. The nonvolatile memory cell includes a vertical field-effect transistor (FET). The FET contains a nanoelement arranged as a channel region and an electrically insulating layer. The electrically insulating layer at least partially surrounds the nanoelement and acts as a charge storage layer and as a gate-insulating layer. The electrically insulating layer is arranged such that electrical charge carriers may be selectively introduced into or removed from the electrically insulating layer and the electrical conductivity characteristics of the nanoelement may be influenced by the electrical charge carriers introduced into the electrically insulating layer.
摘要翻译：公开了一种用于制造非易失性存储单元的非易失性存储单元，存储单元布置和方法。非易失性存储单元包括垂直场效应晶体管（FET）。 FET包含布置为沟道区和电绝缘层的纳米元件。电绝缘层至少部分地包围纳米元件并充当电荷存储层和作为栅极绝缘层。电绝缘层被布置成使得电荷载体可以被选择性地引入到电绝缘层中或从电绝缘层移除，并且纳米元件的导电特性可能受到引入电绝缘层中的电荷载流子的影响。

2. 发明授权

US06730930B2 Memory element and method for fabricating a memory element 失效
标题翻译：用于制造存储元件的存储元件和方法
公开(公告)号：US06730930B2
公开(公告)日：2004-05-04
申请号：US10275598
申请日：2003-04-21
申请人： Franz Hofmann , Richard Johannes Luyken , Wolfgang Rösner
发明人： Franz Hofmann , Richard Johannes Luyken , Wolfgang Rösner
IPC分类号： H01L3524
CPC分类号： H01L27/28 , B82Y10/00 , G11C13/0014 , G11C13/0016 , G11C2213/77 , H01L51/0575
摘要： A memory element with organic material comprises two metallized layers, arranged one on top of the other, with first lines and second lines which are arranged to intersect with each other. A channel is formed at the intersections between the first line and the second line, which overlaps the first line partially and completely overlaps the second line. The channels are filled with a filling material, the electrical conductivity of which may be altered by an applied electrical voltage.
摘要翻译：具有有机材料的存储元件包括两个金属化层，其一个在另一个的顶部上，第一线和第二线被布置为彼此相交。在第一线和第二线之间的交叉处形成通道，其与第一线重叠，并且与第二线完全重叠。通道填充有填充材料，其电导率可以通过施加的电压而改变。

3. 发明授权

US07189988B2 Molecular electronics arrangement and method for producing a molecular electronics arrangement 有权
标题翻译：分子电子学布置和分子电子学布置方法
公开(公告)号：US07189988B2
公开(公告)日：2007-03-13
申请号：US10482719
申请日：2002-07-01
申请人： Jessica Hartwich , Johannes Kretz , Richard Johannes Luyken , Wolfgang Rösner
发明人： Jessica Hartwich , Johannes Kretz , Richard Johannes Luyken , Wolfgang Rösner
IPC分类号： H01L35/24
CPC分类号： G11C13/0019 , B82Y10/00 , G11C13/0014 , H01L51/0048 , H01L51/005 , H01L51/0052 , H01L51/0093 , H01L51/0595
摘要： The invention relates to a molecular electronics arrangement comprising a substrate, at least one first strip conductor having a surface and being arranged in or on the substrate, a spacer which is arranged on the surface of the at least one first strip conductor and which partially covers the surface of the at least one first strip conductor, and at least one second strip conductor which is arranged on the spacer and comprises a surface which faces the surface of the at least one first strip conductor in a plane manner. The spacer partially covers the surface of the at least one second strip conductor, and defines a pre-determined distance between the at least one first strip conductor and the at least one second strip conductor. The inventive molecular electronics arrangement also comprises molecular electronics molecules which are arranged between a free region of the surface of the at least one first strip conductor and a free region of the surface of the at least one second strip conductor, the length of said molecules being essentially equal to the distance between the at least one first strip conductor and the at least one second strip conductor. The invention also relates to a method for producing a molecular electronics arrangement.
摘要翻译：本发明涉及一种分子电子装置，其包括基底，至少一个具有表面并且布置在基底中或基底上的第一条状导体，隔离物，其被布置在至少一个第一条状导体的表面上，并且部分覆盖所述至少一个第一带状导体的表面和布置在所述间隔件上并包括以平面方式面对所述至少一个第一带状导体的表面的表面的至少一个第二条状导体。所述间隔件部分地覆盖所述至少一个第二条状导体的表面，并且限定所述至少一个第一条状导体和所述至少一个第二条状导体之间的预定距离。本发明的分子电子学装置还包括分子电子学分子，其分布在至少一个第一带状导体的表面的自由区域和至少一个第二条状导体的表面的自由区域之间，所述分子的长度为基本上等于所述至少一个第一带状导体和所述至少一个第二带状导体之间的距离。本发明还涉及生产分子电子装置的方法。

4. 发明授权

US06914292B2 Floating gate field-effect transistor 失效
标题翻译：浮栅场效应晶体管
公开(公告)号：US06914292B2
公开(公告)日：2005-07-05
申请号：US10302615
申请日：2002-11-21
申请人： Michael Specht , Martin Städele , Wolfgang Rösner , Franz Hofmann
发明人： Michael Specht , Martin Städele , Wolfgang Rösner , Franz Hofmann
IPC分类号： H01L21/8247 , H01L21/28 , H01L27/115 , H01L29/423 , H01L29/51 , H01L29/788 , H01L29/792
CPC分类号： H01L21/28194 , H01L29/42324 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/7883
摘要： A floating gate field-effect transistor (400), which is preferably used as a memory cell, has, above or below a floating gate region (407), an electrically insulating layer sequence (408) having a lower layer (409) having a first relative permittivity, having a middle layer (410) having a second relative permittivity, and having an upper layer (411) having a third relative permittivity, the second relative permittivity being greater than the first relative permittivity and greater than the third relative permittivity.
摘要翻译：优选用作存储单元的浮置栅极场效应晶体管（400）具有在浮置栅极区域（407）的上方或下方的具有下层（409）的电绝缘层序列（408），其具有具有第二相对介电常数的中间层（410）和具有第三相对介电常数的上层（411）的第一相对介电常数，第二相对介电常数大于第一相对介电常数且大于第三相对介电常数。

5. 发明授权

US06229169B1 Memory cell configuration, method for fabricating it and methods for operating it 失效
标题翻译：存储单元配置，其制造方法及其操作方法
公开(公告)号：US06229169B1
公开(公告)日：2001-05-08
申请号：US09213724
申请日：1998-12-17
申请人： Franz Hofmann , Wolfgang Krautschneider , Wolfgang Rösner , Lothar Risch , Till Schlösser , Paul-Werner Basse
发明人： Franz Hofmann , Wolfgang Krautschneider , Wolfgang Rösner , Lothar Risch , Till Schlösser , Paul-Werner Basse
IPC分类号： H01L27108
CPC分类号： H01L27/11502 , H01L27/108 , H01L27/10823 , H01L27/10876 , H01L27/115 , H01L27/11507
摘要： A memory cell configuration contains a multiplicity of memory cells in a semiconductor substrate. Each of the memory cells has a selection transistor connected between a bit line and a storage element. The memory cells can each be driven via a first word line and a second word line, the first word line and the second word line crossing one another. The memory cell configuration is, in particular, a DRAM configuration.
摘要翻译：存储单元配置在半导体衬底中包含多个存储单元。每个存储单元具有连接在位线和存储元件之间的选择晶体管。每个存储器单元可以通过第一字线和第二字线驱动，第一字线和第二字线彼此交叉。存储单元配置尤其是DRAM配置。

6. 发明授权

US08097915B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08097915B2
公开(公告)日：2012-01-17
申请号：US11139976
申请日：2005-05-31
申请人： Wolfgang Rösner , Franz Hofmann , Michael Specht , Martin Städele , Johannes Luyken
发明人： Wolfgang Rösner , Franz Hofmann , Michael Specht , Martin Städele , Johannes Luyken
IPC分类号： H01L31/119
CPC分类号： H01L27/108 , H01L27/10802 , H01L27/1203 , H01L29/7393
摘要： A semiconductor memory device comprises a plurality of memory cells, each memory cell having a respective transistor. The transistor comprises a transistor body of a first conductivity type, a drain area and a source area each having a second conductivity type, wherein said drain area and source area are embedded in the transistor body on a first surface of said transistor body, a gate structure having a gate dielectric layer and a gate electrode. Said gate structure is arranged between said drain area and said source area. An emitter area of said first conductivity type is provided wherein said emitter area is arranged on top of said drain area.
摘要翻译：半导体存储器件包括多个存储单元，每个存储单元具有相应的晶体管。晶体管包括第一导电类型的晶体管体，漏极区域和源极区域，每个具有第二导电类型，其中所述漏极区域和源极区域嵌入在所述晶体管本体的第一表面上的晶体管本体中，栅极具有栅极电介质层和栅电极的结构。所述栅极结构布置在所述漏极区域和所述源极区域之间。提供了所述第一导电类型的发射极区域，其中所述发射极区域布置在所述漏极区域的顶部。

7. 发明授权

US07214582B2 Semiconductor substrate and semiconductor circuit formed therein and fabrication methods 有权
标题翻译：其中形成半导体衬底和半导体电路及其制造方法
公开(公告)号：US07214582B2
公开(公告)日：2007-05-08
申请号：US10523944
申请日：2003-09-13
申请人： Franz Hofmann , Volker Lehmann , Lothar Risoh , Wolfgang Rösner , Michael Specht
发明人： Franz Hofmann , Volker Lehmann , Lothar Risoh , Wolfgang Rösner , Michael Specht
IPC分类号： H01L21/8242
CPC分类号： H01L27/1087 , H01L21/84 , H01L27/10832 , H01L27/10867 , H01L27/1203 , H01L28/82 , H01L29/66181 , H01L29/945
摘要： A semiconductor substrate and a semiconductor circuit formed therein and associated fabrication methods are provided. A multiplicity of depressions with a respective dielectric layer and a capacitor electrode are formed for realizing buried capacitors in a carrier substrate and an actual semiconductor component layer being insulated from the carrier substrate by an insulation layer.
摘要翻译：提供了一种形成在其中的半导体衬底和半导体电路及其制造方法。形成具有相应电介质层和电容器电极的多个凹陷，用于在载体衬底中实现埋入式电容器，并且通过绝缘层与实施方式的半导体组件层与载体衬底绝缘。

8. 发明授权

US06362502B1 DRAM cell circuit 有权
标题翻译： DRAM单元电路
公开(公告)号：US06362502B1
公开(公告)日：2002-03-26
申请号：US09692118
申请日：2000-10-19
申请人： Wolfgang Rösner , Thomas Schulz , Lothar Risch , Franz Hofmann
发明人： Wolfgang Rösner , Thomas Schulz , Lothar Risch , Franz Hofmann
IPC分类号： H01L27108
CPC分类号： H01L27/1203 , H01L27/108 , H01L27/10876
摘要： A memory cell contains a memory transistor and a transfer transistor. A gate electrode of the transfer transistor and a control gate electrode of the memory transistor are connected to a word line. The memory transistor has a floating gate electrode that is isolated from a channel region of the memory transistor by a first dielectric layer and is connected to a first source/drain region of the transfer transistor. The control gate electrode is isolated from the floating gate electrode by a second dielectric layer. A first source/drain region of the memory transistor is connected to a bit line. The memory and transfer transistors are preferably of different conductivity types. During the writing of information, the transfer transistor is in the on-state and the memory transistor is in the off-state. During the reading-out of information, the transfer transistor is in the off-state and the memory transistor is in the on-state.
摘要翻译：存储单元包含存储晶体管和转移晶体管。转移晶体管的栅电极和存储晶体管的控制栅电极连接到字线。存储晶体管具有通过第一介电层与存储晶体管的沟道区隔离并与转移晶体管的第一源极/漏极区连接的浮栅电极。控制栅电极通过第二电介质层与浮置栅电极隔离。存储晶体管的第一源/漏区连接到位线。存储器和转移晶体管优选地具有不同的导电类型。在写入信息期间，传输晶体管处于导通状态，并且存储晶体管处于截止状态。在读出信息期间，传输晶体管处于截止状态，并且存储晶体管处于导通状态。

9. 发明授权

US07709827B2 Vertically integrated field-effect transistor having a nanostructure therein 失效
标题翻译：其中具有纳米结构的垂直集成的场效应晶体管
公开(公告)号：US07709827B2
公开(公告)日：2010-05-04
申请号：US10533550
申请日：2003-10-29
申请人： Andrew Graham , Franz Hofmann , Wolfgang Hönlein , Johannes Kretz , Franz Kreupl , Erhard Landgraf , Johannes Richard Luyken , Wolfgang Rösner , Thomas Schulz , Michael Specht
发明人： Andrew Graham , Franz Hofmann , Wolfgang Hönlein , Johannes Kretz , Franz Kreupl , Erhard Landgraf , Johannes Richard Luyken , Wolfgang Rösner , Thomas Schulz , Michael Specht
IPC分类号： H01L21/8238
CPC分类号： H01L29/78642 , B82Y10/00 , H01L27/283 , H01L29/0673 , H01L29/0676 , H01L29/66439 , H01L29/66742 , H01L29/66787 , H01L29/775 , H01L51/0048 , H01L51/0052 , H01L51/0512
摘要： The invention relates to a vertical integrated component, a component arrangement and a method for production of a vertical integrated component. The vertical integrated component has a first electrical conducting layer, a mid layer, partly embodied from dielectric material on the first electrical conducting layer, a second electrical conducting layer on the mid layer and a nanostructure integrated in a through hold introduced in the mid layer. A first end section of the nanostructure is coupled to the first electrical conducting layer and a second end section is coupled to the second electrical conducting layer. The mid layer includes a third electrical conducting layer between two adjacent dielectric partial layers, the thickness of which is less than the thickness of at least one of the dielectric partial layers.
摘要翻译：本发明涉及垂直集成部件，部件布置和用于生产垂直集成部件的方法。垂直集成部件具有第一导电层，中间层，其部分地由第一导电层上的介电材料实现，中间层上的第二导电层和集成在中间层中的贯通保持件中的纳米结构。纳米结构的第一端部分耦合到第一导电层，第二端部分耦合到第二导电层。中间层包括在两个相邻的介电部分层之间的第三导电层，其厚度小于介电部分层中的至少一个的厚度。

10. 发明授权

US07368752B2 DRAM memory cell 失效
标题翻译： DRAM存储单元
公开(公告)号：US07368752B2
公开(公告)日：2008-05-06
申请号：US10839800
申请日：2004-05-06
申请人： Richard J. Luyken , Franz Hofmann , Lothar Risch , Dirk Manger , Wolfgang Rösner , Till Schlösser , Michael Specht
发明人： Richard J. Luyken , Franz Hofmann , Lothar Risch , Dirk Manger , Wolfgang Rösner , Till Schlösser , Michael Specht
IPC分类号： H01L27/108 , H01L29/12 , H01L31/112
CPC分类号： H01L27/10823 , H01L27/10808 , H01L27/10826 , H01L27/10829 , H01L27/10891 , H01L29/7851
摘要： A DRAM memory cell is provided with a selection transistor, which is arranged horizontally at a semiconductor substrate surface and has a first source/drain electrode, a second source/drain electrode, a channel layer arranged between the first and the second source/drain electrode in the semiconductor substrate, and a gate electrode, which is arranged along the channel layer and is electrically insulated from the channel layer, a storage capacitor, which has a first capacitor electrode and a second capacitor electrode, insulated from the first capacitor electrode, one of the capacitor electrodes of the storage capacitor being electrically conductively connected to one of the source/drain electrodes of the selection transistor, and a semiconductor substrate electrode on the rear side, the gate electrode enclosing the channel layer at at least two opposite sides.
摘要翻译： DRAM存储单元设置有选择晶体管，该晶体管被水平地布置在半导体衬底表面处并且具有第一源极/漏极，第二源极/漏极，布置在第一和第二源极/漏极之间的沟道层在所述半导体基板中，沿着所述沟道层配置并与所述沟道层电绝缘的栅电极具有与所述第一电容电极绝缘的第一电容电极和第二电容电极的保持电容器，所述存储电容器的电容器电极与所述选择晶体管的源极/漏极之一导电地连接，并且在后侧具有半导体衬底电极，所述栅电极在至少两个相对的两侧包围所述沟道层。

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