专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

81. 发明申请

US20070196999A1 Method For Manufacturing Semiconductor Device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20070196999A1
公开(公告)日：2007-08-23
申请号：US11632048
申请日：2005-07-28
申请人： Tomoko Tamura , Eiji Sugiyama , Yoshitaka Dozen , Koji Dairiki , Takuya Tsurume
发明人： Tomoko Tamura , Eiji Sugiyama , Yoshitaka Dozen , Koji Dairiki , Takuya Tsurume
IPC分类号： H01L21/00 , H01L21/30 , H01L21/46
CPC分类号： H01L21/02381 , H01L21/84 , H01L27/1214 , H01L27/1266 , H01L27/13 , H01L2221/68359 , H01L2221/68368 , H01L2224/81001
摘要： A release layer formed over a substrate; at least one of thin film integrated circuits is formed over the release layer; a film is formed over each of the at least one of thin film integrated circuits; and the release layer is removed by using an etchant; thus, the at least one of thin film integrated circuits is peeled from the substrate. A semiconductor device is formed by sealing the peeled thin film integrated circuit by lamination or the like.
摘要翻译：形成在衬底上的释放层; 在剥离层上形成薄膜集成电路中的至少一个; 在薄膜集成电路中的至少一个上形成膜; 并通过使用蚀刻剂除去释放层; 因此，薄膜集成电路中的至少一个从基板剥离。半导体器件通过层压等密封剥离的薄膜集成电路而形成。

82. 发明申请

US20060267204A1 Semiconductor device and manufacturing method thereof 有权
公开(公告)号：US20060267204A1
公开(公告)日：2006-11-30
申请号：US11436090
申请日：2006-05-18
申请人： Hidekazu Takahashi , Daiki Yamada , Kyosuke Ito , Eiji Sugiyama , Yoshitaka Dozen
发明人： Hidekazu Takahashi , Daiki Yamada , Kyosuke Ito , Eiji Sugiyama , Yoshitaka Dozen
IPC分类号： H01L23/48
CPC分类号： H01L23/66 , H01L23/49855 , H01L2924/0002 , H01L2924/00
摘要： The semiconductor device of the invention includes a transistor, an insulating layer provided over the transistor, a first conductive layer (corresponding to a source wire or a drain wire) electrically connected to a source region or a drain region of the transistor through an opening portion provided in the insulating layer, a first resin layer provided over the insulating layer and the first conductive layer, a layer containing conductive particles which is electrically connected to the first conductive layer through an opening portion provided in the first resin layer, and a substrate provided with a second resin layer and a second conductive layer serving as an antenna. In the semiconductor device having the above-described structure, the second conductive layer is electrically connected to the first conductive layer with the layer containing conductive particles interposed therebetween. In addition, the second resin layer is provided over the first resin layer.

83. 发明申请

US20060199382A1 Manufacturing Method of Semiconductor Device 有权
标题翻译：半导体器件的制造方法
公开(公告)号：US20060199382A1
公开(公告)日：2006-09-07
申请号：US11276349
申请日：2006-02-24
申请人： Eiji Sugiyama , Yoshitaka Dozen , Yumiko Fukumoto , Hideaki Kuwabara , Shunpei Yamazaki
发明人： Eiji Sugiyama , Yoshitaka Dozen , Yumiko Fukumoto , Hideaki Kuwabara , Shunpei Yamazaki
IPC分类号： H01L21/44 , H01L21/461
CPC分类号： H01L21/7806 , H01L21/31111 , H01L21/6708 , H01L21/67132 , H01L27/1214 , H01L27/1266 , H01L2021/775
摘要： The present invention has an object to perform a peeling treatment in a short time. Peeling is performed while a peeling layer is exposed to an atmosphere of an etching gas. Alternatively, peeling is performed while an etching gas for a peeling layer is blown to the peeling layer in an atmosphere of an etching gas. Specifically, an etching gas is blown to a part to be peeled while a layer to be peeled is torn off from a substrate. Alternatively, peeling is performed in an etchant for a peeling layer while supplying an etchant to the peeling layer.
摘要翻译：本发明的目的是在短时间内进行剥离处理。在剥离层暴露于蚀刻气体的气氛的同时进行剥离。或者，在蚀刻气体的气氛中将用于剥离层的蚀刻气体吹向剥离层的同时进行剥离。具体地说，将蚀刻气体吹向待剥离的部分，同时从基板上撕下被剥离层。或者，在用于剥离层的蚀刻剂中进行剥离，同时向剥离层供给蚀刻剂。

84. 发明申请

US20060063309A1 Method for manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20060063309A1
公开(公告)日：2006-03-23
申请号：US11229497
申请日：2005-09-20
申请人： Eiji Sugiyama , Kyosuke Ito
发明人： Eiji Sugiyama , Kyosuke Ito
IPC分类号： H01L21/50 , H01L21/78 , H01L21/00
CPC分类号： H01L27/1266 , H01L21/7806 , H01L27/1214
摘要： In the case where an integrated circuit formed of a thin film is formed over a substrate and peeled from the substrate, a fissure (also referred to as crack) is generated in the integrated circuit in some cases. The present invention is to restrain the generation of a fissure by fixing the proceeding direction of etching in one direction to make a peeled layer warp in one direction in accordance with the proceeding of etching. For example, the proceeding of etching can be controlled by utilizing the fact that a portion where a substrate is in contact with a base insulating layer is not etched in the case of patterning a peeling layer provided over the substrate, then forming the base insulating layer, and then fixing a peeled layer by the portion where the substrate is in contact with the base insulating layer.
摘要翻译：在由薄膜形成的集成电路形成在基板上并从基板剥离的情况下，在某些情况下，在集成电路中产生裂缝（也称为裂纹）。本发明是通过在一个方向上固定前进方向的蚀刻来抑制裂缝的产生，以便根据蚀刻的进行使剥离层在一个方向上翘曲。例如，可以通过利用以下事实来控制蚀刻的进行：在图案化设置在基板上的剥离层的情况下，基板与基底绝缘层接触的部分不被蚀刻，然后形成基底绝缘层，然后通过基板与基底绝缘层接触的部分固定剥离层。

85. 发明申请

US20050167573A1 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20050167573A1
公开(公告)日：2005-08-04
申请号：US10952914
申请日：2004-09-30
申请人： Junya Maruyama , Toru Takayama , Masafumi Morisue , Ryosuke Watanabe , Eiji Sugiyama , Susumu Okazaki , Kazuo Nishi , Jun Koyama , Takeshi Osada , Takanori Matsuzaki
发明人： Junya Maruyama , Toru Takayama , Masafumi Morisue , Ryosuke Watanabe , Eiji Sugiyama , Susumu Okazaki , Kazuo Nishi , Jun Koyama , Takeshi Osada , Takanori Matsuzaki
IPC分类号： H01L27/146 , H01J40/14 , H01L21/82 , H01L27/14 , H01L31/00 , H01L31/10
CPC分类号： H01L27/1266 , H01L27/1214 , H01L27/1218 , H01L27/14609 , H01L27/14665 , H01L2224/16225
摘要： The object of the present invention is to miniaturize the area occupied by the element and to integrate a plenty of elements in a limited area so that the sensor element can have higher output and smaller size. In the present invention, higher output and miniaturization are achieved by uniting a sensor element using an amorphous semiconductor film (typically an amorphous silicon film) and an output amplifier circuit including a TFT with a semiconductor film having a crystal structure (typically a poly-crystalline silicon film) used as an active layer over a plastic film substrate that can resist the temperature in the process for mounting such as a solder reflow process. According to the present invention, the sensor element that can resist the bending stress can be obtained.
摘要翻译：本发明的目的是使元件占据的面积小型化，并将大量的元件集成在有限的区域中，使传感器元件具有更高的输出和更小的尺寸。在本发明中，通过使用非晶半导体膜（通常为非晶硅膜）的传感器元件和包括具有晶体结构的半导体膜（通常为多晶体）的TFT的输出放大器电路来实现更高的输出和小型化硅膜）用作塑料膜基材上的活性层，其能够抵抗诸如焊料回流工艺的安装过程中的温度。根据本发明，可以获得能够抵抗弯曲应力的传感器元件。

86. 发明授权

US5570766A End bearing for one-way clutch 失效
标题翻译：单向离合器的端部轴承
公开(公告)号：US5570766A
公开(公告)日：1996-11-05
申请号：US403469
申请日：1995-03-14
申请人： Eichi Sato , Yoshihiro Kaku , Yuji Yokota , Hiroshi Shibata , Masanori Hatanaka , Eiji Sugiyama , Jun Sonoda , Tetsuaki Numata
发明人： Eichi Sato , Yoshihiro Kaku , Yuji Yokota , Hiroshi Shibata , Masanori Hatanaka , Eiji Sugiyama , Jun Sonoda , Tetsuaki Numata
IPC分类号： F16C33/12 , F16D41/07 , F16H57/08 , F16D41/06
CPC分类号： F16C33/12 , F16C33/122 , F16D41/07 , F16H57/08 , F16C2204/60
摘要： An end bearing for one-way clutch which is preferred for use in an automatic transmission is disclosed. The end bearing comprises a body formed of a steel plate, a hard coating applied to the surface of the body, and a soft coating applied to the surface of the hard coating. The steel plate of the body assures a sufficient rigidity. Regions of the end bearing which provide sliding surfaces are covered by a soft coating and a hard coating, which improves the anti-seizing resistance and the durability of the end bearing.
摘要翻译：公开了一种优选用于自动变速器的单向离合器的端部轴承。端轴承包括由钢板形成的主体，施加到主体表面的硬涂层，以及施加到硬涂层表面的软涂层。机身钢板确保足够的刚性。提供滑动表面的端部轴承的区域被软涂层和硬涂层覆盖，这提高了端部轴承的防卡死性和耐久性。

87. 发明授权

US4779009A Master-slave type flip-flop circuit 失效
标题翻译：主从型触发电路
公开(公告)号：US4779009A
公开(公告)日：1988-10-18
申请号：US886828
申请日：1986-07-18
申请人： Hiroyuki Tsunoi , Eiji Sugiyama , Motohiro Seto
发明人： Hiroyuki Tsunoi , Eiji Sugiyama , Motohiro Seto
IPC分类号： G11C11/40 , H03K3/289 , H03K3/284 , H03K19/00
CPC分类号： H03K3/289
摘要： In a master-slave type flip-flop circuit including a normal function in a normal mode for flip/flop operation and a scanning function in a scanning mode for testing an integrated circuit, the master-slave type flip-flop circuit comprises: a master stage having a first pair of differential transistors for taking in data, a second pair of differential transistors for latching data taken in to the first pair of differential transistors, a third pair of differential transistors for taking in scanning data, and a fourth pair of differential transistors for activating the second and third pair of differential transistors in the scanning mode; and a slave stage having a first pair of differential transistors for taking in data from the master stage, a second pair of differential transistors for latching data taken in to the first pair of differential transistors, a third pair of differential transistors for latching scanning data, and a fourth pair of differential transistors for activating the first and third pair of differential transistors in the scanning mode.
摘要翻译：主从型触发电路包括：主从触发器电路，包括用于触发/翻转操作的正常模式的正常功能和用于测试集成电路的扫描模式的扫描功能，主从触发器电路包括：主器件阶段具有用于接收数据的第一对差分晶体管，用于锁存取入第一对差分晶体管的数据的第二对差分晶体管，用于接收扫描数据的第三对差分晶体管和第四对差分用于在扫描模式下激活第二和第三对差分晶体管的晶体管; 以及具有用于从主级接收数据的第一对差分晶体管的子级，用于锁存取入第一对差分晶体管的数据的第二对差分晶体管，用于锁存扫描数据的第三对差分晶体管，以及第四对差分晶体管，用于在扫描模式下激活第一和第三对差分晶体管。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式