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1. 发明授权

US4779009A Master-slave type flip-flop circuit 失效
标题翻译：主从型触发电路
公开(公告)号：US4779009A
公开(公告)日：1988-10-18
申请号：US886828
申请日：1986-07-18
申请人： Hiroyuki Tsunoi , Eiji Sugiyama , Motohiro Seto
发明人： Hiroyuki Tsunoi , Eiji Sugiyama , Motohiro Seto
IPC分类号： G11C11/40 , H03K3/289 , H03K3/284 , H03K19/00
CPC分类号： H03K3/289
摘要： In a master-slave type flip-flop circuit including a normal function in a normal mode for flip/flop operation and a scanning function in a scanning mode for testing an integrated circuit, the master-slave type flip-flop circuit comprises: a master stage having a first pair of differential transistors for taking in data, a second pair of differential transistors for latching data taken in to the first pair of differential transistors, a third pair of differential transistors for taking in scanning data, and a fourth pair of differential transistors for activating the second and third pair of differential transistors in the scanning mode; and a slave stage having a first pair of differential transistors for taking in data from the master stage, a second pair of differential transistors for latching data taken in to the first pair of differential transistors, a third pair of differential transistors for latching scanning data, and a fourth pair of differential transistors for activating the first and third pair of differential transistors in the scanning mode.
摘要翻译：主从型触发电路包括：主从触发器电路，包括用于触发/翻转操作的正常模式的正常功能和用于测试集成电路的扫描模式的扫描功能，主从触发器电路包括：主器件阶段具有用于接收数据的第一对差分晶体管，用于锁存取入第一对差分晶体管的数据的第二对差分晶体管，用于接收扫描数据的第三对差分晶体管和第四对差分用于在扫描模式下激活第二和第三对差分晶体管的晶体管; 以及具有用于从主级接收数据的第一对差分晶体管的子级，用于锁存取入第一对差分晶体管的数据的第二对差分晶体管，用于锁存扫描数据的第三对差分晶体管，以及第四对差分晶体管，用于在扫描模式下激活第一和第三对差分晶体管。

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