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81. 发明授权

US08368136B2 Integrating a capacitor in a metal gate last process 有权
标题翻译：将电容器集成在金属栅极最后工艺中
公开(公告)号：US08368136B2
公开(公告)日：2013-02-05
申请号：US12256132
申请日：2008-10-22
申请人： Harry Chuang , Tzung-Chi Lee , Kong-Beng Thei , Sheng-Chen Chung , Mong-Song Liang
发明人： Harry Chuang , Tzung-Chi Lee , Kong-Beng Thei , Sheng-Chen Chung , Mong-Song Liang
IPC分类号： H01L27/04
CPC分类号： H01L27/0629 , H01L27/11 , H01L29/94
摘要： A semiconductor device is provided which includes a semiconductor substrate having a first region and a second region, transistors having metal gates formed in the first region, and at least one capacitor formed in the second region. The capacitor includes a top electrode having at least one stopping structure formed in the top electrode, the at least one stopping structure being of a different material from the top electrode, a bottom electrode, and a dielectric layer interposed between the top electrode and the bottom electrode.
摘要翻译：提供一种半导体器件，其包括具有第一区域和第二区域的半导体衬底，在第一区域中形成有金属栅极的晶体管，以及形成在第二区域中的至少一个电容器。所述电容器包括顶电极，所述顶电极具有形成在所述顶电极中的至少一个止动结构，所述至少一个止动结构与所述顶电极，底电极和介于所述顶电极和所述底电极之间的电介质层具有不同的材料电极。

82. 发明授权

US08349680B2 High-k metal gate CMOS patterning method 有权
标题翻译：高k金属栅极CMOS图案化方法
公开(公告)号：US08349680B2
公开(公告)日：2013-01-08
申请号：US12536629
申请日：2009-08-06
申请人： Kong-Beng Thei , Harry Chuang , Ryan Chia-Jen Chen , Su-Chen Lai , Yi-Shien Mor , Yi-Hsing Chen , Gary Shen , Yu Chao Lin
发明人： Kong-Beng Thei , Harry Chuang , Ryan Chia-Jen Chen , Su-Chen Lai , Yi-Shien Mor , Yi-Hsing Chen , Gary Shen , Yu Chao Lin
IPC分类号： H01L21/8238
CPC分类号： H01L21/31645 , H01L21/31604 , H01L21/823842
摘要： The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a semiconductor substrate having a first active region and a second active region, forming a high-k dielectric layer over the semiconductor substrate, forming a capping layer over the high-k dielectric layer, forming a first metal layer over the capping layer, the first metal layer having a first work function, forming a mask layer over the first metal layer in the first active region, removing the first metal layer and at least a portion of the capping layer in the second active region using the mask layer, and forming a second metal layer over the partially removed capping layer in the second active region, the second metal layer having a second work function.
摘要翻译：本公开提供了制造半导体器件的方法。该方法包括提供具有第一有源区和第二有源区的半导体衬底，在半导体衬底上形成高k电介质层，在高k电介质层上形成覆盖层，在覆盖层上形成第一金属层第一金属层具有第一功函数，在第一有源区中的第一金属层上形成掩模层，使用掩模层去除第一金属层和第二有源区中的覆盖层的至少一部分并且在所述第二有源区域中的所述部分去除的覆盖层上形成第二金属层，所述第二金属层具有第二功函数。

83. 发明授权

US08216888B2 Eliminating poly uni-direction line-end shortening using second cut 有权
标题翻译：使用第二次切割消除多边形单向线端缩短
公开(公告)号：US08216888B2
公开(公告)日：2012-07-10
申请号：US13079435
申请日：2011-04-04
申请人： Harry Chuang , Kong-Beng Thei
发明人： Harry Chuang , Kong-Beng Thei
IPC分类号： H01L21/82
CPC分类号： H01L29/4238 , H01L21/823437 , H01L27/0207
摘要： A method of forming an integrated circuit structure includes providing a substrate including a first active region and a second active region; forming a gate electrode layer over the substrate; and etching the gate electrode layer. The remaining portions of the gate electrode layer include a first gate strip and a second gate strip substantially parallel to each other; and a sacrificial strip unparallel to, and interconnecting, the first gate strip and the second gate strip. The sacrificial strip is between the first active region and the second active region. The method further includes forming a mask layer covering portions of the first gate strip and the second gate strip, wherein the sacrificial strip and portions of the first gate strip and the second gate strip are exposed through an opening in the mask layer; and etching the sacrificial strip and the portions of the first gate strip and the second gate strip through the opening.
摘要翻译：形成集成电路结构的方法包括提供包括第一有源区和第二有源区的衬底; 在所述衬底上形成栅电极层; 并蚀刻栅电极层。栅极电极层的其余部分包括彼此基本平行的第一栅极条和第二栅极条; 以及不平行于并互连第一栅极条和第二栅极条的牺牲条。牺牲条在第一有源区和第二有源区之间。所述方法还包括形成覆盖所述第一栅极条和所述第二栅极条的部分的掩模层，其中所述牺牲条和所述第一栅极条和所述第二栅极条的部分通过所述掩模层中的开口暴露; 并且蚀刻所述牺牲条和所述第一栅极条和所述第二栅极条的所述部分通过所述开口。

84. 发明申请

US20110284972A1 Modifying Work Function in PMOS Devices by Counter-Doping 有权
标题翻译：通过反掺杂修改PMOS器件中的工作功能
公开(公告)号：US20110284972A1
公开(公告)日：2011-11-24
申请号：US13204461
申请日：2011-08-05
申请人： Chun-Yi Lee , Harry Chuang , Ping-Wei Wang , Kong-Beng Thei
发明人： Chun-Yi Lee , Harry Chuang , Ping-Wei Wang , Kong-Beng Thei
IPC分类号： H01L21/8238 , H01L27/092
CPC分类号： H01L27/0883 , G11C11/412 , H01L27/092 , H01L27/105 , H01L27/11 , H01L27/1104 , H01L27/1116 , H01L29/1083 , H01L29/165 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7848 , Y10S438/919
摘要： A semiconductor structure comprising an SRAM/inverter cell and a method for forming the same are provided, wherein the SRAM/inverter cell has an improved write margin. The SRAM/inverter cell includes a pull-up PMOS device comprising a gate dielectric over the semiconductor substrate, a gate electrode on the gate dielectric wherein the gate electrode comprises a p-type impurity and an n-type impurity, and a stressor formed in a source/drain region. The device drive current of the pull-up PMOS device is reduced due to the counter-doping of the gate electrode.
摘要翻译：提供了包括SRAM /反相器单元的半导体结构及其形成方法，其中SRAM /反相器单元具有改善的写入裕度。 SRAM /反相器单元包括上拉PMOS器件，其包括半导体衬底上的栅极电介质，栅极电介质上的栅电极，其中栅电极包括p型杂质和n型杂质，以及形成在源极/漏极区域。上拉PMOS器件的器件驱动电流由于栅电极的反掺杂而降低。

85. 发明授权

US08048752B2 Spacer shape engineering for void-free gap-filling process 有权
标题翻译：无间隙填充过程的间隔形状工程
公开(公告)号：US08048752B2
公开(公告)日：2011-11-01
申请号：US12179395
申请日：2008-07-24
申请人： Ming-Yuan Wu , Yi-Shien Mor , Chih-Tang Peng , Chiung-Han Yeh , Kong-Beng Thei , Harry Chuang , Mong-Song Liang
发明人： Ming-Yuan Wu , Yi-Shien Mor , Chih-Tang Peng , Chiung-Han Yeh , Kong-Beng Thei , Harry Chuang , Mong-Song Liang
IPC分类号： H01L21/336
CPC分类号： H01L21/823481 , H01L21/823468 , H01L21/823475 , H01L29/6653 , H01L29/6656 , H01L29/7833 , H01L29/7843
摘要： A method of forming a semiconductor device includes providing a semiconductor substrate; forming a gate stack on the semiconductor substrate; forming a gate spacer adjacent to a sidewall of the gate stack; thinning the gate spacer; and forming a secondary gate spacer on a sidewall of the gate spacer after the step of thinning the gate spacer.
摘要翻译：一种形成半导体器件的方法包括提供半导体衬底; 在半导体衬底上形成栅叠层; 形成邻近所述栅叠层的侧壁的栅极间隔; 减薄栅间隔; 以及在所述栅极间隔物变薄的步骤之后，在所述栅极间隔物的侧壁上形成次级栅极间隔物。

86. 发明申请

US20110256677A1 NOVEL POLY RESISTOR AND POLY EFUSE DESIGN FOR REPLACEMENT GATE TECHNOLOGY 有权
标题翻译：新型POLY电阻和POLY EFUSE设计替代GATE技术
公开(公告)号：US20110256677A1
公开(公告)日：2011-10-20
申请号：US13174368
申请日：2011-06-30
申请人： Harry Chuang , Kong-Beng Thei
发明人： Harry Chuang , Kong-Beng Thei
IPC分类号： H01L21/77 , H01L21/336
CPC分类号： H01L27/0629 , H01L23/5256 , H01L28/20 , H01L29/66545 , H01L29/66628 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： Methods for fabricating a semiconductor device are disclosed. In an example, a method includes forming an isolation region on a substrate, wherein the isolation region extends a depth into the substrate from a substrate surface; forming a recess in the isolation region, wherein the recess is defined by a concave surface of the isolation region; and forming a first gate structure over the substrate surface and a second gate structure over the concave surface of the isolation region.
摘要翻译：公开了制造半导体器件的方法。在一个实例中，一种方法包括在衬底上形成隔离区域，其中隔离区域从衬底表面向衬底延伸深度; 在所述隔离区域中形成凹部，其中所述凹部由所述隔离区域的凹面限定; 以及在所述衬底表面上形成第一栅极结构，以及在所述隔离区域的所述凹表面上方形成第二栅极结构。

87. 发明申请

US20110227189A1 Dishing-Free Gap-Filling with Multiple CMPs 有权
标题翻译：无间隙填充多个CMP
公开(公告)号：US20110227189A1
公开(公告)日：2011-09-22
申请号：US13151666
申请日：2011-06-02
申请人： Ming-Yuan Wu , Kong-Beng Thei , Chiun-Han Yeh , Harry Chuang , Mong-Song Liang
发明人： Ming-Yuan Wu , Kong-Beng Thei , Chiun-Han Yeh , Harry Chuang , Mong-Song Liang
IPC分类号： H01L27/04
CPC分类号： H01L21/76883 , H01L21/76229
摘要： A method of forming an integrated circuit structure includes providing a semiconductor substrate; forming patterned features over the semiconductor substrate, wherein gaps are formed between the patterned features; filling the gaps with a first filling material, wherein the first filling material has a first top surface higher than top surfaces of the patterned features; and performing a first planarization to lower the top surface of the first filling material, until the top surfaces of the patterned features are exposed. The method further includes depositing a second filling material, wherein the second filling material has a second top surface higher than the top surfaces of the patterned features; and performing a second planarization to lower the top surface of the second filling material, until the top surfaces of the patterned features are exposed.
摘要翻译：形成集成电路结构的方法包括提供半导体衬底; 在所述半导体衬底上形成图案化特征，其中在所述图案化特征之间形成间隙; 用第一填充材料填充间隙，其中第一填充材料具有高于图案化特征的顶表面的第一顶表面; 以及执行第一平面化以降低所述第一填充材料的顶表面，直到所述图案化特征的顶表面露出。该方法还包括沉积第二填充材料，其中第二填充材料具有高于图案化特征的顶表面的第二顶表面; 以及执行第二平面化以降低第二填充材料的顶表面，直到图案化特征的顶表面露出。

88. 发明授权

US07923321B2 Method for gap filling in a gate last process 有权
标题翻译：最后一道工序间隙填充方法
公开(公告)号：US07923321B2
公开(公告)日：2011-04-12
申请号：US12487894
申请日：2009-06-19
申请人： Su-Chen Lai , Kong-Beng Thei , Harry Chuang , Gary Shen
发明人： Su-Chen Lai , Kong-Beng Thei , Harry Chuang , Gary Shen
IPC分类号： H01L21/8238
CPC分类号： H01L29/7848 , H01L21/823842 , H01L29/165 , H01L29/517 , H01L29/665 , H01L29/66545 , H01L29/66628
摘要： A method is provided for fabricating a semiconductor device that includes providing a semiconductor substrate having a first region and a second region, forming a high-k dielectric layer over the substrate, forming a silicon layer over the high-k dielectric layer, forming a hard mask layer over the silicon layer, patterning the hard mask layer, silicon layer, and high-k dielectric layer to form first and second gate structures over the first and second regions, respectively, forming a contact etch stop layer (CESL) over the first and second gate structures, modifying a profile of the CESL by an etching process, forming an inter-layer dielectric (ILD) over the modified CESL, performing a chemical mechanical polishing (CMP) on the ILD to expose the silicon layer of the first and second gate structures, respectively, and removing the silicon layer from the first and second gate structures, respectively, and replacing it with metal gate structures.
摘要翻译：提供一种用于制造半导体器件的方法，该半导体器件包括提供具有第一区域和第二区域的半导体衬底，在衬底上形成高k电介质层，在高k电介质层上形成硅层，形成硬的掩模层，图案化硬掩模层，硅层和高k电介质层，以分别在第一和第二区域上形成第一和第二栅极结构，在第一和第二区域上形成接触蚀刻停止层（CESL）和第二栅极结构，通过蚀刻工艺修改CESL的轮廓，在改性CESL上形成层间电介质（ILD），在ILD上进行化学机械抛光（CMP）以暴露第一和第二栅极结构的硅层第二栅极结构，并分别从第一和第二栅极结构去除硅层，并用金属栅极结构代替硅层。

89. 发明申请

US20110059601A1 METHOD FOR TUNING A WORK FUNCTION OF HIGH-K METAL GATE DEVICES 有权
标题翻译：用于调谐高K金属栅极器件功能的方法
公开(公告)号：US20110059601A1
公开(公告)日：2011-03-10
申请号：US12944221
申请日：2010-11-11
申请人： Chiung-Han Yeh , Sheng-Chen Chung , Kong-Beng Thei , Harry Chuang
发明人： Chiung-Han Yeh , Sheng-Chen Chung , Kong-Beng Thei , Harry Chuang
IPC分类号： H01L21/768 , H01L21/8234
CPC分类号： H01L21/823842 , H01L21/28088 , H01L29/517 , H01L29/66545
摘要： A method of fabricating a semiconductor device includes forming a first trench and a second trench on a semiconductor substrate and forming a first metal layer in the first and second trenches. The first metal layer is then removed, at least partially, from within the first trench but not the second trench. A second metal layer and a third metal layer are formed in the first and second trenches. A thermal process is used to reflow the second metal layer and the third metal layer
摘要翻译：制造半导体器件的方法包括在半导体衬底上形成第一沟槽和第二沟槽，并在第一和第二沟槽中形成第一金属层。然后至少部分地从第一沟槽内除去第一金属层而不是第二沟槽。在第一和第二沟槽中形成第二金属层和第三金属层。使用热处理来回流第二金属层和第三金属层

90. 发明授权

US07750416B2 Modifying work function in PMOS devices by counter-doping 失效
标题翻译：通过反掺杂改进PMOS器件的功能
公开(公告)号：US07750416B2
公开(公告)日：2010-07-06
申请号：US11416938
申请日：2006-05-03
申请人： Chun-Yi Lee , Harry Chuang , Ping-Wei Wang , Kong-Beng Thei
发明人： Chun-Yi Lee , Harry Chuang , Ping-Wei Wang , Kong-Beng Thei
IPC分类号： H01L29/76
CPC分类号： H01L27/0883 , G11C11/412 , H01L27/092 , H01L27/105 , H01L27/11 , H01L27/1104 , H01L27/1116 , H01L29/1083 , H01L29/165 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7848 , Y10S438/919
摘要： A semiconductor structure comprising an SRAM/inverter cell and a method for forming the same are provided, wherein the SRAM/inverter cell has an improved write margin. The SRAM/inverter cell includes a pull-up PMOS device comprising a gate dielectric over the semiconductor substrate, a gate electrode on the gate dielectric wherein the gate electrode comprises a p-type impurity and an n-type impurity, and a stressor formed in a source/drain region. The device drive current of the pull-up PMOS device is reduced due to the counter-doping of the gate electrode.
摘要翻译：提供了包括SRAM /反相器单元的半导体结构及其形成方法，其中SRAM /反相器单元具有改善的写入裕度。 SRAM /反相器单元包括上拉PMOS器件，其包括半导体衬底上的栅极电介质，栅极电介质上的栅电极，其中栅电极包括p型杂质和n型杂质，以及形成在源极/漏极区域。上拉PMOS器件的器件驱动电流由于栅电极的反掺杂而降低。

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