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81. 发明授权

US07030451B2 Method and apparatus for performing nickel salicidation 有权
公开(公告)号：US07030451B2
公开(公告)日：2006-04-18
申请号：US11081908
申请日：2005-03-15
申请人： Pooi See Lee , Kin Leong Pey , Alex See , Lap Chan
发明人： Pooi See Lee , Kin Leong Pey , Alex See , Lap Chan
IPC分类号： H01L29/78
CPC分类号： H01L29/665 , H01L21/26506 , H01L21/28518 , H01L29/4933
摘要： A method and apparatus for performing nickel salicidation is disclosed. The nickel salicide process typically includes: forming a processed substrate including partially fabricated integrated circuit components and a silicon substrate; incorporating nitrogen into the processed substrate; depositing nickel onto the processed substrate; annealing the processed substrate so as to form nickel mono-silicide; removing the unreacted nickel; and performing a series procedures to complete integrated circuit fabrication. This nickel salicide process increases the annealing temperature range for which a continuous, thin nickel mono-silicide layer can be formed on silicon by salicidation. It also delays the onset of agglomeration of nickel mono-silicide thin-films to a higher annealing temperature. Moreover, this nickel salicide process delays the transformation from nickel mono-silicide to higher resistivity nickel di-silicide, to higher annealing temperature. It also reduces nickel enhanced poly-silicon grain growth to prevent layer inversion. Some embodiments of this nickel salicide process may be used in an otherwise standard salicide process, to form integrated circuit devices with low resistivity transistor gate electrodes and source/drain contacts.

82. 发明授权

US06924202B2 Heterojunction bipolar transistor with self-aligned emitter and sidewall base contact 有权
标题翻译：具有自对准发射极和侧壁基极接触的异质结双极晶体管
公开(公告)号：US06924202B2
公开(公告)日：2005-08-02
申请号：US10683142
申请日：2003-10-09
申请人： Jian Xun Li , Lap Chan , Purakh Raj Verma , Jia Zhen Zheng , Shao-fu Sanford Chu
发明人： Jian Xun Li , Lap Chan , Purakh Raj Verma , Jia Zhen Zheng , Shao-fu Sanford Chu
IPC分类号： H01L21/331 , H01L29/08 , H01L29/737
CPC分类号： H01L29/66242 , H01L29/0817 , H01L29/7378
摘要： A heterojunction bipolar transistor (HBT), and manufacturing method therfor, comprising a semiconductor substrate having a collector region is provided. A base contact layer is formed over the collector region, and a base trench is formed in the base contact layer and the collector region. An intrinsic base structure having a sidewall portion and a bottom portion is formed in the base trench. An insulating spacer is formed over the sidewall portion of the intrinsic base structure, and an emitter structure is formed over the insulating spacer and the bottom portion of the intrinsic base structure. An interlevel dielectric layer is formed over the base contact layer and the emitter structure. Connections are formed through the interlevel dielectric layer to the collector region, the base contact layer, and the emitter structure. The intrinsic base structure is silicon and at least one of silicon-germanium, silicon-germanium-carbon, and combinations thereof.
摘要翻译：提供了具有集电极区域的半导体衬底的异质结双极晶体管（HBT）及其制造方法。基极接触层形成在集电极区域上，基底沟槽形成在基极接触层和集电极区域中。在基底沟槽中形成具有侧壁部分和底部的本征基底结构。在本征基底结构的侧壁部分上形成绝缘间隔物，并且在绝缘间隔物和本征基底结构的底部上形成发射极结构。在基极接触层和发射极结构之上形成层间电介质层。通过层间绝缘层到集电极区，基极接触层和发射极结构形成连接。本征基础结构是硅和硅 - 锗，硅 - 锗 - 碳及其组合中的至少一种。

83. 发明授权

US06908824B2 Self-aligned lateral heterojunction bipolar transistor 有权
标题翻译：自对准横向异质结双极晶体管
公开(公告)号：US06908824B2
公开(公告)日：2005-06-21
申请号：US10703284
申请日：2003-11-06
申请人： Jian Xun Li , Lap Chan , Purakh Raj Verma , Jia Zhen Zheng , Shao-fu Sanford Chu
发明人： Jian Xun Li , Lap Chan , Purakh Raj Verma , Jia Zhen Zheng , Shao-fu Sanford Chu
IPC分类号： H01L21/331 , H01L29/737
CPC分类号： H01L29/66242 , H01L29/737
摘要： A method for manufacturing a lateral heterojunction bipolar transistor (HBT) is provided comprising a semiconductor substrate having a first insulating layer over the semiconductor substrate. A base trench is formed in a first silicon layer over the first insulating layer to form a collector layer over an exposed portion of the semiconductor substrate and an emitter layer over the first insulating layer. A semiconductive layer is formed on the sidewalls of the base trench to form a collector structure in contact with the collector layer and an emitter structure in contact with the emitter layer. A base structure is formed in the base trench. A plurality of connections is formed through an interlevel dielectric layer to the collector layer, the emitter layer, and the base structure. The base structure preferably is a compound semiconductive material of silicon and at least one of silicon-germanium, silicon-germanium-carbon, and combinations thereof.
摘要翻译：提供一种用于制造横向异质结双极晶体管（HBT）的方法，包括半导体衬底上的第一绝缘层的半导体衬底。基底沟槽形成在第一绝缘层上的第一硅层中，以在半导体衬底的暴露部分和第一绝缘层上的发射极层之上形成集电极层。半导体层形成在基底沟槽的侧壁上，以形成与集电极层接触的集电极结构和与发射极层接触的发射极结构。基底结构形成在基底沟槽中。通过层间电介质层到集电极层，发射极层和基底结构形成多个连接。基底结构优选是硅的化合物半导体材料和硅 - 锗，硅 - 锗 - 碳及其组合中的至少一种。

84. 发明授权

US06881976B1 Heterojunction BiCMOS semiconductor 失效
标题翻译：异质结BiCMOS半导体
公开(公告)号：US06881976B1
公开(公告)日：2005-04-19
申请号：US10705163
申请日：2003-11-06
申请人： Jia Zhen Zheng , Lap Chan , Shao-fu Sanford Chu
发明人： Jia Zhen Zheng , Lap Chan , Shao-fu Sanford Chu
IPC分类号： H01L21/331 , H01L21/8249 , H01L27/06 , H01L27/108 , H01L29/04 , H01L29/76 , H01L31/036 , H01L31/112
CPC分类号： H01L29/66242 , H01L21/8249 , H01L27/0623
摘要： A BiCMOS semiconductor, and manufacturing method therefore, is provided. A semiconductor substrate having a collector region is provided. A pseudo-gate is formed over the collector region. An emitter window is formed in the pseudo-gate to form an extrinsic base structure. An undercut region beneath a portion of the pseudo-gate is formed to provide an intrinsic base structure in the undercut region. An emitter structure is formed in the emitter window over the intrinsic base structure. An interlevel dielectric layer is formed over the semiconductor substrate, and connections are formed through the interlevel dielectric layer to the collector region, the extrinsic base structure, and the emitter structure. The intrinsic base structure comprises a compound semiconductive material such as silicon and silicon-germanium, or silicon-germanium-carbon, or combinations thereof.
摘要翻译：因此，提供BiCMOS半导体及其制造方法。提供具有集电极区域的半导体衬底。在集电极区域上形成伪栅极。在伪栅极中形成发射器窗口以形成外部基极结构。在伪栅极的一部分下面的底切区域形成为在底切区域中提供内部基极结构。发射极结构在内部基极结构的发射极窗口中形成。在半导体衬底上形成层间电介质层，并且通过层间电介质层到集电极区域，非本征基极结构和发射极结构形成连接。本征基础结构包括诸如硅和硅 - 锗的复合半导体材料或硅 - 锗 - 碳或其组合。

85. 发明申请

US20050079658A1 Heterojunction bipolar transistor with self-aligned emitter and sidewall base contact 有权
公开(公告)号：US20050079658A1
公开(公告)日：2005-04-14
申请号：US10683142
申请日：2003-10-09
申请人： Jian Li , Lap Chan , Purakh Verma , Jia Zheng , Shao-Fu Chu
发明人： Jian Li , Lap Chan , Purakh Verma , Jia Zheng , Shao-Fu Chu
IPC分类号： H01L21/331 , H01L29/08 , H01L29/737 , H01L21/8222
CPC分类号： H01L29/66242 , H01L29/0817 , H01L29/7378
摘要： A heterojunction bipolar transistor (HBT), and manufacturing method therfor, comprising a semiconductor substrate having a collector region is provided. A base contact layer is formed over the collector region, and a base trench is formed in the base contact layer and the collector region. An intrinsic base structure having a sidewall portion and a bottom portion is formed in the base trench. An insulating spacer is formed over the sidewall portion of the intrinsic base structure, and an emitter structure is formed over the insulating spacer and the bottom portion of the intrinsic base structure. An interlevel dielectric layer is formed over the base contact layer and the emitter structure. Connections are formed through the interlevel dielectric layer to the collector region, the base contact layer, and the emitter structure. The intrinsic base structure is silicon and at least one of silicon-germanium, silicon-germanium-carbon, and combinations thereof.

86. 发明授权

US06777329B2 Method to form C54 TiSi2 for IC device fabrication 失效
标题翻译：用于IC器件制造的形成C54 TiSi2的方法
公开(公告)号：US06777329B2
公开(公告)日：2004-08-17
申请号：US09838513
申请日：2001-04-20
申请人： Shaoyin Chen , Ze Xiang Shen , Alex See , Lap Chan
发明人： Shaoyin Chen , Ze Xiang Shen , Alex See , Lap Chan
IPC分类号： H01L2144
CPC分类号： H01L21/28518 , H01L21/268 , H01L21/28052 , H01L29/665
摘要： A novel method for forming a C54 phase titanium disilicide film in the fabrication of an integrated circuit is described. A semiconductor substrate is provided having silicon regions to be silicided. A titanium layer is deposited overlying the silicon regions to be silicided. The substrate is subjected to a first annealing whereby the titanium is transformed to phase C40 titanium disilicide where it overlies the silicon regions and wherein the titanium not overlying the silicon regions is unreacted. The unreacted titanium layer is removed. The substrate is subjected to a second annealing whereby the phase C40 titanium disilicide is transformed to phase C54 titanium disilicide to complete formation of a phase 54 titanium disilicide film in the manufacture of an integrated circuit.
摘要翻译：描述了在制造集成电路中形成C54相二硅化钛膜的新颖方法。提供具有要被硅化的硅区域的半导体衬底。沉积钛层以硅化硅层。对基板进行第一退火，由此将钛转化为相C40二硅化钛，其中它覆盖在硅区域上，并且其中不覆盖硅区域的钛是未反应的。去除未反应的钛层。对基板进行第二次退火，由此在制造集成电路中相C40二硅化钛转变为C54二硅化钛以完成形成54相的二硅化钛膜。

87. 发明授权

US06716693B1 Method of forming a surface coating layer within an opening within a body by atomic layer deposition 有权
标题翻译：通过原子层沉积在体内的开口内形成表面涂层的方法
公开(公告)号：US06716693B1
公开(公告)日：2004-04-06
申请号：US10400511
申请日：2003-03-27
申请人： Lap Chan , Sanford Chu , Chit Hwei Ng , Yelehanka Ramachandramurthy Pradeep , Jia Zhen Zheng
发明人： Lap Chan , Sanford Chu , Chit Hwei Ng , Yelehanka Ramachandramurthy Pradeep , Jia Zhen Zheng
IPC分类号： H01L218234
CPC分类号： H01L28/10 , H01F17/0033 , H01F41/042 , H01L21/76838 , H01L23/522 , H01L23/5227 , H01L23/53238 , H01L27/08 , H01L2924/0002 , H01L2924/00
摘要： An improved new process for fabricating multilevel interconnected vertical channels and horizontal channels or tunnels. The method has broad applications in semiconductors, for copper interconnects and inductors, as well as, in the field of bio-sensors for mini- or micro-columns in gas or liquid separation, gas/liquid chromatography, and in capillary separation techniques. In addition, special techniques are described to deposit by atomic layer deposition, ALD, a copper barrier layer and seed layer for electroless copper plating, filling trench and channel or tunnel openings in a type of damascene process, to form copper interconnects and inductors.
摘要翻译：一种用于制造多层互连垂直通道和水平通道或隧道的改进的新工艺。该方法在半导体，铜互连和电感器以及在气体或液体分离中的微型或微型柱的生物传感器领域，气/液相色谱和毛细管分离技术领域具有广泛的应用。此外，描述了通过原子层沉积，ALD，铜阻挡层和用于化学镀铜的种子层，一种镶嵌工艺中的填充沟槽和沟道或隧道开口来沉积特殊技术以形成铜互连和电感器。

88. 发明授权

US06709934B2 Method for forming variable-K gate dielectric 失效
标题翻译：用于形成可变K栅极电介质的方法
公开(公告)号：US06709934B2
公开(公告)日：2004-03-23
申请号：US10196111
申请日：2002-07-16
申请人： James Yong Meng Lee , Ying Keung Leung , Yelehanka Ramachandramurthy Pradeep , Jia Zhen Zheng , Lap Chan , Elgin Quek , Ravi Sundaresan , Yang Pan
发明人： James Yong Meng Lee , Ying Keung Leung , Yelehanka Ramachandramurthy Pradeep , Jia Zhen Zheng , Lap Chan , Elgin Quek , Ravi Sundaresan , Yang Pan
IPC分类号： H01L21336
CPC分类号： H01L21/28194 , H01L29/42376 , H01L29/512 , H01L29/517 , H01L29/518 , H01L29/66583
摘要： A method for forming a gate dielectric having regions with different dielectric constants. A low-K dielectric layer is formed over a semiconductor structure. A dummy dielectric layer is formed over the low-K dielectric layer. The dummy dielectric layer and low-K dielectric layer are patterned to form an opening. The dummy dielectric layer is isontropically etched selectively to the low-K dielectric layer to form a stepped gate opening. A high-K dielectric layer is formed over the dummy dielectric and in the stepped gate opening. A gate electrode is formed on the high-K dielectric layer.
摘要翻译：一种形成具有不同介电常数区域的栅极电介质的方法。在半导体结构上形成低K电介质层。在低K电介质层上形成虚拟电介质层。图案化虚拟介电层和低K电介质层以形成开口。虚拟电介质层被选择性地蚀刻到低K电介质层以形成阶梯式栅极开口。在虚拟电介质和阶梯式门开口中形成高K电介质层。在高K电介质层上形成栅电极。

89. 发明授权

US06696761B2 Method to encapsulate copper plug for interconnect metallization 有权
标题翻译：封装用于互连金属化的铜插头的方法
公开(公告)号：US06696761B2
公开(公告)日：2004-02-24
申请号：US09785108
申请日：2001-02-20
申请人： Lap Chan , Sam Fong Yau Li , Hou Tee Ng
发明人： Lap Chan , Sam Fong Yau Li , Hou Tee Ng
IPC分类号： H01L2348
CPC分类号： H01L21/76849 , H01L21/7684 , H01L21/76879 , H01L23/485 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： An encapsulated copper plug on a doped silicon semiconductor substrate has a substrate surface, covered with insulation, with a plug hole with a diffusion barrier formed on the walls and the bottom of the hole to the top of the hole. The plug hole is partially filled with an electrolessly deposited copper metal plug. An encapsulating metal deposit caps the plug without any intervening oxidation and degradation. In a transition from copper to a codeposit of copper, an encapsulating Pt, Pd, and/or Ag metal deposits in the electroless bath without oxidation and degradation followed by a pure deposit of the encapsulating metal layer to cap the plug. The surface of the encapsulating metal deposit is formed by overgrowth above the plug hole followed by polishing the surface of the insulator layer removing the overgrowth of the metal layer polished by a CMP process to planarize the surface of the insulator layer which is the top surface of device to achieve coplanarity of metal layer with the topography of the insulator layer.
摘要翻译：掺杂硅半导体衬底上的封装铜插头具有覆盖有绝缘体的衬底表面，其上形成有扩散阻挡层的插塞孔，孔形成在孔的顶部和顶部。塞孔部分地填充有无电沉积的铜金属塞。封装金属沉积物对插头进行覆盖，而不会发生任何中间氧化和降解。在从铜到铜的共沉积物的转变中，封装的Pt，Pd和/或Ag金属在无电镀浴中沉积而不氧化和降解，然后纯化沉积包封金属层以堵住塞子。封装金属沉积物的表面通过在插塞孔上方过度生长而形成，随后抛光绝缘体层的表面，从而去除通过CMP工艺抛光的金属层的过度生长，以使作为顶部表面的绝缘体层的表面平坦化器件实现金属层与绝缘体层的形貌的共面性。

90. 发明授权

US06656792B2 Nanocrystal flash memory device and manufacturing method therefor 有权
标题翻译：纳米晶体闪存器件及其制造方法
公开(公告)号：US06656792B2
公开(公告)日：2003-12-02
申请号：US10087506
申请日：2002-03-01
申请人： Wee Kiong Choi , Wai Kin Chim , Vivian Ng , Lap Chan
发明人： Wee Kiong Choi , Wai Kin Chim , Vivian Ng , Lap Chan
IPC分类号： H01L21336
CPC分类号： B82Y10/00 , H01L21/28273 , H01L29/42332
摘要： A Flash memory is provided having a trilayer structure of rapid thermal oxide/germanium (Ge) nanocrystals in silicon dioxide (SiO2)/sputtered SiO2 cap with demonstrated via capacitance versus voltage (C-V) measurements having memory hysteresis due to Ge nanocrystals in the middle layer of the trilayer structure. The Ge nanocrystals are synthesized by rapid thermal annealing of a co-sputtered Ge+SiO2 layer.
摘要翻译：提供了一种闪存，其具有在二氧化硅（SiO 2）/溅射的SiO 2盖中具有快速热氧化物/锗（Ge）纳米晶体的三层结构，其经证实的经由电容对电压（CV）测量具有由于中间层中的Ge纳米晶体而具有记忆滞后的三层结构。 Ge纳米晶体通过共溅射的Ge + SiO 2层的快速热退火合成。

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