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71. 发明授权

US08796660B2 Nonvolatile memory element comprising a resistance variable element and a diode 有权
标题翻译：非易失性存储元件包括电阻可变元件和二极管
公开(公告)号：US08796660B2
公开(公告)日：2014-08-05
申请号：US12375881
申请日：2007-09-21
申请人： Takeshi Takagi , Takumi Mikawa
发明人： Takeshi Takagi , Takumi Mikawa
IPC分类号： H01L29/02 , H01L47/00 , H01L29/04 , H01L29/06 , H01L29/08 , H01L31/0352 , H01L45/00 , H01L27/24 , H01L27/10 , H01L21/00 , G11C11/00
CPC分类号： H01L45/04 , H01L27/101 , H01L27/2409 , H01L27/2418 , H01L27/2463 , H01L45/1233 , H01L45/1273 , H01L45/146 , H01L45/1683
摘要： A nonvolatile memory element (20) of the present invention comprises a resistance variable element (14) and a diode (18) which are formed on a substrate (10) such that the resistance variable element (14) has a resistance variable layer (11) sandwiched between a lower electrode (12) and an upper electrode (13), and the diode (18) which is connected in series with the resistance variable element (14) in the laminating direction and has an insulating layer or semiconductor layer (15) sandwiched between a first electrode (16) at the lower side and a second electrode (17) at the upper side. The resistance variable layer (11) is embedded in a first contact hole (21) formed on the lower electrode (12). A first area (22) where insulating layer or semiconductor layer (15) of the diode (18) is in contact with a first electrode (16) of the diode (18) is larger than at least one of a second area (23) where the resistance variable layer (11) is in contact with the upper electrode (13) and a third area (24) where the resistance variable layer (11) is in contact with the lower electrode (12).
摘要翻译：本发明的非易失性存储元件（20）包括形成在基板（10）上的电阻可变元件（14）和二极管（18），使得电阻可变元件（14）具有电阻变化层（11 ）和位于下电极（12）和上电极（13）之间的二极管（18），以及与电阻可变元件（14）在层叠方向上串联连接并具有绝缘层或半导体层（15）的二极管）夹在下侧的第一电极（16）和上侧的第二电极（17）之间。电阻变化层（11）嵌入形成在下电极（12）上的第一接触孔（21）中。二极管（18）的绝缘层或半导体层（15）与二极管（18）的第一电极（16）接触的第一区域（22）大于第二区域（23）中的至少一个，其中电阻变化层（11）与上电极（13）接触，电阻变化层（11）与下电极（12）接触的第三区域（24）。

72. 发明申请

US20130270510A1 NONVOLATILE SEMICONDUCTOR MEMORY ELEMENT, NONVOLATILE SEMICONDUCTOR MEMORY DEVICE, AND METHOD FOR MANUFACTURING NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：非易失性半导体存储器元件，非易失性半导体存储器件及其制造非易失性半导体存储器件的方法
公开(公告)号：US20130270510A1
公开(公告)日：2013-10-17
申请号：US13996203
申请日：2012-06-18
申请人： Satoru Fujii , Kiyotaka Tsuji , Takumi Mikawa
发明人： Satoru Fujii , Kiyotaka Tsuji , Takumi Mikawa
IPC分类号： H01L27/24 , H01L45/00
CPC分类号： H01L27/2409 , H01L27/228 , H01L27/2436 , H01L27/2463 , H01L29/66143 , H01L29/872 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/145 , H01L45/146 , H01L45/16 , H01L45/1608 , H01L45/1616 , H01L45/1625 , H01L45/1675
摘要： A nonvolatile semiconductor memory element includes: a variable resistance element including a first electrode, a variable resistance layer, and a second electrode, and having a resistance value which changes according to a polarity of an electric pulse applied between the first electrode and the second electrode; and a current steering element which is electrically connected to the variable resistance element, allows a current to flow bidirectionally, and has a nonlinear current-voltage characteristic. The current steering element (i) has a structure in which a first current steering element electrode, a first semiconductor layer, and a second current steering element electrode are stacked in this order, and (ii) includes a second semiconductor layer which covers side surfaces of the first current steering element electrode, the first semiconductor layer, and the second current steering element electrode.
摘要翻译：非易失性半导体存储元件包括：可变电阻元件，包括第一电极，可变电阻层和第二电极，并且具有根据施加在第一电极和第二电极之间的电脉冲的极性而变化的电阻值 ; 并且电连接到可变电阻元件的电流导向元件允许电流双向流动，并且具有非线性电流 - 电压特性。当前的操舵元件（i）具有第一电流操舵元件电极，第一半导体层和第二电流操舵元件电极依次层叠的结构，（ⅱ）包括覆盖侧面的第二半导体层的第一电流操舵元件电极，第一半导体层和第二电流操舵元件电极。

73. 发明申请

US20130121063A1 MEMORY DEVICE, SEMICONDUCTOR STORAGE DEVICE, METHOD FOR MANUFACTURING MEMORY DEVICE, AND READING METHOD FOR SEMICONDUCTOR STORAGE DEVICE 有权
标题翻译：存储器件，半导体存储器件，用于制造存储器件的方法和用于半导体存储器件的读取方法
公开(公告)号：US20130121063A1
公开(公告)日：2013-05-16
申请号：US13812532
申请日：2011-09-26
申请人： Kiyotaka Tsuji , Takumi Mikawa
发明人： Kiyotaka Tsuji , Takumi Mikawa
IPC分类号： H01L45/00 , G11C13/00
CPC分类号： H01L45/1253 , G11C13/0007 , G11C13/003 , G11C13/004 , G11C13/0069 , G11C2013/0073 , G11C2213/72 , G11C2213/78 , H01L27/101 , H01L27/2409 , H01L27/2472 , H01L45/08 , H01L45/1233 , H01L45/146 , H01L45/16 , H01L45/1625 , H01L45/1675 , H01L45/1683
摘要： A memory device that can prevent degradation in characteristics of a diode and the destruction due to the miniaturization includes: a substrate; first electrodes, a second electrode, and a third electrode that are stacked above the substrate; a variable resistance layer between the first and second electrodes; and a non-conductive layer between the second and third electrodes. The variable resistance layer includes a high-concentration variable resistance layer closer to the first electrodes, and a low-concentration variable resistance layer closer to the second electrode and having an oxygen concentration lower than that of the high-concentration variable resistance layer. The second and third electrodes and the non-conductive layer comprise the diode, and the first and second electrodes and the variable resistance layer comprise variable resistance elements, a total number of which is equal to that of the first electrodes.
摘要翻译：可以防止二极管的特性劣化和由于小型化引起的破坏的存储器件包括：衬底; 在基板上层叠的第一电极，第二电极和第三电极; 第一和第二电极之间的可变电阻层; 以及在第二和第三电极之间的非导电层。可变电阻层包括靠近第一电极的高浓度可变电阻层和更靠近第二电极并且氧浓度低于高浓度可变电阻层的低浓度可变电阻层的低浓度可变电阻层。第二和第三电极和非导电层包括二极管，并且第一和第二电极和可变电阻层包括可变电阻元件，其总数等于第一电极的总数。

74. 发明授权

US08258493B2 Nonvolatile semiconductor memory apparatus and manufacturing method thereof 有权
标题翻译：非易失性半导体存储装置及其制造方法
公开(公告)号：US08258493B2
公开(公告)日：2012-09-04
申请号：US12515379
申请日：2007-11-13
申请人： Takumi Mikawa , Takeshi Takagi
发明人： Takumi Mikawa , Takeshi Takagi
IPC分类号： H01L29/00
CPC分类号： H01L27/101 , G11C13/0007 , G11C2213/32 , G11C2213/72 , G11C2213/73 , H01L27/0688 , H01L27/112 , H01L27/115 , H01L27/2409 , H01L27/2418 , H01L27/2463 , H01L27/2481 , H01L45/04 , H01L45/1233 , H01L45/146 , H01L45/1683
摘要： A nonvolatile semiconductor memory apparatus (10) of the present invention comprises a substrate (10), lower-layer electrode wires (15) provided on the substrate (11), an interlayer insulating layer (16) which is disposed on the substrate (11) including the lower-layer electrode wires (15) and is provided with contact holes at locations respectively opposite to the lower-layer electrode wires (15), resistance variable layers (18) which are respectively connected to the lower-layer electrode wires (15); and non-ohmic devices (20) which are respectively provided on the resistance variable layers (18) such that the non-ohmic devices are respectively connected to the resistance variable layers (18). The non-ohmic devices (20) each has a laminated-layer structure including plural semiconductor layers, a laminated-layer structure including a metal electrode layer and an insulator layer, or a laminated-layer structure including a metal electrode layer and a semiconductor layer. One layer of the laminated-layer structure is embedded to fill each of the contact holes and the semiconductor layer or the insulator layer which is the other layer of the laminated-layer structure has a larger area than an opening of each of the contact holes and is provided on the interlayer insulating layer (16).
摘要翻译：本发明的非易失性半导体存储装置（10）具备基板（10），设置在基板（11）上的下层电极布线（15），设置在基板（11）上的层间绝缘层（16）），并且在分别与下层电极线（15）相对的位置设置接触孔，电阻变化层（18）分别与下层电极线（15）连接 15）; 和非欧姆器件（20），其分别设置在电阻变化层（18）上，使得非欧姆器件分别连接到电阻变化层（18）。非欧姆装置（20）各自具有包括多个半导体层的层叠层结构，包括金属电极层和绝缘体层的层叠层结构，或者包括金属电极层和半导体层的层叠层结构。嵌入层叠层结构的一层以填充每个接触孔，作为层叠层结构的另一层的半导体层或绝缘体层的面积比每个接触孔的开口大，设置在层间绝缘层（16）上。

75. 发明申请

US20120104350A1 VARIABLE RESISTANCE NONVOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：可变电阻非易失性存储器件及其制造方法
公开(公告)号：US20120104350A1
公开(公告)日：2012-05-03
申请号：US13379460
申请日：2011-04-26
申请人： Atsushi Himeno , Haruyuki Sorada , Takumi Mikawa
发明人： Atsushi Himeno , Haruyuki Sorada , Takumi Mikawa
IPC分类号： H01L27/26 , H01L47/00
CPC分类号： H01L27/2463 , H01L27/2409 , H01L27/2481 , H01L45/08 , H01L45/1233 , H01L45/1266 , H01L45/146 , H01L45/1633
摘要： A step of forming, on a substrate (11), lower layer copper lines (18) each being shaped into a strip, a step of forming electrode seed layers (21) each being shaped into a strip, on the surfaces of the respective lower layer copper lines (18) using electroless plating, a step of forming interlayer insulating layer (19) above the electrode seed layers (21) and the substrate (11), a step of forming, in the interlayer insulating layer (19), memory cell holes (20), penetrating through the interlayer insulating layer (19) and extending to the electrode seed layers (21), a step of forming noble metal electrode layers (29) on the surfaces of the electrode seed layers (21) exposed in the respective memory cell holes (20) using the electroless plating, a step of forming, in the respective memory cell holes (20), variable resistance layers (23) connected to the noble electrode layers (29), and a step of forming, above the interlayer insulating layer (19) and the variable resistance layers (23), upper layer copper lines (24) each being shaped into a strip, connected to a corresponding one of the variable resistance layers (23), and crossing the lower layer copper lines (18), are included.
摘要翻译：在基板（11）上形成各自被成形为条带的下层铜线（18）的步骤，在各自的下表面上形成各自成形为条带的电极种子层（21）的步骤使用无电镀的层间铜线（18），在电极种子层（21）和基板（11）的上方形成层间绝缘层（19）的工序，在层间绝缘层（19）穿过层间绝缘层（19）并延伸到电极种子层（21）的电池孔（20），在暴露于电极种子层（21）的表面上形成贵金属电极层（29）的步骤使用无电镀的各个存储单元孔（20），在各个存储单元孔（20），连接到贵金属电极层（29）的可变电阻层（23）上形成步骤，在层间绝缘层（19）和可变电阻层（23）之上，上层铜线（24）各自被成形为条，连接到相应的一个可变电阻层（23）并与下层铜线（18）交叉。

76. 发明授权

US08093578B2 Nonvolatile memory element, nonvolatile memory element array, and method for manufacturing nonvolatile memory element 有权
标题翻译：非易失性存储元件，非易失性存储元件阵列和用于制造非易失性存储元件的方法
公开(公告)号：US08093578B2
公开(公告)日：2012-01-10
申请号：US12513638
申请日：2007-11-16
申请人： Takeshi Takagi , Takumi Mikawa
发明人： Takeshi Takagi , Takumi Mikawa
IPC分类号： H01L27/10 , H01L21/02
CPC分类号： H01L27/101 , H01L27/1021 , H01L27/2409 , H01L27/2418 , H01L27/2463 , H01L45/04 , H01L45/1233 , H01L45/146 , H01L45/1683
摘要： The present invention is configured such that a resistance variable element (16) and a rectifying element (20) are formed on a substrate (12). The resistance variable element (16) is configured such that a resistance variable layer (14) made of a metal oxide material is sandwiched between a lower electrode (13) and an upper electrode (15). The rectifying element (20) is connected to the resistance variable element (16), and is configured such that a blocking layer (18) is sandwiched between a first electrode layer (17) located on a lower side of the blocking layer (18) and a second electrode layer (19) located on an upper side of the blocking layer (18). The resistance variable element (16) and the rectifying element (20) are connected to each other in series in a thickness direction of the resistance variable layer (14), and the blocking layer (18) is formed as a barrier layer having a hydrogen barrier property.
摘要翻译：本发明被构造成使得在基板（12）上形成电阻可变元件（16）和整流元件（20）。电阻可变元件（16）被构造为使得由金属氧化物材料制成的电阻变化层（14）夹在下电极（13）和上电极（15）之间。整流元件（20）连接到电阻可变元件（16），并且被构造为使阻挡层（18）夹在位于阻挡层（18）的下侧的第一电极层（17）之间，以及位于阻挡层（18）的上侧的第二电极层（19）。电阻可变元件（16）和整流元件（20）在电阻变化层（14）的厚度方向上串联连接，并且阻挡层（18）形成为具有氢的阻挡层屏障属性。

77. 发明授权

US07557011B2 Semiconductor device and method for fabricating the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US07557011B2
公开(公告)日：2009-07-07
申请号：US11280250
申请日：2005-11-17
申请人： Takumi Mikawa , Yuji Judai , Toshie Kutsunai
发明人： Takumi Mikawa , Yuji Judai , Toshie Kutsunai
IPC分类号： H01L21/108 , H01L21/316 , H01L21/318
CPC分类号： H01L28/65 , H01L27/11507 , H01L28/57 , H01L28/75
摘要： A semiconductor device includes a first hydrogen barrier film, a capacitor device formed on the first hydrogen barrier film, and a second hydrogen barrier film formed to cover the capacitor device. The first and second hydrogen barrier films each contain at least one common type of atoms for allowing the first and second hydrogen barrier films to adhere to each other.
摘要翻译：半导体器件包括第一氢阻挡膜，形成在第一氢阻挡膜上的电容器器件和形成为覆盖电容器器件的第二氢阻挡膜。第一和第二氢阻挡膜每个含有至少一种常见类型的原子，用于允许第一和第二氢阻挡膜彼此粘附。

78. 发明授权

US07413949B2 Capacitor and method for fabricating the same 失效
标题翻译：电容器及其制造方法
公开(公告)号：US07413949B2
公开(公告)日：2008-08-19
申请号：US11117328
申请日：2005-04-29
申请人： Takumi Mikawa , Yuji Judai , Shinichiro Hayashi
发明人： Takumi Mikawa , Yuji Judai , Shinichiro Hayashi
IPC分类号： H01L21/8242
CPC分类号： H01L28/55 , H01L28/60 , Y10T29/43
摘要： A capacitor is formed on an interlayer insulating film formed on a semiconductor substrate. The capacitor includes a bottom electrode made of platinum, a capacitor insulating film made of SrTaBiO (SBT) containing an element absorbing hydrogen such as titanium, for example, in grain boundaries, inter-lattice positions or holes, and a top electrode made of platinum.
摘要翻译：在形成在半导体衬底上的层间绝缘膜上形成电容器。电容器包括由铂制成的底部电极，由SrTaBiO（SBT）制成的电容器绝缘膜，其包含例如在晶界，晶格间位置或空穴中吸收钛的钛的元素，以及由铂制成的顶部电极。

79. 发明申请

US20060292816A1 Semiconductor device and method for fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20060292816A1
公开(公告)日：2006-12-28
申请号：US11415069
申请日：2006-05-02
申请人： Takumi Mikawa , Toru Nasu
发明人： Takumi Mikawa , Toru Nasu
IPC分类号： H01L21/20 , H01L29/00
CPC分类号： H01L28/55 , H01L27/11502 , H01L27/11507 , H01L28/65 , H01L28/91
摘要： A semiconductor device comprises: an insulating film formed over a semiconductor substrate and having a first recess; a plurality of capacitor elements each of which is composed of a capacitor lower electrode formed on wall and bottom portions of the first recess and having a second recess, a capacitor insulating film of a dielectric film formed on wall and bottom portions of the second recess and having a third recess, and a capacitor upper electrode formed on wall and bottom portions of the third recess; and a conductive layer (referred hereinafter to as a low-resistance conductive layer) which is formed to cover at least portions of the respective capacitor upper electrodes constituting the plurality of capacitor elements and to extend across the plurality of capacitor elements and which has a lower resistance than the capacitor upper electrode.
摘要翻译：半导体器件包括：形成在半导体衬底上并具有第一凹槽的绝缘膜; 多个电容器元件，每个电容器元件由形成在第一凹部的壁和底部上的电容器下电极组成，并具有第二凹部，形成在第二凹部的壁和底部上的电介质膜的电容绝缘膜，具有第三凹部和形成在第三凹部的壁部和底部上的电容器上电极; 以及形成为覆盖构成多个电容器元件的各个电容器上电极的至少一部分并且跨越多个电容器元件并且具有较低电容器元件的导电层（以下称为低电阻导电层）电阻比电容器上电极。

80. 发明授权

US07115937B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07115937B2
公开(公告)日：2006-10-03
申请号：US11270156
申请日：2005-11-09
申请人： Takumi Mikawa , Yuuji Jyuudai , Shinya Natsume
发明人： Takumi Mikawa , Yuuji Jyuudai , Shinya Natsume
IPC分类号： H01L27/108
CPC分类号： H01L28/60 , H01L21/31053 , H01L27/11502 , H01L27/11507
摘要： A method for manufacturing a semiconductor device includes the steps of forming a conductive layer over a first insulating layer formed on a substrate, and over a plurality of contact plugs formed in the first insulating layer; forming a plurality of capacitor element lower electrodes by patterning the conductive layer; forming a second insulating layer on the first insulating layer and the capacitor element lower electrodes; forming recesses in the second insulating layer at a region above the capacitor element lower electrodes; planarizing the second insulating layer by polishing; exposing the capacitor element lower electrodes; and forming a capacitive insulating film and capacitor element upper electrodes above the capacitor element lower electrodes. In polishing the second insulating layer, leveling of steps can be accelerated, insufficient polishing, peeling of the lower electrodes and generation of scratches can be suppressed, and the global step difference can be reduced.
摘要翻译：一种制造半导体器件的方法包括以下步骤：在形成于基板上的第一绝缘层上形成导电层，以及形成在第一绝缘层中的多个接触插塞; 通过图案化导电层形成多个电容器元件下电极; 在所述第一绝缘层和所述电容器元件下电极上形成第二绝缘层; 在所述电容器元件下电极上方的区域中在所述第二绝缘层中形成凹部; 通过抛光来平坦化第二绝缘层; 暴露电容元件下电极; 以及在电容器元件下电极之上形成电容绝缘膜和电容元件上电极。在第二绝缘层的研磨中，可以加速台阶的调平，不足的研磨，下部电极的剥离和划痕的产生也可以抑制，从而可以降低全局的步进差。

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