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1. 发明授权

US07115937B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07115937B2
公开(公告)日：2006-10-03
申请号：US11270156
申请日：2005-11-09
申请人： Takumi Mikawa , Yuuji Jyuudai , Shinya Natsume
发明人： Takumi Mikawa , Yuuji Jyuudai , Shinya Natsume
IPC分类号： H01L27/108
CPC分类号： H01L28/60 , H01L21/31053 , H01L27/11502 , H01L27/11507
摘要： A method for manufacturing a semiconductor device includes the steps of forming a conductive layer over a first insulating layer formed on a substrate, and over a plurality of contact plugs formed in the first insulating layer; forming a plurality of capacitor element lower electrodes by patterning the conductive layer; forming a second insulating layer on the first insulating layer and the capacitor element lower electrodes; forming recesses in the second insulating layer at a region above the capacitor element lower electrodes; planarizing the second insulating layer by polishing; exposing the capacitor element lower electrodes; and forming a capacitive insulating film and capacitor element upper electrodes above the capacitor element lower electrodes. In polishing the second insulating layer, leveling of steps can be accelerated, insufficient polishing, peeling of the lower electrodes and generation of scratches can be suppressed, and the global step difference can be reduced.
摘要翻译：一种制造半导体器件的方法包括以下步骤：在形成于基板上的第一绝缘层上形成导电层，以及形成在第一绝缘层中的多个接触插塞; 通过图案化导电层形成多个电容器元件下电极; 在所述第一绝缘层和所述电容器元件下电极上形成第二绝缘层; 在所述电容器元件下电极上方的区域中在所述第二绝缘层中形成凹部; 通过抛光来平坦化第二绝缘层; 暴露电容元件下电极; 以及在电容器元件下电极之上形成电容绝缘膜和电容元件上电极。在第二绝缘层的研磨中，可以加速台阶的调平，不足的研磨，下部电极的剥离和划痕的产生也可以抑制，从而可以降低全局的步进差。

2. 发明申请

US20060060908A1 Semiconductor device and method for manufacturing the same 有权
公开(公告)号：US20060060908A1
公开(公告)日：2006-03-23
申请号：US11270156
申请日：2005-11-09
申请人： Takumi Mikawa , Yuuji Jyuudai , Shinya Natsume
发明人： Takumi Mikawa , Yuuji Jyuudai , Shinya Natsume
IPC分类号： H01L27/108
CPC分类号： H01L28/60 , H01L21/31053 , H01L27/11502 , H01L27/11507
摘要： A method for manufacturing a semiconductor device includes the steps of forming a conductive layer over a first insulating layer formed on a substrate, and over a plurality of contact plugs formed in the first insulating layer; forming a plurality of capacitor element lower electrodes by patterning the conductive layer; forming a second insulating layer on the first insulating layer and the capacitor element lower electrodes; forming recesses in the second insulating layer at a region above the capacitor element lower electrodes; planarizing the second insulating layer by polishing; exposing the capacitor element lower electrodes; and forming a capacitive insulating film and capacitor element upper electrodes above the capacitor element lower electrodes. In polishing the second insulating layer, leveling of steps can be accelerated, insufficient polishing, peeling of the lower electrodes and generation of scratches can be suppressed, and the global step difference can be reduced.

3. 发明授权

US07008840B2 Method for manufacturing semiconductor device with capacitor elements 失效
标题翻译：具有电容器元件的半导体器件的制造方法
公开(公告)号：US07008840B2
公开(公告)日：2006-03-07
申请号：US10642955
申请日：2003-08-18
申请人： Takumi Mikawa , Yuuji Jyuudai , Shinya Natsume
发明人： Takumi Mikawa , Yuuji Jyuudai , Shinya Natsume
IPC分类号： H01L21/8242
CPC分类号： H01L28/60 , H01L21/31053 , H01L27/11502 , H01L27/11507
摘要： A method for manufacturing a semiconductor device includes the steps of forming a conductive layer over a first insulating layer formed on a substrate, and over a plurality of contact plugs formed in the first insulating layer; forming a plurality of capacitor element lower electrodes by patterning the conductive layer; forming a second insulating layer on the first insulating layer and the capacitor element lower electrodes; forming recesses in the second insulating layer at a region above the capacitor element lower electrodes; planarizing the second insulating layer by polishing; exposing the capacitor element lower electrodes; and forming a capacitive insulating film and capacitor element upper electrodes above the capacitor element lower electrodes. In polishing the second insulating layer, leveling of steps can be accelerated, insufficient polishing, peeling of the lower electrodes and generation of scratches can be suppressed, and the global step difference can be reduced.
摘要翻译：一种制造半导体器件的方法包括以下步骤：在形成于基板上的第一绝缘层上形成导电层，以及形成在第一绝缘层中的多个接触插塞; 通过图案化导电层形成多个电容器元件下电极; 在所述第一绝缘层和所述电容器元件下电极上形成第二绝缘层; 在所述电容器元件下电极上方的区域中在所述第二绝缘层中形成凹部; 通过抛光来平坦化第二绝缘层; 暴露电容元件下电极; 以及在电容器元件下电极之上形成电容绝缘膜和电容元件上电极。在第二绝缘层的研磨中，可以加速台阶的调平，不足的研磨，下部电极的剥离和划痕的产生也可以抑制，从而可以降低全局的步进差。

4. 发明授权

US09252189B2 Nonvolatile semiconductor memory element, nonvolatile semiconductor memory device, and method for manufacturing nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储元件，非易失性半导体存储器件以及用于制造非易失性半导体存储器件的方法
公开(公告)号：US09252189B2
公开(公告)日：2016-02-02
申请号：US13996203
申请日：2012-06-18
申请人： Satoru Fujii , Kiyotaka Tsuji , Takumi Mikawa
发明人： Satoru Fujii , Kiyotaka Tsuji , Takumi Mikawa
IPC分类号： H01L27/24 , H01L45/00 , H01L29/66 , H01L29/872 , H01L27/22
CPC分类号： H01L27/2409 , H01L27/228 , H01L27/2436 , H01L27/2463 , H01L29/66143 , H01L29/872 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/145 , H01L45/146 , H01L45/16 , H01L45/1608 , H01L45/1616 , H01L45/1625 , H01L45/1675
摘要： A nonvolatile semiconductor memory element includes: a variable resistance element including a first electrode, a variable resistance layer, and a second electrode, and having a resistance value which changes according to a polarity of an electric pulse applied between the first electrode and the second electrode; and a current steering element which is electrically connected to the variable resistance element, allows a current to flow bidirectionally, and has a nonlinear current-voltage characteristic. The current steering element (i) has a structure in which a first current steering element electrode, a first current steering layer, and a second current steering element electrode are stacked in this order, and (ii) includes a second current steering layer which covers side surfaces of the first current steering element electrode, the first current steering layer, and the second current steering element electrode.
摘要翻译：非易失性半导体存储元件包括：可变电阻元件，包括第一电极，可变电阻层和第二电极，并且具有根据施加在第一电极和第二电极之间的电脉冲的极性而变化的电阻值 ; 并且电连接到可变电阻元件的电流导向元件允许电流双向流动，并且具有非线性电流 - 电压特性。当前的操舵元件（i）具有第一电流导向元件电极，第一电流导向层和第二电流操舵元件电极按此顺序堆叠的结构，（ⅱ）包括覆盖第一电流操舵元件电极，第一电流导向层和第二电流导向元件电极的侧面。

5. 发明授权

US09000506B2 Variable resistance nonvolatile memory element and method for manufacturing the same 有权
标题翻译：可变电阻非易失性存储元件及其制造方法
公开(公告)号：US09000506B2
公开(公告)日：2015-04-07
申请号：US13501624
申请日：2011-11-18
申请人： Takeki Ninomiya , Takumi Mikawa , Yukio Hayakawa
发明人： Takeki Ninomiya , Takumi Mikawa , Yukio Hayakawa
IPC分类号： H01L27/108 , H01L45/00 , H01L27/24
CPC分类号： H01L45/146 , H01L27/2463 , H01L27/2481 , H01L45/08 , H01L45/1233 , H01L45/145 , H01L45/1675
摘要： A nonvolatile memory element which inhibits deterioration of an oxygen concentration profile of a variable resistance layer due to a thermal budget and is able to stably operate at low voltages, and a method for manufacturing the nonvolatile memory element are provided. The nonvolatile memory element includes a first electrode layer formed above a substrate, a variable resistance layer disposed on the first electrode layer, and a second electrode layer disposed on the variable resistance layer, and the variable resistance layer has a two-layer structure in which an oxygen- and/or nitrogen-deficient tantalum oxynitride layer and a tantalum oxide layer are stacked.
摘要翻译：提供一种非易失性存储元件，其抑制由于热预算导致的可变电阻层的氧浓度分布的劣化，并能够在低电压下稳定地工作，并且提供了一种制造非易失性存储元件的方法。非易失性存储元件包括形成在基板上的第一电极层，设置在第一电极层上的可变电阻层和设置在可变电阻层上的第二电极层，可变电阻层具有两层结构，其中氧和/或氮缺乏的氮氧化钽层和氧化钽层被堆叠。

6. 发明授权

US08796660B2 Nonvolatile memory element comprising a resistance variable element and a diode 有权
标题翻译：非易失性存储元件包括电阻可变元件和二极管
公开(公告)号：US08796660B2
公开(公告)日：2014-08-05
申请号：US12375881
申请日：2007-09-21
申请人： Takeshi Takagi , Takumi Mikawa
发明人： Takeshi Takagi , Takumi Mikawa
IPC分类号： H01L29/02 , H01L47/00 , H01L29/04 , H01L29/06 , H01L29/08 , H01L31/0352 , H01L45/00 , H01L27/24 , H01L27/10 , H01L21/00 , G11C11/00
CPC分类号： H01L45/04 , H01L27/101 , H01L27/2409 , H01L27/2418 , H01L27/2463 , H01L45/1233 , H01L45/1273 , H01L45/146 , H01L45/1683
摘要： A nonvolatile memory element (20) of the present invention comprises a resistance variable element (14) and a diode (18) which are formed on a substrate (10) such that the resistance variable element (14) has a resistance variable layer (11) sandwiched between a lower electrode (12) and an upper electrode (13), and the diode (18) which is connected in series with the resistance variable element (14) in the laminating direction and has an insulating layer or semiconductor layer (15) sandwiched between a first electrode (16) at the lower side and a second electrode (17) at the upper side. The resistance variable layer (11) is embedded in a first contact hole (21) formed on the lower electrode (12). A first area (22) where insulating layer or semiconductor layer (15) of the diode (18) is in contact with a first electrode (16) of the diode (18) is larger than at least one of a second area (23) where the resistance variable layer (11) is in contact with the upper electrode (13) and a third area (24) where the resistance variable layer (11) is in contact with the lower electrode (12).
摘要翻译：本发明的非易失性存储元件（20）包括形成在基板（10）上的电阻可变元件（14）和二极管（18），使得电阻可变元件（14）具有电阻变化层（11 ）和位于下电极（12）和上电极（13）之间的二极管（18），以及与电阻可变元件（14）在层叠方向上串联连接并具有绝缘层或半导体层（15）的二极管）夹在下侧的第一电极（16）和上侧的第二电极（17）之间。电阻变化层（11）嵌入形成在下电极（12）上的第一接触孔（21）中。二极管（18）的绝缘层或半导体层（15）与二极管（18）的第一电极（16）接触的第一区域（22）大于第二区域（23）中的至少一个，其中电阻变化层（11）与上电极（13）接触，电阻变化层（11）与下电极（12）接触的第三区域（24）。

7. 发明申请

US20140197368A1 NONVOLATILE MEMORY ELEMENT, NONVOLATILE MEMORY DEVICE, NONVOLATILE MEMORY ELEMENT MANUFACTURING METHOD, AND NONVOLATILE MEMORY DEVICE MANUFACTURING METHOD 有权
标题翻译：非易失性存储器元件，非易失性存储器件，非易失性存储元件制造方法和非易失性存储器件制造方法
公开(公告)号：US20140197368A1
公开(公告)日：2014-07-17
申请号：US14343441
申请日：2012-09-10
申请人： Shinichi Yoneda , Takumi Mikawa , Satoru Ito , Yukio Hayakawa , Atsushi Himeno
发明人： Shinichi Yoneda , Takumi Mikawa , Satoru Ito , Yukio Hayakawa , Atsushi Himeno
IPC分类号： H01L45/00
CPC分类号： H01L45/124 , H01L27/2409 , H01L27/2436 , H01L27/2481 , H01L45/08 , H01L45/1233 , H01L45/1246 , H01L45/145 , H01L45/146 , H01L45/1608 , H01L45/1625 , H01L45/1675
摘要： A nonvolatile memory element including: a first electrode; a second electrode; a variable resistance layer that is between the first electrode and the second electrode and includes, as stacked layers, a first variable resistance layer connected to the first electrode and a second variable resistance layer connected to the second electrode; and a side wall protecting layer that has oxygen barrier properties and covers a side surface of the variable resistance layer. The first variable resistance layer includes a first metal oxide and a third metal oxide formed around the first metal oxide and having an oxygen deficiency lower than that of the first metal oxide, and the second variable resistance layer includes a second metal oxide having an oxygen deficiency lower than that of the first metal oxide.
摘要翻译：一种非易失性存储元件，包括：第一电极; 第二电极; 在第一电极和第二电极之间的可变电阻层，并且包括作为堆叠层的连接到第一电极的第一可变电阻层和连接到第二电极的第二可变电阻层; 以及具有阻氧性并覆盖可变电阻层的侧面的侧壁保护层。第一可变电阻层包括形成在第一金属氧化物周围的第一金属氧化物和第三金属氧化物，其氧缺陷低于第一金属氧化物，第二可变电阻层包括具有氧缺乏的第二金属氧化物低于第一金属氧化物。

8. 发明申请

US20130270510A1 NONVOLATILE SEMICONDUCTOR MEMORY ELEMENT, NONVOLATILE SEMICONDUCTOR MEMORY DEVICE, AND METHOD FOR MANUFACTURING NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：非易失性半导体存储器元件，非易失性半导体存储器件及其制造非易失性半导体存储器件的方法
公开(公告)号：US20130270510A1
公开(公告)日：2013-10-17
申请号：US13996203
申请日：2012-06-18
申请人： Satoru Fujii , Kiyotaka Tsuji , Takumi Mikawa
发明人： Satoru Fujii , Kiyotaka Tsuji , Takumi Mikawa
IPC分类号： H01L27/24 , H01L45/00
CPC分类号： H01L27/2409 , H01L27/228 , H01L27/2436 , H01L27/2463 , H01L29/66143 , H01L29/872 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/145 , H01L45/146 , H01L45/16 , H01L45/1608 , H01L45/1616 , H01L45/1625 , H01L45/1675
摘要： A nonvolatile semiconductor memory element includes: a variable resistance element including a first electrode, a variable resistance layer, and a second electrode, and having a resistance value which changes according to a polarity of an electric pulse applied between the first electrode and the second electrode; and a current steering element which is electrically connected to the variable resistance element, allows a current to flow bidirectionally, and has a nonlinear current-voltage characteristic. The current steering element (i) has a structure in which a first current steering element electrode, a first semiconductor layer, and a second current steering element electrode are stacked in this order, and (ii) includes a second semiconductor layer which covers side surfaces of the first current steering element electrode, the first semiconductor layer, and the second current steering element electrode.
摘要翻译：非易失性半导体存储元件包括：可变电阻元件，包括第一电极，可变电阻层和第二电极，并且具有根据施加在第一电极和第二电极之间的电脉冲的极性而变化的电阻值 ; 并且电连接到可变电阻元件的电流导向元件允许电流双向流动，并且具有非线性电流 - 电压特性。当前的操舵元件（i）具有第一电流操舵元件电极，第一半导体层和第二电流操舵元件电极依次层叠的结构，（ⅱ）包括覆盖侧面的第二半导体层的第一电流操舵元件电极，第一半导体层和第二电流操舵元件电极。

9. 发明授权

US08537605B2 Nonvolatile semiconductor memory device having coplanar surfaces at resistance variable layer and wiring layer and manufacturing method thereof 有权
标题翻译：在电阻变化层和布线层具有共面的非易失性半导体存储器件及其制造方法
公开(公告)号：US08537605B2
公开(公告)日：2013-09-17
申请号：US12867437
申请日：2009-02-09
申请人： Takumi Mikawa , Yoshio Kawashima , Koji Arita , Takeki Ninomiya
发明人： Takumi Mikawa , Yoshio Kawashima , Koji Arita , Takeki Ninomiya
IPC分类号： G11C11/14
CPC分类号： H01L27/101 , H01L27/2436 , H01L45/04 , H01L45/1233 , H01L45/146 , H01L45/1675
摘要： A nonvolatile semiconductor memory device (100) comprises a substrate (102) provided with a transistor (101); a first interlayer insulating layer (103) formed over the substrate to cover the transistor; a first contact plug (104) formed in the first interlayer insulating layer and electrically connected to either of a drain electrode (101a) or a source electrode (101b) of the transistor, and a second contact plug (105) formed in the first interlayer insulating layer and electrically connected to the other of the drain electrode or the source electrode of the transistor; a resistance variable layer (106) formed to cover a portion of the first contact plug; a first wire (107) formed on the resistance variable layer; and a second wire (108) formed to cover a portion of the second contact plug; an end surface of the resistance variable layer being coplanar with an end surface of the first wire.
摘要翻译：非易失性半导体存储器件（100）包括设置有晶体管（101）的衬底（102）; 形成在所述衬底上以覆盖所述晶体管的第一层间绝缘层（103）形成在所述第一层间绝缘层中并电连接到所述晶体管的漏电极（101a）或源电极（101b）中的任一个的第一接触插塞（104）和形成在所述第一中间层绝缘层并与晶体管的漏电极或源电极中的另一个电连接; 形成为覆盖所述第一接触插塞的一部分的电阻变化层（106）形成在电阻变化层上的第一线（107）以及形成为覆盖所述第二接触插塞的一部分的第二线（108）所述电阻变化层的端面与所述第一线的端面共面。

10. 发明申请

US20130171799A1 CURRENT STEERING ELEMENT AND NON-VOLATILE MEMORY ELEMENT INCORPORATING CURRENT STEERING ELEMENT 有权
标题翻译：电流转向元件和非易失性存储元件包含电流转向元件
公开(公告)号：US20130171799A1
公开(公告)日：2013-07-04
申请号：US13823667
申请日：2011-09-16
申请人： Ryoko Miyanaga , Takumi Mikawa , Yukio Hayakawa , Takeki Ninomiya , Koji Arita
发明人： Ryoko Miyanaga , Takumi Mikawa , Yukio Hayakawa , Takeki Ninomiya , Koji Arita
IPC分类号： H01L45/00 , H01L21/768
CPC分类号： H01L45/16 , H01L21/768 , H01L27/101 , H01L27/2409 , H01L27/2418 , H01L45/00 , H01L45/04 , H01L45/1233 , H01L45/146
摘要： A current steering element (100) formed such that the current steering element covers a lower opening (105) of a via hole (104) formed in an interlayer insulating layer (102), comprises: a corrosion-suppressing layer (106) formed on a lower side of a lower opening of the via hole such that the corrosion-suppressing layer covers an entire portion of the lower opening; a second electrode layer (108) formed under the corrosion-suppressing layer and comprising a material different from a material of the corrosion-suppressing layer; a current steering layer (110) formed under the second electrode layer such that the current steering layer is physically in contact with the second electrode layer; and a first electrode layer (112) formed under the current steering layer such that the first electrode layer is physically in contact with the current steering layer; and the first electrode layer, the current steering layer and the second electrode layer constitute one of a MSM diode and a MIM diode.
摘要翻译：一种形成为当前的操舵元件覆盖形成在层间绝缘层（102）中的通孔（104）的下开口（105）的电流控制元件（100），包括：形成在通孔的下开口的下侧，使得防蚀层覆盖下开口的整个部分; 形成在所述腐蚀抑制层下方并且包含不同于所述腐蚀抑制层的材料的材料的第二电极层（108）形成在所述第二电极层下方的电流转向层（110），使得所述电流导向层物理地与所述第二电极层接触; 以及第一电极层（112），形成在所述电流导向层下方，使得所述第一电极层物理地与所述电流转向层接触; 并且第一电极层，电流导向层和第二电极层构成MSM二极管和MIM二极管之一。

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