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71. 发明申请

US20130265818A1 WRITE CONTENTION-FREE, NOISE-TOLERANT MULTI-PORT BITCELL 有权
标题翻译：无限制，无噪声多端口BITCELL
公开(公告)号：US20130265818A1
公开(公告)日：2013-10-10
申请号：US13441414
申请日：2012-04-06
申请人： Ambica Ashok , Ravindraraj Ramaraju , Andrew C. Russell
发明人： Ambica Ashok , Ravindraraj Ramaraju , Andrew C. Russell
IPC分类号： G11C11/413
CPC分类号： G11C8/16 , G11C7/12 , G11C7/18 , G11C8/14 , G11C11/419
摘要： A multi-port memory cell of a multi-port memory array includes a first inverter that inverter is disabled by a first subset of write word lines and a second inverter, cross coupled with the first inverter, wherein the second inverter is disabled by a second subset of the plurality of write word lines. A first selection circuit has data inputs coupled to a first subset of a plurality of write bit lines, selection inputs coupled to the first subset of the plurality of write word lines, and an output coupled to the input of the second inverter. The second selection circuit has data inputs coupled to a second subset of the plurality of write bit lines, selection inputs coupled to the second subset of the plurality of write word lines, and an output coupled to the input of the first inverter.
摘要翻译：多端口存储器阵列的多端口存储单元包括第一反相器，反相器被写入字线的第一子集禁止，第二反相器与第一反相器交叉耦合，其中第二反相器被第二反相器禁用多个写入字线的子集。第一选择电路具有耦合到多个写位线的第一子集的数据输入，耦合到多个写字线的第一子集的选择输入以及耦合到第二反相器的输入的输出。第二选择电路具有耦合到多个写位线的第二子集的数据输入，耦合到多个写字线的第二子集的选择输入以及耦合到第一反相器的输入的输出。

72. 发明授权

US08484523B2 Sequential digital circuitry with test scan 有权
标题翻译：具有测试扫描的顺序数字电路
公开(公告)号：US08484523B2
公开(公告)日：2013-07-09
申请号：US12729826
申请日：2010-03-23
申请人： Ravindraraj Ramaraju , Prashant U. Kenkare , Gary A. Mussemann , Mihir S. Sabnis
发明人： Ravindraraj Ramaraju , Prashant U. Kenkare , Gary A. Mussemann , Mihir S. Sabnis
IPC分类号： G01R31/28
CPC分类号： G06F11/267 , G01R31/318541 , G01R31/318575
摘要： A digital scan chain system having test scan has a plurality of flip-flop modules, each of the plurality of flip-flop modules having a first data bit input, a second data bit input, a test bit input, a clock input, a first data bit output, a second data bit output, and a test bit output. The test bit output of a first flip-flop module is directly connected to the test bit input of a second flip-flop module with no intervening circuitry. First and second multiplexed master/slave flip-flops are directly serially connected. A clocked latch is coupled to the output of the second multiplexed master/slave flip-flop and provides the test bit output. The clocked latch is clocked only during a test mode to save power.
摘要翻译：具有测试扫描的数字扫描链系统具有多个触发器模块，多个触发器模块中的每一个具有第一数据位输入，第二数据位输入，测试位输入，时钟输入，第一数据位输出，第二数据位输出和测试位输出。第一触发器模块的测试位输出直接连接到第二触发器模块的测试位输入，而没有中间电路。第一和第二复用主/从触发器直接串行连接。时钟锁存器耦合到第二复用主/从触发器的输出并提供测试位输出。时钟锁存器仅在测试模式下计时才能节省电量。

73. 发明授权

US08379468B2 Word line fault detection 有权
标题翻译：字线故障检测
公开(公告)号：US08379468B2
公开(公告)日：2013-02-19
申请号：US13169397
申请日：2011-06-27
申请人： Ravindraraj Ramaraju , Alexander B. Hoefler
发明人： Ravindraraj Ramaraju , Alexander B. Hoefler
IPC分类号： G11C29/00
CPC分类号： G11C29/025 , G11C11/40 , G11C29/024 , G11C2029/1202 , G11C2029/2602
摘要： In a memory having a word line driver and a ROM having N bit positions and a plurality of rows in which each row is coupled to a corresponding word line of the word line driver and stores a unique N bit value, a method includes activating, by the word line driver, a selected word line, and, for each bit position, determining whether a value of a true bit line of the bit position is at a same logic state as a value of a complementary bit line of the bit position when the word line driver activates the selected word line. In response to determining that a value of the true bit line is at the same logic state as the value of the complementary bit line for any of the N bit positions, providing a multiple word line fault indicator indicating that multiple word lines are activated simultaneously.
摘要翻译：在具有字线驱动器和具有N位位置的ROM的存储器和多行中，其中每行耦合到字线驱动器的对应字线并存储唯一的N位值，该方法包括通过字线驱动器，所选字线，并且对于每个位位置，确定位位置的真位线的值是否与位位置的互补位线的值处于与位位置的互补位线的值相同的逻辑状态字线驱动程序激活所选字线。响应于确定真位位线的值与用于任何N位位置的互补位线的值处于相同的逻辑状态，提供指示多个字线同时被激活的多字线故障指示符。

74. 发明授权

US08143929B2 Flip-flop having shared feedback and method of operation 有权
标题翻译：触发器具有共享的反馈和操作方法
公开(公告)号：US08143929B2
公开(公告)日：2012-03-27
申请号：US12607574
申请日：2009-10-28
申请人： Ravindraraj Ramaraju , Prashant U. Kenkare
发明人： Ravindraraj Ramaraju , Prashant U. Kenkare
IPC分类号： H03K3/356
CPC分类号： H03K3/356156 , H03K3/356173
摘要： A method of operating a circuit includes receiving a first data signal at a first node. The first node is coupled to a second node to couple the first data signal to the second node. After coupling the first node to the second node, the second node is coupled to a third node to couple the first data signal to the third node. The first node is decoupled from the second node and a first step of latching the first data signal at the third node is performed, wherein the first step of latching is through the second node while the second node is coupled to the third node. The second node is decoupled from the third node and a second step of latching is performed wherein the first data signal latched at the third node while the second node is decoupled from the third node.
摘要翻译：一种操作电路的方法包括在第一节点处接收第一数据信号。第一节点耦合到第二节点以将第一数据信号耦合到第二节点。在将第一节点耦合到第二节点之后，第二节点耦合到第三节点以将第一数据信号耦合到第三节点。执行第一节点与第二节点的耦合，并且执行在第三节点处锁存第一数据信号的第一步骤，其中锁定的第一步骤是通过第二节点，而第二节点耦合到第三节点。第二节点与第三节点分离，并执行锁定的第二步骤，其中第一数据信号在第三节点处锁存，而第二节点与第三节点分离。

75. 发明申请

US20120033520A1 MEMORY WITH LOW VOLTAGE MODE OPERATION 有权
标题翻译：低电压模式运行的存储器
公开(公告)号：US20120033520A1
公开(公告)日：2012-02-09
申请号：US12850533
申请日：2010-08-04
申请人： Huy B. Nguyen , Troy L. Cooper , Ravindraraj Ramaraju , Andrew C. Russell
发明人： Huy B. Nguyen , Troy L. Cooper , Ravindraraj Ramaraju , Andrew C. Russell
IPC分类号： G11C5/14
CPC分类号： G11C11/417
摘要： A memory comprising memory cells wherein the memory is configured to operate in a normal voltage mode and a low voltage mode. The method includes during the normal voltage mode, operating the memory cells at a first voltage across each of the memory cells. The method further includes upon transitioning from the normal voltage mode to the low voltage mode, operating the memory cells at a second voltage across each of the memory cells, wherein the second voltage is lower than the first voltage. The method further includes performing an access on a subset of the memory cells while maintaining the second voltage across the memory cells.
摘要翻译：一种存储器，包括存储器单元，其中存储器被配置为在正常电压模式和低电压模式下操作。该方法包括在正常电压模式期间，以每个存储器单元的第一电压操作存储器单元。该方法还包括在从正常电压模式转换到低电压模式时，在每个存储单元上以第二电压操作存储单元，其中第二电压低于第一电压。该方法还包括在保持存储器单元两端的第二电压的同时对存储器单元的子集执行访问。

76. 发明申请

US20120032655A1 MULTISTAGE VOLTAGE REGULATOR CIRCUIT 有权
标题翻译：多电平电压调节器电路
公开(公告)号：US20120032655A1
公开(公告)日：2012-02-09
申请号：US12853106
申请日：2010-08-09
申请人： Ravindraraj Ramaraju , Kenneth R. Burch , Charles E. Seaberg
发明人： Ravindraraj Ramaraju , Kenneth R. Burch , Charles E. Seaberg
IPC分类号： G05F1/10
CPC分类号： G11C5/147 , G05F1/00 , G05F1/577
摘要： A circuit including a multistage voltage regulator having a plurality of stages each including a regulated node and a bias transistor. The bias transistors and regulated nodes are configured to control the voltage of the regulated nodes. For at least some of the stages, the regulated nodes are coupled to voltage supply terminals of circuit modules of the stages.
摘要翻译：一种电路，包括具有多个级的多级稳压器，每个级包括调节节点和偏置晶体管。偏置晶体管和调节节点配置为控制受调节节点的电压。对于至少一些级，调节节点耦合到级的电路模块的电压端。

77. 发明申请

US20100312957A1 TRANSLATION LOOK-ASIDE BUFFER WITH A TAG MEMORY AND METHOD THEREFOR 有权
标题翻译：翻译带有标记内存的缓冲区及其方法
公开(公告)号：US20100312957A1
公开(公告)日：2010-12-09
申请号：US12480809
申请日：2009-06-09
申请人： Ravindraraj Ramaraju , Jogendra C. Sarker , Vu N. Tran
发明人： Ravindraraj Ramaraju , Jogendra C. Sarker , Vu N. Tran
IPC分类号： G06F12/00 , G06F12/10 , G06F12/08
CPC分类号： G06F12/1027 , G06F12/0895
摘要： A translation look-aside buffer (TLB) has a TAG memory for determining if a desired translated address is stored in the TLB. A TAG portion is compared to contents of the TAG memory without requiring a read of the TAG memory because the TAG memory has a storage portion that is constructed as a CAM. For each row of the CAM a match determination is made that indicates if the TAG portion is the same as contents of the particular row. A decoder decodes an index portion and provides an output for each row. On a per row basis the output of the decoder is logically combined with the hit/miss signals to determine if there is a hit for the TAG memory. If there is a hit for the TAG memory, a translated address corresponding to the index portion of the address is then output as the selected translated address.
摘要翻译：翻译后备缓冲器（TLB）具有用于确定所需翻译地址是否存储在TLB中的TAG存储器。将TAG部分与TAG存储器的内容进行比较，而不需要读取TAG存储器，因为TAG存储器具有构造为CAM的存储部分。对于CAM的每一行，进行匹配确定，其指示TAG部分是否与特定行的内容相同。解码器解码索引部分并为每行提供输出。在每行的基础上，解码器的输出与命中/未命中信号逻辑地组合以确定是否存在对TAG存储器的命中。如果存在TAG存储器的命中，则将与地址的索引部分相对应的翻译地址作为选择的翻译地址输出。

78. 发明授权

US07626842B2 Photon-based memory device and method thereof 有权
标题翻译：基于光子的存储器件及其方法
公开(公告)号：US07626842B2
公开(公告)日：2009-12-01
申请号：US11560607
申请日：2006-11-16
申请人： Ravindraraj Ramaraju
发明人： Ravindraraj Ramaraju
IPC分类号： G11C13/04 , G11C5/06
CPC分类号： G11C13/044
摘要： A memory device includes a bit cell including an adjustable transmittance component having a first side and a second side. The adjustable transmittance component has an adjustable transmittance state representative of a bit value of the bit cell. The memory device further includes a photon detector optically coupled to a second side of the adjustable transmittance component. A technique related to the memory device includes determining a transmittance state of the adjustable transmittance component and providing a bit value for the bit cell based on the transmittance state. Another technique related to the memory device includes determining a bit value to be stored at the bit cell and configuring the adjustable transmittance component to have a transmittance state corresponding to the bit value.
摘要翻译：存储器件包括具有第一侧和第二侧的可调节透射率分量的位单元。可调节的透射率分量具有表示位单元的位值的可调透射率状态。存储器件还包括光学检测器，其光学耦合到可调透射率分量的第二侧。与存储器件相关的技术包括：确定可调节的透射率分量的透射率状态，并且基于透射率状态提供位单元的位值。与存储器件相关的另一技术包括确定要存储在位单元处的位值，并且将可调透射率分量配置为具有对应于位值的透射率状态。

79. 发明授权

US07545702B2 Memory pipelining in an integrated circuit memory device using shared word lines 有权
标题翻译：在使用共享字线的集成电路存储器件中的存储器流水线
公开(公告)号：US07545702B2
公开(公告)日：2009-06-09
申请号：US11459170
申请日：2006-07-21
申请人： Prashant Kenkare , Ravindraraj Ramaraju , Ambica Ashok
发明人： Prashant Kenkare , Ravindraraj Ramaraju , Ambica Ashok
IPC分类号： G11C8/10 , G11C8/14
CPC分类号： G11C7/1039 , G06F12/0855 , G06F12/0864 , G06F2212/1016 , G06F2212/6082 , G11C2207/2245 , Y02D10/13
摘要： A method for pipelining a memory in an integrated circuit includes providing a first clock phase and providing a second clock phase, wherein the first clock phase and the second clock phase are at least partially non-overlapping. The method further includes providing a first memory array and providing a second memory array, wherein the second memory array shares a wordline with the first memory array. The method further includes using said wordline to select at least one row of the first memory array during the first clock phase. The method further includes using said wordline to select at least one row of the second memory array during the second clock phase.
摘要翻译：用于在集成电路中流水线存储器的方法包括提供第一时钟相位和提供第二时钟相位，其中第一时钟相位和第二时钟相位至少部分地不重叠。该方法还包括提供第一存储器阵列并提供第二存储器阵列，其中第二存储器阵列与第一存储器阵列共享字线。该方法还包括在第一时钟阶段期间使用所述字线来选择第一存储器阵列的至少一行。该方法还包括在第二时钟阶段期间使用所述字线来选择第二存储器阵列的至少一行。

80. 发明申请

US20080198681A1 MULTIPLE PORT MEMORY WITH PRIORITIZED WORD LINE DRIVER AND METHOD THEREOF 有权
标题翻译：具有优先级字线驱动器的多端口存储器及其方法
公开(公告)号：US20080198681A1
公开(公告)日：2008-08-21
申请号：US11676341
申请日：2007-02-19
申请人： Prashant U. Kenkare , Ravindraraj Ramaraju , Troy L. Cooper
发明人： Prashant U. Kenkare , Ravindraraj Ramaraju , Troy L. Cooper
IPC分类号： G11C8/16
CPC分类号： G11C8/10 , G11C8/08 , G11C8/16
摘要： A multiple port memory has a word line driver that provides a word line signal to access a first write port of a multiple port memory cell in an array of multiple port memory cells during a write operation. A first logic circuit has a first input for receiving a first port selection signal, a second input for receiving a disable signal, and an output. A buffer circuit has an input coupled to the output of the first logic circuit, and an output for providing the word line signal. The disable signal is asserted to prevent the word line driver from accessing the first write port when a second write port of the multiple port memory cell is accessed during the write operation and the second write port has a higher priority than the first write port.
摘要翻译：多端口存储器具有字线驱动器，其在写操作期间提供字线信号以访问多端口存储器单元阵列中的多端口存储器单元的第一写端口。第一逻辑电路具有用于接收第一端口选择信号的第一输入端，用于接收禁止信号的第二输入端和输出端。缓冲电路具有耦合到第一逻辑电路的输出的输入和用于提供字线信号的输出。当在写入操作期间访问多端口存储器单元的第二写入端口并且第二写入端口具有比第一写入端口更高的优先级时，禁止信号被断言以防止字线驱动器访问第一写入端口。

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