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1. 发明授权

US08755244B2 Write contention-free, noise-tolerant multi-port bitcell 有权
标题翻译：写入无争用，耐噪声的多端口位单元
公开(公告)号：US08755244B2
公开(公告)日：2014-06-17
申请号：US13441414
申请日：2012-04-06
申请人： Ambica Ashok , Ravindraraj Ramaraju , Andrew C. Russell
发明人： Ambica Ashok , Ravindraraj Ramaraju , Andrew C. Russell
IPC分类号： G11C8/00 , G11C11/00
CPC分类号： G11C8/16 , G11C7/12 , G11C7/18 , G11C8/14 , G11C11/419
摘要： A multi-port memory cell of a multi-port memory array includes a first inverter that inverter is disabled by a first subset of write word lines and a second inverter, cross coupled with the first inverter, wherein the second inverter is disabled by a second subset of the plurality of write word lines. A first selection circuit has data inputs coupled to a first subset of a plurality of write bit lines, selection inputs coupled to the first subset of the plurality of write word lines, and an output coupled to the input of the second inverter. The second selection circuit has data inputs coupled to a second subset of the plurality of write bit lines, selection inputs coupled to the second subset of the plurality of write word lines, and an output coupled to the input of the first inverter.
摘要翻译：多端口存储器阵列的多端口存储单元包括第一反相器，反相器被写入字线的第一子集禁止，第二反相器与第一反相器交叉耦合，其中第二反相器被第二反相器禁用多个写入字线的子集。第一选择电路具有耦合到多个写位线的第一子集的数据输入，耦合到多个写字线的第一子集的选择输入以及耦合到第二反相器的输入的输出。第二选择电路具有耦合到多个写位线的第二子集的数据输入，耦合到多个写字线的第二子集的选择输入以及耦合到第一反相器的输入的输出。

2. 发明申请

US20130265818A1 WRITE CONTENTION-FREE, NOISE-TOLERANT MULTI-PORT BITCELL 有权
标题翻译：无限制，无噪声多端口BITCELL
公开(公告)号：US20130265818A1
公开(公告)日：2013-10-10
申请号：US13441414
申请日：2012-04-06
申请人： Ambica Ashok , Ravindraraj Ramaraju , Andrew C. Russell
发明人： Ambica Ashok , Ravindraraj Ramaraju , Andrew C. Russell
IPC分类号： G11C11/413
CPC分类号： G11C8/16 , G11C7/12 , G11C7/18 , G11C8/14 , G11C11/419
摘要： A multi-port memory cell of a multi-port memory array includes a first inverter that inverter is disabled by a first subset of write word lines and a second inverter, cross coupled with the first inverter, wherein the second inverter is disabled by a second subset of the plurality of write word lines. A first selection circuit has data inputs coupled to a first subset of a plurality of write bit lines, selection inputs coupled to the first subset of the plurality of write word lines, and an output coupled to the input of the second inverter. The second selection circuit has data inputs coupled to a second subset of the plurality of write bit lines, selection inputs coupled to the second subset of the plurality of write word lines, and an output coupled to the input of the first inverter.
摘要翻译：多端口存储器阵列的多端口存储单元包括第一反相器，反相器被写入字线的第一子集禁止，第二反相器与第一反相器交叉耦合，其中第二反相器被第二反相器禁用多个写入字线的子集。第一选择电路具有耦合到多个写位线的第一子集的数据输入，耦合到多个写字线的第一子集的选择输入以及耦合到第二反相器的输入的输出。第二选择电路具有耦合到多个写位线的第二子集的数据输入，耦合到多个写字线的第二子集的选择输入以及耦合到第一反相器的输入的输出。

3. 发明授权

US08533578B2 Error detection in a content addressable memory (CAM) and method of operation 有权
标题翻译：内容可寻址存储器（CAM）中的错误检测和操作方法
公开(公告)号：US08533578B2
公开(公告)日：2013-09-10
申请号：US12813974
申请日：2010-06-11
申请人： Ravindraraj Ramaraju , Ambica Ashok , Kent W. Li
发明人： Ravindraraj Ramaraju , Ambica Ashok , Kent W. Li
IPC分类号： G11C29/00
CPC分类号： G11C15/04 , G06F11/1064 , H03M13/09
摘要： A method for accessing a content addressable memory (CAM) system having a CAM and random access memory (RAM) includes providing comparand data to the CAM, comparing the comparand data to entries of the CAM to determine a matching CAM entry and asserting a match signal corresponding to the matching CAM entry. In response to asserting the match signal, the method further includes providing output data, an output parity bit, and an output complement parity bit from the RAM, using the comparand data to generate a generated parity bit, and providing an error indicator based on the generated parity bit, the output parity bit, and the output complement parity bit. The error indicator may indicate an error when the generated parity bit is not equal to the output parity bit or when the output parity bit is equal to the output complement parity bit.
摘要翻译：一种用于访问具有CAM和随机存取存储器（RAM）的内容可寻址存储器（CAM）系统的方法，包括向CAM提供比较数据，将比较数据与CAM的条目进行比较，以确定匹配的CAM条目并确定匹配信号对应于匹配的CAM条目。响应于确定匹配信号，该方法还包括使用比较数据从RAM提供输出数据，输出奇偶校验位和输出补码奇偶校验位，以产生生成的奇偶校验位，并且基于产生的奇偶校验位，输出奇偶校验位和输出补码奇偶校验位。当产生的奇偶校验位不等于输出奇偶校验位时，或当输出奇偶校验位等于输出补码奇偶校验位时，错误指示器可能指示错误。

4. 发明授权

US07545702B2 Memory pipelining in an integrated circuit memory device using shared word lines 有权
标题翻译：在使用共享字线的集成电路存储器件中的存储器流水线
公开(公告)号：US07545702B2
公开(公告)日：2009-06-09
申请号：US11459170
申请日：2006-07-21
申请人： Prashant Kenkare , Ravindraraj Ramaraju , Ambica Ashok
发明人： Prashant Kenkare , Ravindraraj Ramaraju , Ambica Ashok
IPC分类号： G11C8/10 , G11C8/14
CPC分类号： G11C7/1039 , G06F12/0855 , G06F12/0864 , G06F2212/1016 , G06F2212/6082 , G11C2207/2245 , Y02D10/13
摘要： A method for pipelining a memory in an integrated circuit includes providing a first clock phase and providing a second clock phase, wherein the first clock phase and the second clock phase are at least partially non-overlapping. The method further includes providing a first memory array and providing a second memory array, wherein the second memory array shares a wordline with the first memory array. The method further includes using said wordline to select at least one row of the first memory array during the first clock phase. The method further includes using said wordline to select at least one row of the second memory array during the second clock phase.
摘要翻译：用于在集成电路中流水线存储器的方法包括提供第一时钟相位和提供第二时钟相位，其中第一时钟相位和第二时钟相位至少部分地不重叠。该方法还包括提供第一存储器阵列并提供第二存储器阵列，其中第二存储器阵列与第一存储器阵列共享字线。该方法还包括在第一时钟阶段期间使用所述字线来选择第一存储器阵列的至少一行。该方法还包括在第二时钟阶段期间使用所述字线来选择第二存储器阵列的至少一行。

5. 发明授权

US07984229B2 Pipelined tag and information array access with speculative retrieval of tag that corresponds to information access 有权
标题翻译：流水线标签和信息数组访问，与信息访问相对应的标签的推测检索
公开(公告)号：US07984229B2
公开(公告)日：2011-07-19
申请号：US11684529
申请日：2007-03-09
申请人： Ravindraraj Ramaraju , Ambica Ashok , David R. Bearden , Prashant U. Kenkare
发明人： Ravindraraj Ramaraju , Ambica Ashok , David R. Bearden , Prashant U. Kenkare
IPC分类号： G06F12/00
CPC分类号： G06F12/0895 , Y02D10/13
摘要： A cache design is described in which corresponding accesses to tag and information arrays are phased in time, and in which tags are retrieved (typically speculatively) from a tag array without benefit of an effective address calculation subsequently used for a corresponding retrieval from an information array. In some exploitations, such a design may allow cycle times (and throughput) of a memory subsystem to more closely match demands of some processor and computation system architectures. Our techniques seek to allow early (indeed speculative) retrieval from the tag array without delays that would otherwise be associated with calculation of an effective address eventually employed for a corresponding retrieval from the information array. Speculation can be resolved using the eventually calculated effective address or using separate functionality. In some embodiments, we use calculated effective addresses for way selection based on tags retrieved from the tag array.
摘要翻译：描述了一种高速缓存设计，其中对标签和信息数组的相应访问在时间上是相位的，并且其中从标签数组中检索（通常是推测性地）的标签，而不受随后用于从信息数组的相应检索的有效地址计算的益处。在一些开发中，这样的设计可以允许存储器子系统的周期时间（和吞吐量）更接近地匹配一些处理器和计算系统架构的需求。我们的技术旨在允许从标签数组中提前（确实是推测性的）检索，而不会延迟，否则将与从信息数组中相应检索最终采用的有效地址的计算相关联。可以使用最终计算的有效地址或使用单独的功能来解决投机。在一些实施例中，我们使用基于从标签阵列检索的标签的方法选择的计算的有效地址。

6. 发明申请

US20110307769A1 ERROR DETECTION IN A CONTENT ADDRESSABLE MEMORY (CAM) AND METHOD OF OPERATION 有权
标题翻译：内容可寻址存储器（CAM）中的错误检测和操作方法
公开(公告)号：US20110307769A1
公开(公告)日：2011-12-15
申请号：US12813974
申请日：2010-06-11
申请人： Ravindraraj Ramaraju , Ambica Ashok , Kent W. Li
发明人： Ravindraraj Ramaraju , Ambica Ashok , Kent W. Li
IPC分类号： H03M13/09 , G11C15/00 , G11C7/00 , G06F11/10
CPC分类号： G11C15/04 , G06F11/1064 , H03M13/09
摘要： A method for accessing a content addressable memory (CAM) system having a CAM and random access memory (RAM) includes providing comparand data to the CAM, comparing the comparand data to entries of the CAM to determine a matching CAM entry and asserting a match signal corresponding to the matching CAM entry. In response to asserting the match signal, the method further includes providing output data, an output parity bit, and an output complement parity bit from the RAM, using the comparand data to generate a generated parity bit, and providing an error indicator based on the generated parity bit, the output parity bit, and the output complement parity bit. The error indicator may indicate an error when the generated parity bit is not equal to the output parity bit or when the output parity bit is equal to the output complement parity bit.
摘要翻译：一种用于访问具有CAM和随机存取存储器（RAM）的内容可寻址存储器（CAM）系统的方法，包括向CAM提供比较数据，将比较数据与CAM的条目进行比较，以确定匹配的CAM条目并确定匹配信号对应于匹配的CAM条目。响应于确定匹配信号，该方法还包括使用比较数据从RAM提供输出数据，输出奇偶校验位和输出补码奇偶校验位，以产生生成的奇偶校验位，并且基于产生的奇偶校验位，输出奇偶校验位和输出补码奇偶校验位。当产生的奇偶校验位不等于输出奇偶校验位时，或当输出奇偶校验位等于输出补码奇偶校验位时，错误指示器可能指示错误。

7. 发明授权

US07548102B2 Data latch with minimal setup time and launch delay 有权
标题翻译：数据锁存器具有最小的建立时间和启动延迟
公开(公告)号：US07548102B2
公开(公告)日：2009-06-16
申请号：US11457668
申请日：2006-07-14
申请人： Ravindraraj Ramaraju , Ambica Ashok , Cody B. Croxton , Peter M. Ippolito , Prashant U. Kenkare
发明人： Ravindraraj Ramaraju , Ambica Ashok , Cody B. Croxton , Peter M. Ippolito , Prashant U. Kenkare
IPC分类号： H03K3/289
CPC分类号： H03K3/0375 , H03K3/356156
摘要： The present invention provides a latch circuit that is operable to generate a pulse from first and second clock signals to allow gates in a datapath to propagate data with minimal latency. The first clock signal is a version of the system clock and the second control signal is a time-shifted, inverted version of the system clock signal. Each of the individual latches in a datapath comprises data propagation logic. In one embodiment of the invention, the data propagation logic uses the first and second clock signals to generate an “implicit” pulse. In another embodiment of the invention, the data propagation logic uses the first and second clock signals to generate an “explicit” pulse. The implicit and explicit pulses are used to control the transmission gate of the latch to provide propagation of data through the latch with minimal latency.
摘要翻译：本发明提供了一种锁存电路，其可操作以从第一和第二时钟信号产生脉冲，以允许数据路径中的门以最小延迟传播数据。第一时钟信号是系统时钟的版本，第二控制信号是系统时钟信号的时移反转版本。数据路径中的每个锁存器包括数据传播逻辑。在本发明的一个实施例中，数据传播逻辑使用第一和第二时钟信号来产生“隐含”脉冲。在本发明的另一个实施例中，数据传播逻辑使用第一和第二时钟信号来产生“显式”脉冲。隐式和显式脉冲用于控制锁存器的传输门，以最小的延迟提供数据通过锁存器的传播。

8. 发明申请

US20080222361A1 PIPELINED TAG AND INFORMATION ARRAY ACCESS WITH SPECULATIVE RETRIEVAL OF TAG THAT CORRESPONDS TO INFORMATION ACCESS 有权
标题翻译：管道标签和信息阵列访问与信息访问相关的标签的检索
公开(公告)号：US20080222361A1
公开(公告)日：2008-09-11
申请号：US11684529
申请日：2007-03-09
申请人： Ravindraraj Ramaraju , Ambica Ashok , David R. Bearden , Prashant U. Kenkare
发明人： Ravindraraj Ramaraju , Ambica Ashok , David R. Bearden , Prashant U. Kenkare
IPC分类号： G06F12/08
CPC分类号： G06F12/0895 , Y02D10/13
摘要： A cache design is described in which corresponding accesses to tag and information arrays are phased in time, and in which tags are retrieved (typically speculatively) from a tag array without benefit of an effective address calculation subsequently used for a corresponding retrieval from an information array. In some exploitations, such a design may allow cycle times (and throughput) of a memory subsystem to more closely match demands of some processor and computation system architectures. In some cases, phased access can be described as pipelined tag and information array access, though strictly speaking, indexing into the information array need not depend on results of the tag array access. Our techniques seek to allow early (indeed speculative) retrieval from the tag array without delays that would otherwise be associated with calculation of an effective address eventually employed for a corresponding retrieval from the information array. Speculation can be resolved using the eventually calculated effective address or using separate functionality. In some embodiments, we use calculated effective addresses for way selection based on tags retrieved from the tag array.
摘要翻译：描述了一种高速缓存设计，其中对标签和信息数组的相应访问在时间上是相位的，并且其中从标签数组中检索（通常是推测性地）的标签，而不受随后用于从信息数组的相应检索的有效地址计算的益处。在一些开发中，这样的设计可以允许存储器子系统的周期时间（和吞吐量）更接近地匹配一些处理器和计算系统架构的需求。在某些情况下，分阶段访问可以被描述为流水线标签和信息数组访问，但严格来说，索引到信息数组不需要依赖于标签数组访问的结果。我们的技术旨在允许从标签数组中提前（确实是推测性的）检索，而不会延迟，否则将与从信息数组中相应检索最终采用的有效地址的计算相关联。可以使用最终计算的有效地址或使用单独的功能来解决投机。在一些实施例中，我们使用基于从标签阵列检索的标签的方法选择的计算的有效地址。

9. 发明申请

US20080022064A1 MEMORY PIPELINING IN AN INTEGRATED CIRCUIT 有权
标题翻译：集成电路中的存储器管路
公开(公告)号：US20080022064A1
公开(公告)日：2008-01-24
申请号：US11459170
申请日：2006-07-21
申请人： Prashant Kenkare , Ravindraraj Ramaraju , Ambica Ashok
发明人： Prashant Kenkare , Ravindraraj Ramaraju , Ambica Ashok
IPC分类号： G06F13/00
CPC分类号： G11C7/1039 , G06F12/0855 , G06F12/0864 , G06F2212/1016 , G06F2212/6082 , G11C2207/2245 , Y02D10/13
摘要： A method for pipelining a memory in an integrated circuit includes providing a first clock phase and providing a second clock phase, wherein the first clock phase and the second clock phase are at least partially non-overlapping. The method further includes providing a first memory array and providing a second memory array, wherein the second memory array shares a wordline with the first memory array. The method further includes using said wordline to select at least one row of the first memory array during the first clock phase. The method further includes using said wordline to select at least one row of the second memory array during the second clock phase.
摘要翻译：用于在集成电路中流水线存储器的方法包括提供第一时钟相位和提供第二时钟相位，其中第一时钟相位和第二时钟相位至少部分地不重叠。该方法还包括提供第一存储器阵列并提供第二存储器阵列，其中第二存储器阵列与第一存储器阵列共享字线。该方法还包括在第一时钟阶段期间使用所述字线来选择第一存储器阵列的至少一行。该方法还包括在第二时钟阶段期间使用所述字线来选择第二存储器阵列的至少一行。

10. 发明申请

US20080012618A1 Data Latch 有权
标题翻译：数据锁
公开(公告)号：US20080012618A1
公开(公告)日：2008-01-17
申请号：US11457668
申请日：2006-07-14
申请人： Ravindraraj Ramaraju , Ambica Ashok , Cody B. Croxton , Peter M. Ippolito , Prashant U. Kenkare
发明人： Ravindraraj Ramaraju , Ambica Ashok , Cody B. Croxton , Peter M. Ippolito , Prashant U. Kenkare
IPC分类号： H03K3/289
CPC分类号： H03K3/0375 , H03K3/356156
摘要： The present invention provides a latch circuit that is operable to generate a pulse from first and second clock signals to allow gates in a datapath to propagate data with minimal latency. The first clock signal is a version of the system clock and the second control signal is a time-shifted, inverted version of the system clock signal. Each of the individual latches in a datapath comprises data propagation logic. In one embodiment of the invention, the data propagation logic uses the first and second clock signals to generate an “implicit” pulse. In another embodiment of the invention, the data propagation logic uses the first and second clock signals to generate an “explicit” pulse. The implicit and explicit pulses are used to control the transmission gate of the latch to provide propagation of data through the latch with minimal latency.
摘要翻译：本发明提供了一种锁存电路，其可操作以从第一和第二时钟信号产生脉冲，以允许数据路径中的门以最小延迟传播数据。第一时钟信号是系统时钟的版本，第二控制信号是系统时钟信号的时移反转版本。数据路径中的每个锁存器包括数据传播逻辑。在本发明的一个实施例中，数据传播逻辑使用第一和第二时钟信号来产生“隐含”脉冲。在本发明的另一个实施例中，数据传播逻辑使用第一和第二时钟信号来产生“显式”脉冲。隐式和显式脉冲用于控制锁存器的传输门，以最小的延迟提供数据通过锁存器的传播。

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