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1. 发明授权

US08537625B2 Memory voltage regulator with leakage current voltage control 有权
标题翻译：内存电压调节器，具有漏电流电压控制
公开(公告)号：US08537625B2
公开(公告)日：2013-09-17
申请号：US13045294
申请日：2011-03-10
申请人： Ravindraraj Ramaraju , Shayan Zhang , Kenneth R. Burch , Charles E. Seaberg , Andrew C. Russell
发明人： Ravindraraj Ramaraju , Shayan Zhang , Kenneth R. Burch , Charles E. Seaberg , Andrew C. Russell
IPC分类号： G11C11/412
CPC分类号： G11C11/417 , G11C5/147 , G11C11/412 , G11C29/021 , G11C29/028
摘要： A voltage regulator for a memory that regulates a voltage provided to the memory cells based on a measured leakage current from a second set of memory cells. In one embodiment, based on the measured leakage current, the voltage to the cells is raised or lowered to control the amount of leakage current from the cells.
摘要翻译：一种用于存储器的电压调节器，其基于来自第二组存储器单元的测量的泄漏电流来调节提供给存储器单元的电压。在一个实施例中，基于测量的漏电流，提高或降低对电池的电压以控制来自电池的泄漏电流的量。

2. 发明申请

US20100207687A1 CIRCUIT FOR A LOW POWER MODE 有权
标题翻译：低功耗模式电路
公开(公告)号：US20100207687A1
公开(公告)日：2010-08-19
申请号：US12372997
申请日：2009-02-18
申请人： Ravindraraj Ramaraju , David R. Bearden , Kenneth R. Burch , Charles E. Seaberg
发明人： Ravindraraj Ramaraju , David R. Bearden , Kenneth R. Burch , Charles E. Seaberg
IPC分类号： G05F1/10
CPC分类号： G05F1/56 , G11C5/147
摘要： A circuit has a first transistor having a first current electrode coupled to a first supply voltage terminal and a second current electrode coupled to a virtual supply voltage node. A second transistor has a first current electrode coupled to the first supply voltage terminal and a control electrode coupled to the virtual supply voltage node. A first load has an input and has an output coupled to a second current electrode of the second transistor. A third transistor has a control electrode coupled to the output of the first load. A second load has an input coupled to the first supply voltage terminal, and has an output that is coupled to both a control electrode of the first transistor and a first current electrode of the third transistor. The virtual supply voltage node provides an operating voltage to a circuit module that alternates between normal and drowsy operating modes.
摘要翻译：电路具有第一晶体管，其具有耦合到第一电源电压端子的第一电流电极和耦合到虚拟电源电压节点的第二电流电极。第二晶体管具有耦合到第一电源电压端子的第一电流电极和耦合到虚拟电源电压节点的控制电极。第一负载具有输入并且具有耦合到第二晶体管的第二电流电极的输出。第三晶体管具有耦合到第一负载的输出的控制电极。第二负载具有耦合到第一电源电压端子的输入，并且具有耦合到第一晶体管的控制电极和第三晶体管的第一电流电极两者的输出。虚拟电源电压节点向在正常和困倦的操作模式之间交替的电路模块提供工作电压。

3. 发明授权

US09117507B2 Multistage voltage regulator circuit 有权
标题翻译：多级稳压电路
公开(公告)号：US09117507B2
公开(公告)日：2015-08-25
申请号：US12853106
申请日：2010-08-09
申请人： Ravindraraj Ramaraju , Kenneth R. Burch , Charles E. Seaberg
发明人： Ravindraraj Ramaraju , Kenneth R. Burch , Charles E. Seaberg
IPC分类号： G05F1/10 , G11C5/14 , G05F1/577 , G05F1/00
CPC分类号： G11C5/147 , G05F1/00 , G05F1/577
摘要： Circuit embodiments of a multistage voltage regulator circuit are presented, where a circuit includes a first stage that includes a first bias transistor having a current terminal coupled to a first regulated node. The circuit also includes a second stage that includes a second bias transistor having a current terminal coupled to a second regulated node. The circuit also includes a third stage including a third bias transistor having a current terminal coupled to a third node. The circuit also includes a control loop for regulating voltages at the first and second regulated nodes, where the second regulated node is connected to a control terminal of the first bias transistor; and where the first regulated node is connected to a control terminal of the third bias transistor.
摘要翻译：呈现多级电压调节器电路的电路实施例，其中电路包括第一级，其包括具有耦合到第一调节节点的电流端的第一偏置晶体管。电路还包括第二级，其包括具有耦合到第二调节节点的电流端子的第二偏置晶体管。电路还包括第三级，包括具有耦合到第三节点的电流端子的第三偏置晶体管。电路还包括用于调节第一和第二调节节点处的电压的控制回路，其中第二调节节点连接到第一偏置晶体管的控制端子; 并且其中第一调节节点连接到第三偏置晶体管的控制端子。

4. 发明授权

US08319548B2 Integrated circuit having low power mode voltage regulator 有权
标题翻译：集成电路具有低功耗模式电压调节器
公开(公告)号：US08319548B2
公开(公告)日：2012-11-27
申请号：US12622277
申请日：2009-11-19
申请人： Ravindraraj Ramaraju , David R. Bearden , Kenneth R. Burch , Charles E. Seaberg , Hector Sanchez , Bradley J. Garni
发明人： Ravindraraj Ramaraju , David R. Bearden , Kenneth R. Burch , Charles E. Seaberg , Hector Sanchez , Bradley J. Garni
IPC分类号： G05F1/10
CPC分类号： G05F1/56 , G11C5/147
摘要： A voltage regulator regulates voltage at a node and has circuitry coupled to the node for providing a current to the node. A regulating transistor coupled between the node and a first power supply voltage terminal has a disabling transistor coupled in parallel and is selectively disabled by directly connecting the first power supply voltage terminal to the node. An inverting stage has an output connected to the regulating transistor. A load transistor has a first current electrode coupled to a second power supply voltage terminal, and a control electrode and second current electrode connected together and coupled to an input of the inverting stage. A sensing transistor has a first current electrode coupled to the second current electrode of the load transistor, a control electrode connected directly to the node and a second current electrode coupled to the first power supply voltage terminal.
摘要翻译：电压调节器调节节点处的电压，并且具有耦合到节点的电路以向节点提供电流。耦合在节点和第一电源电压端子之间的调节晶体管具有并联耦合的禁用晶体管，并且通过将第一电源电压端子直接连接到节点来选择性地禁止。反相级具有连接到调节晶体管的输出端。负载晶体管具有耦合到第二电源电压端子的第一电流电极和连接在一起并耦合到反相级的输入端的控制电极和第二电流电极。感测晶体管具有耦合到负载晶体管的第二电流电极的第一电流电极，直接连接到节点的控制电极和耦合到第一电源电压端子的第二电流电极。

5. 发明申请

US20120032655A1 MULTISTAGE VOLTAGE REGULATOR CIRCUIT 有权
标题翻译：多电平电压调节器电路
公开(公告)号：US20120032655A1
公开(公告)日：2012-02-09
申请号：US12853106
申请日：2010-08-09
申请人： Ravindraraj Ramaraju , Kenneth R. Burch , Charles E. Seaberg
发明人： Ravindraraj Ramaraju , Kenneth R. Burch , Charles E. Seaberg
IPC分类号： G05F1/10
CPC分类号： G11C5/147 , G05F1/00 , G05F1/577
摘要： A circuit including a multistage voltage regulator having a plurality of stages each including a regulated node and a bias transistor. The bias transistors and regulated nodes are configured to control the voltage of the regulated nodes. For at least some of the stages, the regulated nodes are coupled to voltage supply terminals of circuit modules of the stages.
摘要翻译：一种电路，包括具有多个级的多级稳压器，每个级包括调节节点和偏置晶体管。偏置晶体管和调节节点配置为控制受调节节点的电压。对于至少一些级，调节节点耦合到级的电路模块的电压端。

6. 发明申请

US20120230126A1 MEMORY VOLTAGE REGULATOR WITH LEAKAGE CURRENT VOLTAGE CONTROL 有权
标题翻译：具有漏电流电压控制的存储电压调节器
公开(公告)号：US20120230126A1
公开(公告)日：2012-09-13
申请号：US13045294
申请日：2011-03-10
申请人： Ravindraraj Ramaraju , Shayan Zhang , Kenneth R. Burch , Charles E. Seaberg , Andrew C. Russell
发明人： Ravindraraj Ramaraju , Shayan Zhang , Kenneth R. Burch , Charles E. Seaberg , Andrew C. Russell
IPC分类号： G11C5/14 , G11C7/14 , G11C7/00
CPC分类号： G11C11/417 , G11C5/147 , G11C11/412 , G11C29/021 , G11C29/028
摘要： A voltage regulator for a memory that regulates a voltage provided to the memory cells based on a measured leakage current from a second set of memory cells. In one embodiment, based on the measured leakage current, the voltage to the cells is raised or lowered to control the amount of leakage current from the cells.
摘要翻译：一种用于存储器的电压调节器，其基于来自第二组存储器单元的测量的泄漏电流来调节提供给存储器单元的电压。在一个实施例中，基于测量的漏电流，提高或降低对电池的电压以控制来自电池的泄漏电流的量。

7. 发明授权

US07825720B2 Circuit for a low power mode 有权
标题翻译：低功耗模式电路
公开(公告)号：US07825720B2
公开(公告)日：2010-11-02
申请号：US12372997
申请日：2009-02-18
申请人： Ravindraraj Ramaraju , David R. Bearden , Kenneth R. Burch , Charles E. Seaberg
发明人： Ravindraraj Ramaraju , David R. Bearden , Kenneth R. Burch , Charles E. Seaberg
IPC分类号： G05F1/10
CPC分类号： G05F1/56 , G11C5/147
摘要： A circuit has a first transistor having a first current electrode coupled to a first supply voltage terminal and a second current electrode coupled to a virtual supply voltage node. A second transistor has a first current electrode coupled to the first supply voltage terminal and a control electrode coupled to the virtual supply voltage node. A first load has an input and has an output coupled to a second current electrode of the second transistor. A third transistor has a control electrode coupled to the output of the first load. A second load has an input coupled to the first supply voltage terminal, and has an output that is coupled to both a control electrode of the first transistor and a first current electrode of the third transistor. The virtual supply voltage node provides an operating voltage to a circuit module that alternates between normal and drowsy operating modes.
摘要翻译：电路具有第一晶体管，其具有耦合到第一电源电压端子的第一电流电极和耦合到虚拟电源电压节点的第二电流电极。第二晶体管具有耦合到第一电源电压端子的第一电流电极和耦合到虚拟电源电压节点的控制电极。第一负载具有输入并且具有耦合到第二晶体管的第二电流电极的输出。第三晶体管具有耦合到第一负载的输出的控制电极。第二负载具有耦合到第一电源电压端子的输入，并且具有耦合到第一晶体管的控制电极和第三晶体管的第一电流电极两者的输出。虚拟电源电压节点向在正常和困倦的操作模式之间交替的电路模块提供工作电压。

8. 发明授权

US06658245B2 Radio receiver having a dynamic bandwidth filter and method therefor 有权
公开(公告)号：US06658245B2
公开(公告)日：2003-12-02
申请号：US09818337
申请日：2001-03-28
申请人： Junsong Li , Charles E. Seaberg , Jie Su
发明人： Junsong Li , Charles E. Seaberg , Jie Su
IPC分类号： H04B110
CPC分类号： H04B1/1036
摘要： A radio receiver (100) has an IF (intermediate frequency) filter (200) for dynamically adjusting its intermediate frequency. The filter (200) includes a filter bank (301), power/amplitude estimator circuits (308, 310, 312), and weighting circuits (314, 316, 318). The filter bank (301) generates sub-bands, each sub-band having a predetermined frequency range. The power/amplitude estimators (308, 310, 312) provide an estimated power/amplitude in each sub-band. A filter control (320) uses the power/amplitude estimates to determine a percentage of each sub-band signal that is permitted to be coupled a summation circuit (319). The summation circuit (319) sums the weighted sub-band signals to provide a filtered output signal to a demodulator (212).

9. 发明授权

US06760386B2 Receiver and method therefor 有权
标题翻译：接收机及其方法
公开(公告)号：US06760386B2
公开(公告)日：2004-07-06
申请号：US09916915
申请日：2001-07-27
申请人： Junsong Li , Jon D. Hendrix , Charles E. Seaberg
发明人： Junsong Li , Jon D. Hendrix , Charles E. Seaberg
IPC分类号： H04L102
CPC分类号： H04B7/0865 , H04B1/1081 , H04B1/28 , H04B7/0871 , H04B7/0891
摘要： Embodiments of the present invention relate generally to receivers. One embodiment relates to a digital FM receiver having multiple sensors (e.g. antennas). In one embodiment, the digital receiver includes a baseband unit having a channel processing unit. In one embodiment, the channel processing unit is capable of calculating or estimating a phase difference between the incoming signals prior to combining them. One embodiment uses phase estimation method for diversity combining the signals while another embodiment utlizes a hybrid phase lock loop method. Also, some embodiments of the present invention provide for echo-cancelling after diversity combining. An alternate embodiment of the channel processing unit utilizes a space-time unit to diversity combine and provide echo cancelling for the incoming signals. Other embodiments of the present invention allow for the incoming signals from the multiple antennas to pass through the baseband unit uncombined, where the incoming signals may have different data formats.
摘要翻译：本发明的实施例一般涉及接收机。一个实施例涉及具有多个传感器（例如，天线）的数字FM接收机。在一个实施例中，数字接收机包括具有信道处理单元的基带单元。在一个实施例中，信道处理单元能够在组合它们之前计算或估计输入信号之间的相位差。一个实施例使用相位估计方法用于组合信号的分集，而另一实施例利用混合锁相环方法。此外，本发明的一些实施例提供了在分集组合之后的回波消除。信道处理单元的另一实施例利用时空单元进行分集组合，并为输入信号提供回波消除。本发明的其他实施例允许来自多个天线的输入信号通过未组合的基带单元，其中输入信号可以具有不同的数据格式。

10. 发明授权

US09294081B2 System and method for breakdown protection for switching output driver 有权
标题翻译：开关输出驱动器的故障保护系统和方法
公开(公告)号：US09294081B2
公开(公告)日：2016-03-22
申请号：US14229270
申请日：2014-03-28
申请人： Chang Joon Park , Charles E. Seaberg
发明人： Chang Joon Park , Charles E. Seaberg
IPC分类号： H03K3/00 , H03K17/08 , H03K17/687
CPC分类号： H03K17/08 , H03K17/08122 , H03K17/6872
摘要： An integrated circuit device includes a driver circuit (100) having a pull-up network with a first pull-up transistor (108) coupled to a second pull-up transistor (110) at a first node (VP), and a pull-down network coupled to the pull-up network including a first pull-down transistor (112) coupled to a second pull-down transistor (114) at a second node (VN). A first bias switch (116) is coupled to the first node. A second bias switch (118) is coupled to the second node. A control circuit (104) is coupled to operate the first and second bias switches. The first bias switch is operated to reduce a voltage at the first node during a pull-down cycle of the driver circuit and the second bias switch is operated to reduce a voltage at the second node during a pull-up cycle of the driver circuit.
摘要翻译：集成电路装置包括具有上拉网络的驱动器电路（100），其中第一上拉晶体管（108）在第一节点（VP）处耦合到第二上拉晶体管（110）耦合到上拉网络的下拉网络包括在第二节点（VN）处耦合到第二下拉晶体管（114）的第一下拉晶体管（112）。第一偏置开关（116）耦合到第一节点。第二偏置开关（118）耦合到第二节点。耦合控制电路（104）以操作第一和第二偏置开关。操作第一偏置开关以在驱动器电路的下拉周期期间减小第一节点处的电压，并且在驱动器电路的上拉周期期间操作第二偏置开关以降低第二节点处的电压。

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