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1. 发明申请

US20120033520A1 MEMORY WITH LOW VOLTAGE MODE OPERATION 有权
标题翻译：低电压模式运行的存储器
公开(公告)号：US20120033520A1
公开(公告)日：2012-02-09
申请号：US12850533
申请日：2010-08-04
申请人： Huy B. Nguyen , Troy L. Cooper , Ravindraraj Ramaraju , Andrew C. Russell
发明人： Huy B. Nguyen , Troy L. Cooper , Ravindraraj Ramaraju , Andrew C. Russell
IPC分类号： G11C5/14
CPC分类号： G11C11/417
摘要： A memory comprising memory cells wherein the memory is configured to operate in a normal voltage mode and a low voltage mode. The method includes during the normal voltage mode, operating the memory cells at a first voltage across each of the memory cells. The method further includes upon transitioning from the normal voltage mode to the low voltage mode, operating the memory cells at a second voltage across each of the memory cells, wherein the second voltage is lower than the first voltage. The method further includes performing an access on a subset of the memory cells while maintaining the second voltage across the memory cells.
摘要翻译：一种存储器，包括存储器单元，其中存储器被配置为在正常电压模式和低电压模式下操作。该方法包括在正常电压模式期间，以每个存储器单元的第一电压操作存储器单元。该方法还包括在从正常电压模式转换到低电压模式时，在每个存储单元上以第二电压操作存储单元，其中第二电压低于第一电压。该方法还包括在保持存储器单元两端的第二电压的同时对存储器单元的子集执行访问。

2. 发明授权

US08514611B2 Memory with low voltage mode operation 有权
标题翻译：内存低电压模式运行
公开(公告)号：US08514611B2
公开(公告)日：2013-08-20
申请号：US12850533
申请日：2010-08-04
申请人： Huy B. Nguyen , Troy L. Cooper , Ravindraraj Ramaraju , Andrew C. Russell
发明人： Huy B. Nguyen , Troy L. Cooper , Ravindraraj Ramaraju , Andrew C. Russell
IPC分类号： G11C11/00
CPC分类号： G11C11/417
摘要： A memory comprising memory cells wherein the memory is configured to operate in a normal voltage mode and a low voltage mode. The method includes during the normal voltage mode, operating the memory cells at a first voltage across each of the memory cells. The method further includes upon transitioning from the normal voltage mode to the low voltage mode, operating the memory cells at a second voltage across each of the memory cells, wherein the second voltage is lower than the first voltage. The method further includes performing an access on a subset of the memory cells while maintaining the second voltage across the memory cells.
摘要翻译：一种存储器，包括存储器单元，其中存储器被配置为在正常电压模式和低电压模式下操作。该方法包括在正常电压模式期间，以每个存储器单元的第一电压操作存储器单元。该方法还包括在从正常电压模式转换到低电压模式时，在每个存储单元上以第二电压操作存储单元，其中第二电压低于第一电压。该方法还包括在保持存储器单元两端的第二电压的同时对存储器单元的子集执行访问。

3. 发明授权

US09367475B2 System and method for cache access 有权
标题翻译：用于缓存访问的系统和方法
公开(公告)号：US09367475B2
公开(公告)日：2016-06-14
申请号：US13440728
申请日：2012-04-05
申请人： Ravindraraj Ramaraju , David R. Bearden , Andrew C. Russell
发明人： Ravindraraj Ramaraju , David R. Bearden , Andrew C. Russell
IPC分类号： G06F12/00 , G06F13/00 , G06F12/08 , G06F1/32
CPC分类号： G06F12/0895 , G06F1/3225 , G06F1/3275 , Y02D10/13 , Y02D10/14 , Y02D50/20
摘要： The rows of a cache are generally maintained in a low power state. In response to a memory access operation, the data processor predicts a plurality of cache rows that may be targeted by the operation, and transitions each of the plurality of cache rows to an active state to prepare them for access. The plurality of cache rows are predicted based on speculatively decoding a portion of a base address and a corresponding portion of an offset without performing a full addition of the portions. Because a full addition is not performed, the speculative decoding can be performed at sufficient speed to allow the set of rows to be transitioned to the active state before full decoding of the memory address is completed. The cache row associated with the memory address is therefore ready for access when decoding is complete, maintaining low latency for cache accesses.
摘要翻译：缓存的行通常维持在低功率状态。响应于存储器访问操作，数据处理器预测可能由操作定向的多个高速缓存行，并且将多个高速缓存行中的每一个转换为活动状态以准备它们进行访问。基于对基本地址的一部分和偏移的对应部分的推测性解码来预测多个高速缓存行，而不执行部分的完全添加。由于没有执行完全相加，所以可以以足够的速度执行推测解码，以便在存储器地址的完全解码完成之前允许该组行转换到活动状态。因此，当解码完成时，与存储器地址相关联的高速缓存行可以进行访问，从而保持高速缓存访问的低延迟。

4. 发明授权

US09367437B2 Method and apparatus for reducing the number of speculative accesses to a memory array 有权
标题翻译：用于减少对存储器阵列的推测访问次数的方法和装置
公开(公告)号：US09367437B2
公开(公告)日：2016-06-14
申请号：US13831870
申请日：2013-03-15
申请人： Andrew C. Russell , Ravindraraj Ramaraju
发明人： Andrew C. Russell , Ravindraraj Ramaraju
IPC分类号： G06F12/00 , G06F12/02 , G06F9/34 , G06F12/06
CPC分类号： G06F12/00 , G06F9/34 , G06F12/0207 , G06F12/0215 , G06F12/06 , G06F2212/1028 , Y02D10/13
摘要： A method includes: receiving a first plurality of consecutive bits from a base operand, wherein a MSB of the first plurality of consecutive bits from the base operand is a LSB of a second plurality of consecutive bits from the base operand; and receiving a first plurality of consecutive bits from an offset operand, wherein a MSB of the first plurality of consecutive bits from the offset operand is a LSB of a second plurality of consecutive bits from the offset operand. The method includes summing the first plurality of consecutive bits from the base operand with the first plurality of consecutive bits from the offset operand to generate a sum value; and allowing access to one of a plurality of memory arrays and disabling access to the remainder of the plurality of memory arrays when a lesser significant bit to a MSB of the sum value equals zero.
摘要翻译：一种方法包括：从基本操作数接收第一多个连续比特，其中来自基本操作数的第一多个连续比特的MSB是来自基本操作数的第二多个连续比特的LSB; 以及从偏移操作数接收第一多个连续比特，其中来自所述偏移操作数的所述第一多个连续比特的MSB是来自所述偏移操作数的第二多个连续比特的LSB。该方法包括将来自基本操作数的第一多个连续比特与来自该偏移操作数的第一多个连续比特相加以产生和值; 并且当和值的MSB的较低有效位等于零时，允许访问多个存储器阵列中的一个并且禁止对多个存储器阵列的其余部分的访问。

5. 发明授权

US09081693B2 Data type dependent memory scrubbing 有权
标题翻译：数据类型相关内存擦除
公开(公告)号：US09081693B2
公开(公告)日：2015-07-14
申请号：US13588243
申请日：2012-08-17
申请人： Ravindraraj Ramaraju , William C. Moyer , Andrew C. Russell
发明人： Ravindraraj Ramaraju , William C. Moyer , Andrew C. Russell
IPC分类号： G06F12/00 , G06F12/08 , G06F11/10
CPC分类号： G06F12/0895 , G06F11/106 , G06F11/1064 , Y02D10/13
摘要： A method for controlling a memory scrubbing rate based on content of the status bit of a tag array of a cache memory. More specifically, the tag array of a cache memory is scrubbed at smaller interval than the scrubbing rate of the storage arrays of the cache. This increased scrubbing rate is in appreciation for the importance of maintaining integrity of tag data. Based on the content of the status bit of the tag array which indicates modified, the corresponding data entry in the cache storage array is scrubbed accordingly. If the modified bit is set, then the entry in the storage array is scrubbed after processing the tag entry. If the modified bit is not set, then the storage array is scrubbed at a predetermined scrubbing interval.
摘要翻译：一种用于基于高速缓冲存储器的标签阵列的状态位的内容来控制存储器擦除速率的方法。更具体地说，高速缓冲存储器的标签阵列以比缓存的存储阵列的擦除速率更小的间隔进行擦除。对于保持标签数据完整性的重要性，这种提高的清洗率是值得赞赏的。基于指示被修改的标签阵列的状态位的内容，相应地擦除缓存存储阵列中的相应数据条目。如果修改的位被设置，则在处理标签条目之后擦除存储阵列中的条目。如果未设置修改的位，则以预定的擦洗间隔擦除存储阵列。

6. 发明申请

US20140269131A1 MEMORY WITH POWER SAVINGS FOR UNNECESSARY READS 有权
标题翻译：具有省电功能的记忆用于不必要的阅读
公开(公告)号：US20140269131A1
公开(公告)日：2014-09-18
申请号：US13826427
申请日：2013-03-14
申请人： Ravindraraj Ramaraju , George P. Hoekstra , Andrew C. Russell
发明人： Ravindraraj Ramaraju , George P. Hoekstra , Andrew C. Russell
IPC分类号： G11C7/08
CPC分类号： G11C7/08 , G11C8/12
摘要： A memory device includes a plurality of sense amplifiers, an array of memory cells including a first subset of memory cells, and a plurality of word lines. Each word line is coupled to each memory cell in a respective row of the memory cells and each row of the memory cells includes one memory cell of the first subset of memory cells. Each of a plurality of control word lines is coupled to a respective one of the memory cells in the first subset of memory cells and each of the memory cells in the first subset of memory cells generates a sense amplifier control signal coupled to control operation of a respective one of the plurality of sense amplifiers.
摘要翻译：存储器件包括多个读出放大器，包括存储器单元的第一子集的存储器单元阵列和多个字线。每个字线被耦合到存储器单元的相应行中的每个存储器单元，并且每行存储器单元包括存储器单元的第一子集的一个存储单元。多个控制字线中的每一个耦合到存储器单元的第一子集中的相应的一个存储器单元，并且存储器单元的第一子集中的每个存储单元产生一个读出放大器控制信号，相应的多个读出放大器之一。

7. 发明授权

US08755244B2 Write contention-free, noise-tolerant multi-port bitcell 有权
标题翻译：写入无争用，耐噪声的多端口位单元
公开(公告)号：US08755244B2
公开(公告)日：2014-06-17
申请号：US13441414
申请日：2012-04-06
申请人： Ambica Ashok , Ravindraraj Ramaraju , Andrew C. Russell
发明人： Ambica Ashok , Ravindraraj Ramaraju , Andrew C. Russell
IPC分类号： G11C8/00 , G11C11/00
CPC分类号： G11C8/16 , G11C7/12 , G11C7/18 , G11C8/14 , G11C11/419
摘要： A multi-port memory cell of a multi-port memory array includes a first inverter that inverter is disabled by a first subset of write word lines and a second inverter, cross coupled with the first inverter, wherein the second inverter is disabled by a second subset of the plurality of write word lines. A first selection circuit has data inputs coupled to a first subset of a plurality of write bit lines, selection inputs coupled to the first subset of the plurality of write word lines, and an output coupled to the input of the second inverter. The second selection circuit has data inputs coupled to a second subset of the plurality of write bit lines, selection inputs coupled to the second subset of the plurality of write word lines, and an output coupled to the input of the first inverter.
摘要翻译：多端口存储器阵列的多端口存储单元包括第一反相器，反相器被写入字线的第一子集禁止，第二反相器与第一反相器交叉耦合，其中第二反相器被第二反相器禁用多个写入字线的子集。第一选择电路具有耦合到多个写位线的第一子集的数据输入，耦合到多个写字线的第一子集的选择输入以及耦合到第二反相器的输入的输出。第二选择电路具有耦合到多个写位线的第二子集的数据输入，耦合到多个写字线的第二子集的选择输入以及耦合到第一反相器的输入的输出。

8. 发明申请

US20120200336A1 ELECTRONIC CIRCUIT HAVING SHARED LEAKAGE CURRENT REDUCTION CIRCUITS 有权
标题翻译：具有共享漏电流减少电路的电子电路
公开(公告)号：US20120200336A1
公开(公告)日：2012-08-09
申请号：US13020565
申请日：2011-02-03
申请人： Ravindraraj Ramaraju , David R. Bearden , Andrew C. Russell , Shayan Zhang
发明人： Ravindraraj Ramaraju , David R. Bearden , Andrew C. Russell , Shayan Zhang
IPC分类号： H03K3/011 , G05F1/10
CPC分类号： H03K19/0008 , H03K19/0016
摘要： An electronic circuit includes a plurality of circuit blocks, a plurality of bias circuits, a switching circuit, and plurality of transistors. The plurality of circuit blocks each includes a high power terminal and a low power terminal. The switching circuit includes a plurality of switches for selectively coupling a bias circuit of the plurality of bias circuits to the low power terminal of a circuit block of the plurality of circuit blocks. Each bias circuit of the plurality of bias circuits is selectively couplable to the low power terminal of each of the plurality of circuit blocks. Each transistor of the plurality of transistors has a first current terminal coupled to a circuit ground terminal, and each transistor of the plurality of transistors has a control terminal for controlling the conductivity of the plurality of the transistors by a bias circuit of the plurality of bias circuits.
摘要翻译：电子电路包括多个电路块，多个偏置电路，开关电路和多个晶体管。多个电路块各自包括高功率端子和低功率端子。开关电路包括多个开关，用于将多个偏置电路的偏置电路选择性地耦合到多个电路块的电路块的低功率端子。多个偏置电路的每个偏置电路可以选择性地耦合到多个电路块中的每一个的低功率端子。多个晶体管的每个晶体管具有耦合到电路接地端子的第一电流端子，并且多个晶体管中的每个晶体管具有控制端子，用于通过多个偏置的偏置电路来控制多个晶体管的导电性电路。

9. 发明申请

US20150293810A1 CONTENT ADDRESSABLE MEMORY WITH ERROR DETECTION 有权
标题翻译：内容可寻址存储器，具有错误检测
公开(公告)号：US20150293810A1
公开(公告)日：2015-10-15
申请号：US14251719
申请日：2014-04-14
申请人： RAVINDRARAJ RAMARAJU , Mihir A. Pandya , Andrew C. Russell
发明人： RAVINDRARAJ RAMARAJU , Mihir A. Pandya , Andrew C. Russell
IPC分类号： G06F11/08
CPC分类号： G06F11/1064
摘要： A content addressable memory (CAM) includes a first entry which includes one or more bits, a second entry which includes one or more bits, first comparison circuitry configured to compare each bit of a comparand to a corresponding bit of the one or more bits of the first entry and to provide a hit/miss indicator in response thereto, and second comparison circuitry configured to compare each bit of the one or more bits of the first entry to a corresponding bit of the one or more bits of the second entry and to provide a fault indicator in response thereto.
摘要翻译：内容可寻址存储器（CAM）包括包括一个或多个比特的第一条目，包括一个或多个比特的第二条目，第一比较电路，被配置为将对比的每个比特与一个或多个比特的相应比特进行比较第一条目并响应于此提供命中/未命中指示符，以及第二比较电路，其被配置为将第一条目的一个或多个比特的每个比特与第二条目的一个或多个比特的对应比特进行比较，提供响应于此的故障指示器。

10. 发明授权

US09141451B2 Memory having improved reliability for certain data types 有权
标题翻译：内存具有提高某些数据类型的可靠性
公开(公告)号：US09141451B2
公开(公告)日：2015-09-22
申请号：US13736310
申请日：2013-01-08
申请人： Andrew C. Russell , Ravindraraj Ramaraju
发明人： Andrew C. Russell , Ravindraraj Ramaraju
IPC分类号： G06F11/00 , G06F11/10 , G06F11/07 , G06F12/08
CPC分类号： G06F11/004 , G06F11/073 , G06F11/1064 , G06F12/0846
摘要： A method for minimizing soft error rates within caches by configuring a cache with certain sections to correspond to bitcell topologies that are more resistant to soft errors and then using these sections to store modified data.
摘要翻译：一种通过配置具有某些部分的高速缓存来对应于比较弱的软错误，然后使用这些部分来存储修改的数据的比特单元拓扑来最小化高速缓存内的软错误率的方法。

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