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71. 发明授权

US06735141B2 Semiconductor memory device having an SRAM and a DRAM on a single chip 失效
标题翻译：在单个芯片上具有SRAM和DRAM的半导体存储器件
公开(公告)号：US06735141B2
公开(公告)日：2004-05-11
申请号：US09917913
申请日：2001-07-31
申请人： Hitoshi Ikeda , Akihiro Funyu , Shinya Fujioka , Takaaki Suzuki , Masao Taguchi , Kimiaki Satoh , Kotoku Sato
发明人： Hitoshi Ikeda , Akihiro Funyu , Shinya Fujioka , Takaaki Suzuki , Masao Taguchi , Kimiaki Satoh , Kotoku Sato
IPC分类号： G11C700
CPC分类号： G11C11/005
摘要： A semiconductor memory device includes an SRAM provided on a chip, the SRAM including an SRAM cell array. A DRAM is provided on the chip, the DRAM including a DRAM cell array. An address input circuit receives an address signal, the address signal having a first portion and a second portion, the first portion carrying a unique value of row-column address information provided to access one of memory locations in one of the SRAM and DRAM cell arrays, the second portion carrying a unique value of SRAM/DRAM address information provided to select one of the SRAM and the DRAM.
摘要翻译：半导体存储器件包括设置在芯片上的SRAM，SRAM包括SRAM单元阵列。在芯片上提供DRAM，DRAM包括DRAM单元阵列。地址输入电路接收地址信号，地址信号具有第一部分和第二部分，第一部分承载提供用于访问SRAM和DRAM单元阵列之一中的存储单元之一的行列地址信息的唯一值，第二部分承载提供用于选择SRAM和DRAM之一的SRAM / DRAM地址信息的唯一值。

72. 发明授权

US06584032B2 Dynamic random access memory having a low power consumption mode, and method of operating the same 有权
标题翻译：具有低功耗模式的动态随机存取存储器及其操作方法
公开(公告)号：US06584032B2
公开(公告)日：2003-06-24
申请号：US09949847
申请日：2001-09-12
申请人： Shinya Fujioka , Tomohiro Kawakubo , Koichi Nishimura , Kotoku Sato
发明人： Shinya Fujioka , Tomohiro Kawakubo , Koichi Nishimura , Kotoku Sato
IPC分类号： G11C700
CPC分类号： G06F1/3234 , G06F1/3203 , G06F1/3268 , G06F1/3275 , G11C5/14 , G11C5/145 , G11C5/147 , G11C11/406 , G11C11/40615 , G11C14/00 , G11C2207/2227 , G11C2211/4067 , H02M3/07 , Y02D10/13 , Y02D10/14 , Y02D50/20
摘要： An internal voltage generator when activated, generates an internal voltage to be supplied to an internal circuit. Operating the internal voltage generator consumes a predetermined amount of the power. In response to a control signal from the exterior, an entry circuit inactivates the internal voltage generator. When the internal voltage generator is inactivated, the internal voltage is not generated, thereby reducing the power consumption. By the control signal from the exterior, therefore, a chip can easily enter a low power consumption mode. The internal voltage generator is exemplified by a booster for generating the boost voltage of a word line connected with memory cells, a substrate voltage generator for generating a substrate voltage, or a precharging voltage generator for generating the precharging voltage of bit lines to be connected with the memory cells.
摘要翻译：内部电压发生器激活时，产生内部电压供给内部电路。操作内部电压发生器消耗预定量的功率。响应来自外部的控制信号，入口电路使内部电压发生器失活。内部电压发生器未激活时，不产生内部电压，从而降低功耗。因此，通过来自外部的控制信号，芯片可以容易地进入低功耗模式。内部电压发生器的例子是用于产生与存储器单元连接的字线的升压电压的升压器，用于产生衬底电压的衬底电压发生器或用于产生要连接的位线的预充电电压的预充电电压发生器记忆细胞。

73. 发明授权

US06566937B1 Fuse circuit 有权
标题翻译：保险丝电路
公开(公告)号：US06566937B1
公开(公告)日：2003-05-20
申请号：US10152579
申请日：2002-05-23
申请人： Katsuhiro Mori , Shinya Fujioka , Masahiro Niimi
发明人： Katsuhiro Mori , Shinya Fujioka , Masahiro Niimi
IPC分类号： H01H3776
CPC分类号： G11C17/16
摘要： Upon receiving a level of a second node through a third switch in the first half of a first period, a holding circuit outputs it as a fuse signal indicating a blown-out state of a fuse. Since the third switch turns off in the second half of the first period, a change in level of the second node occurring thereafter will not affect data in the holding circuit, whereby prevents malfunction of a fuse circuit. With the fuse blown, a level of a first node gets fixed at that of a second power supply line after the first period. This eliminates a voltage difference between both ends of the fuse, thereby preventing a growback. No occurrence of growback makes just one fuse blowing sufficient for the fuse circuit even with the fuse not completely cut off. This consequently shortens a time for blowing the fuse in a test process.
摘要翻译：在第一周期的前半段通过第三开关接收到第二节点的电平时，保持电路将其作为指示保险丝的熔断状态的熔丝信号输出。由于在第一周期的后半部分中第三开关断开，所以其后发生的第二节点的电平变化不会影响保持电路中的数据，从而防止熔丝电路的故障。在保险丝熔断时，在第一周期之后，第一节点的电平固定在第二电源线的电平上。这消除了保险丝两端之间的电压差，从而防止了长时间的恢复。即使没有完全切断保险丝，也不会发生长时间退回，只有一个保险丝对保险丝电路充足。从而缩短了在测试过程中熔断熔断器的时间。

74. 发明授权

US06563746B2 Circuit for entering/exiting semiconductor memory device into/from low power consumption mode and method of controlling internal circuit at low power consumption mode 有权
标题翻译：用于从低功耗模式进入/退出半导体存储器件的电路以及在低功耗模式下控制内部电路的方法
公开(公告)号：US06563746B2
公开(公告)日：2003-05-13
申请号：US09820795
申请日：2001-03-30
申请人： Shinya Fujioka , Tomohiro Kawakubo , Koichi Nishimura , Kotoku Sato
发明人： Shinya Fujioka , Tomohiro Kawakubo , Koichi Nishimura , Kotoku Sato
IPC分类号： G11C700
CPC分类号： G06F1/3234 , G06F1/3203 , G06F1/3268 , G06F1/3275 , G11C5/14 , G11C5/145 , G11C5/147 , G11C11/406 , G11C11/40615 , G11C14/00 , G11C2207/2227 , G11C2211/4067 , H02M3/07 , Y02D10/13 , Y02D10/14 , Y02D50/20
摘要： An internal voltage generator when activated, generates an internal voltage to be supplied to an internal circuit. Operating the internal voltage generator consumes a predetermined amount of the power. In response to a control signal from the exterior, an entry circuit inactivates the internal voltage generator. When the internal voltage generator is inactivated, the internal voltage is not generated, thereby reducing the power consumption. By the control signal from the exterior, therefore, a chip can easily enter a low power consumption mode. The internal voltage generator is exemplified by a booster for generating the boost voltage of a word line connected with memory cells, a substrate voltage generator for generating a substrate voltage, or a precharging voltage generator for generating the precharging voltage of bit lines to be connected with the memory cells.
摘要翻译：内部电压发生器激活时，产生内部电压供给内部电路。操作内部电压发生器消耗预定量的功率。响应来自外部的控制信号，入口电路使内部电压发生器失活。内部电压发生器未激活时，不产生内部电压，从而降低功耗。因此，通过来自外部的控制信号，芯片可以容易地进入低功耗模式。内部电压发生器的例子是用于产生与存储器单元连接的字线的升压电压的升压器，用于产生衬底电压的衬底电压发生器或用于产生要连接的位线的预充电电压的预充电电压发生器记忆细胞。

75. 发明授权

US06535950B1 Semiconductor memory device having a refresh operation 有权
标题翻译：具有刷新操作的半导体存储器件
公开(公告)号：US06535950B1
公开(公告)日：2003-03-18
申请号：US09536988
申请日：2000-03-29
申请人： Akihiro Funyu , Shinya Fujioka , Hitoshi Ikeda , Takaaki Suzuki , Masao Taguchi , Kimiaki Satoh , Kotoku Sato , Yasurou Matsuzaki
发明人： Akihiro Funyu , Shinya Fujioka , Hitoshi Ikeda , Takaaki Suzuki , Masao Taguchi , Kimiaki Satoh , Kotoku Sato , Yasurou Matsuzaki
IPC分类号： G11C114093
CPC分类号： G11C7/1042 , G11C7/1063 , G11C7/20 , G11C11/406 , G11C11/40615 , G11C11/40618 , G11C11/4072
摘要： A semiconductor memory device, such as a DRAM, which needs to be refreshed for retaining data, is provided with a storing portion for storing data therein, and a busy signal outputting portion outputting a busy signal during the refresh operation.
摘要翻译：为了保存数据而需要刷新的诸如DRAM的半导体存储器件提供有用于存储数据的存储部分和在刷新操作期间输出忙信号的忙信号输出部分。

76. 发明授权

US06498522B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US06498522B2
公开(公告)日：2002-12-24
申请号：US09833045
申请日：2001-04-12
申请人： Hitoshi Ikeda , Shinya Fujioka , Yasuharu Sato , Yasurou Matsuzaki
发明人： Hitoshi Ikeda , Shinya Fujioka , Yasuharu Sato , Yasurou Matsuzaki
IPC分类号： H03L700
CPC分类号： G11C7/1084 , G11C7/1072 , G11C7/1078 , G11C7/1093 , G11C7/22 , G11C7/222
摘要： The invention relates to a clock synchronous type semiconductor device that accepts an input signal inputted from the exterior in synchronization with a clock signal. The semiconductor device according to the invention includes an input signal receiving unit that receives an input signal inputted from the exterior, where the receiving is done in synchronization with a clock signal; a clock timing selecting unit for outputting a clock selecting signal; and a clock generating unit that, in response to receiving a clock selecting signal and an external clock signal, generates a clock signal at a predetermined timing which corresponds to a signal level of the clock selecting signal, and outputs the clock signal to the input signal receiving unit, wherein it is possible to securely accept an input signal regardless of the frequency of the external clock signal.
摘要翻译：本发明涉及一种时钟同步型半导体器件，其与时钟信号同步地接收从外部输入的输入信号。根据本发明的半导体器件包括输入信号接收单元，其接收从外部输入的输入信号，其中接收与时钟信号同步完成; 时钟定时选择单元，用于输出时钟选择信号; 以及时钟发生单元，响应于接收到时钟选择信号和外部时钟信号，在与时钟选择信号的信号电平相对应的预定定时产生时钟信号，并将时钟信号输出到输入信号接收单元，其中无论外部时钟信号的频率如何，都可以安全地接受输入信号。

77. 发明授权

US06452453B1 Constant-current generator, differential amplifier, and semiconductor integrated circuit 有权
标题翻译：恒流发电机，差分放大器和半导体集成电路
公开(公告)号：US06452453B1
公开(公告)日：2002-09-17
申请号：US09562289
申请日：2000-05-01
申请人： Shinya Fujioka , Akihiro Funyu
发明人： Shinya Fujioka , Akihiro Funyu
IPC分类号： H03F304
CPC分类号： H03F1/301 , H03F2203/45456 , H03F2203/45508
摘要： The constant-current generator comprises a bias transistor whose drain and gate are connected to each other, and an outputting transistor. The threshold voltage of the outputting transistor is smaller than that of the bias transistor. The outputting transistor has the same source voltage and the same gate voltage as those of the bias transistor. Therefore, the gate-to-source voltages of the outputting transistor and the bias transistor are always kept equal. On the other hand, the drain-to-source current of the outputting transistor becomes larger than that of the bias transistor in accordance with the difference between the threshold voltages of the outputting transistor and the bias transistor. Accordingly, the outputting transistor can output a stable drain-to-source current even when the drain voltage of the bias transistor has shifted to lower the gate-to-source voltage thereof.
摘要翻译：恒流发生器包括漏极和栅极彼此连接的偏置晶体管和输出晶体管。输出晶体管的阈值电压小于偏置晶体管的阈值电压。输出晶体管具有与偏置晶体管相同的源极电压和相同的栅极电压。因此，输出晶体管和偏置晶体管的栅极 - 源极电压总是保持相等。另一方面，根据输出晶体管和偏置晶体管的阈值电压之差，输出晶体管的漏极 - 源极电流变得大于偏置晶体管的漏极 - 源极电流。因此，即使当偏置晶体管的漏极电压已经偏移以降低其栅极至源极电压时，输出晶体管也可以输出稳定的漏极 - 源极电流。

78. 发明授权

US06373764B1 Semiconductor memory device allowing static-charge tolerance test between bit lines 有权
公开(公告)号：US06373764B1
公开(公告)日：2002-04-16
申请号：US09790573
申请日：2001-02-23
申请人： Shinya Fujioka
发明人： Shinya Fujioka
IPC分类号： G11C700
摘要： A semiconductor memory device includes bit lines which transfer data of memory cells, a plurality of first sense amplifier circuits connected to odd-number lines of the bit lines, a plurality of second sense amplifier circuits connected to even-number lines of the bit lines, and a clamp-voltage generation circuit which supplies a first clamp voltage to the first sense amplifier circuits, and supplies a second clamp voltage to the second sense amplifier circuits, whereby during test operation, the odd-number lines are clamped to the first clamp voltage, and the even-number lines are clamped to the second clamp voltage.

79. 发明授权

US06341100B1 Semiconductor integrated circuit having circuit for writing data to memory cell 有权
标题翻译：具有用于将数据写入存储单元的电路的半导体集成电路
公开(公告)号：US06341100B1
公开(公告)日：2002-01-22
申请号：US09575363
申请日：2000-05-22
申请人： Shinya Fujioka
发明人： Shinya Fujioka
IPC分类号： G11C800
CPC分类号： G11C11/4076 , G11C7/1006 , G11C7/1072 , G11C11/4096 , G11C2207/229
摘要： A controlling signal generating unit generates a bit line controlling signal, a word line signal, a sense amplifier activating signal, and a column line signal. The bit line controlling signal activates a resetting circuit which resets a bit line. The word line signal controls the connection between a memory cell and the bit line which transmits data to the memory cell. The sense amplifier activating signal activates a sense amplifier which amplifies data transmitted to the bit line. The column line signal activates a column switch which transmits data to the bit line. The controlling signal generating unit activates predetermined signal(s) among the word line signal, the sense amplifier activating signal, the bit line controlling signal, and the column line signal at the start of a write operation. The controlling signal generating unit activates the remaining signal(s) after the acceptance of write data. Since the predetermined signal(s) is/are activated without the acceptance of write data, it is possible to make the activating timing of the remaining signal(s) earlier. This consequently reduces the time necessary for a write operation.
摘要翻译：控制信号产生单元产生位线控制信号，字线信号，读出放大器激活信号和列线信号。位线控制信号激活复位位线的复位电路。字线信号控制存储单元与向存储单元发送数据的位线之间的连接。读出放大器激活信号激活读出放大器，其放大发送到位线的数据。列线信号激活向位线发送数据的列开关。控制信号产生单元在写入操作开始时激活字线信号，读出放大器激活信号，位线控制信号和列线信号之间的预定信号。控制信号产生单元在接受写入数据之后激活剩余的信号。由于在不接受写入数据的情况下激活预定信号，所以可以使剩余信号的激活定时更早。这因此减少了写操作所需的时间。

80. 发明授权

US06301173B2 Memory device with faster reset operation 有权
标题翻译：具有更快复位操作的存储器件
公开(公告)号：US06301173B2
公开(公告)日：2001-10-09
申请号：US09307758
申请日：1999-05-10
申请人： Shinya Fujioka , Yasuharu Sato
发明人： Shinya Fujioka , Yasuharu Sato
IPC分类号： G11C700
CPC分类号： G11C7/065 , G11C7/12
摘要： The present invention is a memory circuit having a plurality of word lines, a plurality of bit line pairs, and memory cells disposed at the cross-position thereof. The memory comprises: a sense amplifier which is shared by the first bit line pair and the second bit line pair disposed in the column direction and amplifies a voltage of the bit line pairs; a first and a second bit line transfer gates which are disposed between the sense amplifier and the first and second bit line pairs, and connects the bit line pair at the selected memory cell side to the sense amplifier; a bit line clamper, which is disposed between the first and second bit line transfer gates, is shared by the first bit line pair and the second bit line pair, and supplies the precharge level to the bit line pairs; and a bit line short circuit, which is disposed at the first and the second bit line pairs respectively and shorts the bit line pairs. According to the above structure, the reset operation involving a bit line short operation can be executed at high-speed, since the bit line short circuit is disposed for each bit line pair. Also area efficiency can be improved since the bit line clamper circuit is shared by the first and the second bit line pairs.
摘要翻译：本发明是具有多个字线，多个位线对和设置在其交叉位置的存储单元的存储电路。存储器包括：读出放大器，由第一位线对和位于列方向上的第二位线对共享，并放大位线对的电压; 第一位线传输门和第二位线传输门，其布置在读出放大器与第一和第二位线对之间，并将所选存储单元侧的位线对连接到读出放大器; 位于第一和第二位线传输门之间的位线钳位器由第一位线对和第二位线对共用，并将预充电电平提供给位线对; 以及分别布置在第一和第二位线对上并使位线对短路的位线短路。根据上述结构，由于对每个位线对设置位线短路，所以可以高速执行涉及位线短路操作的复位动作。由于位线钳位电路由第一位线对和第二位线对共享，所以可以提高面积效率。

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