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71. 发明授权

US07177366B1 Automatic phase alignment for high-bandwidth cartesian-feedback power amplifiers 有权
标题翻译：高带宽笛卡尔反馈功率放大器的自动相位对准
公开(公告)号：US07177366B1
公开(公告)日：2007-02-13
申请号：US09947624
申请日：2001-09-06
申请人： Joel L. Dawson , Thomas H. Lee
发明人： Joel L. Dawson , Thomas H. Lee
IPC分类号： H04I27/00
CPC分类号： H04L27/368 , H03F1/3247 , H03F1/3294 , H03F3/24 , H03F2200/336
摘要： In an automatic phase alignment circuit for a Cartesian feedback amplifier, the phase error is regularly monitored. In various implementations, this approach is used to provide true and continuous phase alignment. Based on a relationship between the up-converted and down-converted signals, another implementation of the invention provides phase-alignment for quadrature-phase components of a baseband signal by arithmetically combining the quadrature-phase components and the feedback components continuously and, in response, continuously phase-adjusting signals in the feed-forward signal path. Another aspect of the present invention is directed to an approach for calculating phase error for that is caused by DC-offset interference which, in turn, manifest at the outputs of many analog functional blocks.
摘要翻译：在用于笛卡尔反馈放大器的自动相位对准电路中，定期监视相位误差。在各种实施方案中，该方法用于提供真实和连续的相位对准。基于上转换信号和下变频信号之间的关系，本发明的另一实现方式通过连续地对正交相位分量和反馈分量进行算术组合来提供基带信号的正交相位分量的相位对准，作为响应，在前馈信号路径中连续地相位调整信号。本发明的另一方面涉及一种用于计算由DC偏移干扰引起的相位误差的方法，其反过来表现为许多模拟功能块的输出。

72. 发明授权

US06881994B2 Monolithic three dimensional array of charge storage devices containing a planarized surface 有权
标题翻译：包含平坦化表面的电荷存储装置的单片三维阵列
公开(公告)号：US06881994B2
公开(公告)日：2005-04-19
申请号：US09927648
申请日：2001-08-13
申请人： Thomas H. Lee , Vivek Subramanian , James M. Cleeves , Andrew J. Walker , Christopher J. Petti , Igor G. Kouznetzov , Mark G. Johnson , Paul Michael Farmwald , Brad Herner
发明人： Thomas H. Lee , Vivek Subramanian , James M. Cleeves , Andrew J. Walker , Christopher J. Petti , Igor G. Kouznetzov , Mark G. Johnson , Paul Michael Farmwald , Brad Herner
IPC分类号： H01L21/20 , H01L21/336 , H01L21/822 , H01L21/8246 , H01L21/8247 , H01L27/06 , H01L27/10 , H01L27/112 , H01L27/12 , H01L29/423 , H01L29/786 , H01L29/788 , H01L29/792 , H01L29/861 , H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119 , H01L21/8242
CPC分类号： H01L27/11582 , G11C16/0466 , G11C16/10 , G11C16/14 , G11C16/26 , G11C16/3427 , G11C2211/5612 , H01L21/31053 , H01L21/76819 , H01L21/8221 , H01L23/528 , H01L23/5329 , H01L27/0688 , H01L27/112 , H01L27/11286 , H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11551 , H01L27/11556 , H01L27/11558 , H01L27/11565 , H01L27/11568 , H01L27/11573 , H01L27/11578 , H01L27/1158 , H01L27/12 , H01L27/1203 , H01L29/0626 , H01L29/0661 , H01L29/16 , H01L29/1604 , H01L29/42324 , H01L29/42332 , H01L29/42364 , H01L29/511 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66825 , H01L29/66833 , H01L29/7391 , H01L29/78642 , H01L29/7881 , H01L29/7889 , H01L29/792 , H01L29/7926 , H01L29/861 , H01L29/8616
摘要： There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.
摘要翻译：提供了一种包括多个器件级的电荷存储器件的单片三维阵列，其中通过化学机械抛光将两个连续的器件级之间的至少一个表面平坦化。

73. 发明授权

US06867992B2 Modular memory device 有权
标题翻译：模块化存储设备
公开(公告)号：US06867992B2
公开(公告)日：2005-03-15
申请号：US10342122
申请日：2003-01-13
申请人： J. James Tringali , P. Michael Farmwald , Thomas H. Lee , Mark G. Johnson , Derek J. Bosch
发明人： J. James Tringali , P. Michael Farmwald , Thomas H. Lee , Mark G. Johnson , Derek J. Bosch
IPC分类号： G06K19/077 , G11C5/00 , G11C5/02 , G11C5/06
CPC分类号： G11C5/025 , G11C5/063
摘要： In one embodiment, a modular memory device is presented comprising a substrate, a memory array fabricated above the substrate, and first and second circuitry fabricated on the substrate and under the memory array. The first and second circuitry allow the modular memory device to interface with first and second varieties of host devices, respectively. In another embodiment, a modular memory device is presented comprising a substrate, a memory array fabricated above the substrate, memory array support circuitry fabricated on the substrate, and logic circuitry fabricated on the substrate and under the memory array.
摘要翻译：在一个实施例中，呈现模块化存储器件，其包括衬底，在衬底上方制造的存储器阵列，以及在衬底上和存储器阵列下方制造的第一和第二电路。第一和第二电路允许模块化存储器件分别与第一和第二种类型的主机设备接口。在另一个实施例中，提出了一种模块化存储器件，其包括衬底，在衬底上方制造的存储器阵列，在衬底上制造的存储器阵列支持电路，以及在衬底上以及在存储器阵列之下的逻辑电路。

74. 发明授权

US06539072B1 Delay locked loop circuitry for clock delay adjustment 有权
标题翻译：延迟锁定环电路，用于时钟延迟调整
公开(公告)号：US06539072B1
公开(公告)日：2003-03-25
申请号：US09524402
申请日：2000-03-13
申请人： Kevin S. Donnelly , Pak Shing Chau , Mark A. Horowitz , Thomas H. Lee , Mark G. Johnson , Benedict C. Lau , Leung Yu , Bruno W. Garlepp , Yiu-Fai Chan , Jun Kim , Chanh Vi Tran , Donald C. Stark , Nhat M. Nguyen
发明人： Kevin S. Donnelly , Pak Shing Chau , Mark A. Horowitz , Thomas H. Lee , Mark G. Johnson , Benedict C. Lau , Leung Yu , Bruno W. Garlepp , Yiu-Fai Chan , Jun Kim , Chanh Vi Tran , Donald C. Stark , Nhat M. Nguyen
IPC分类号： H04L700
CPC分类号： H03K5/133 , G06F1/10 , G11C7/22 , G11C7/222 , H03K5/2481 , H03K2005/00026 , H03K2005/00032 , H03K2005/00052 , H03K2005/00208 , H03L7/07 , H03L7/0805 , H03L7/0812 , H03L7/0814 , H04L7/0008 , H04L7/0025 , H04L7/0037
摘要： Delay locked loop circuitry for generating a predetermined phase relationship between a pair of clocks. A first delay-locked loop includes a delay elements arranged in a chain, the chain receiving an input clock and generating, from each delay element, a set of phase vectors, each shifted a unit delay from the adjacent vector. The first delay-locked loop adjusts the unit delays in the delay chain using a delay adjustment signal so that the phase vectors span a predetermined phase shift of the input clock. A second delay-locked loop selects, from the first delay-locked loop, a pair of phase vectors which brackets the phase of an input clock. A phase interpolator receives the selected pair of vectors and generates an output clock and a delayed output clock, the amount of the delay being controlled by the delay adjustment signal of the first delay-locked loop circuitry. A phase detector compares the delayed output clock with the input clock and adjusts the phase interpolator, based on the phase comparison, so that the phase of the delayed output clock is in phase with the input clock. As a result, there is a predetermined phase relationship between the output clock and the input clock, the phase relationship being the amount of delay between the output clock and the delayed output clock. Different phase relationships between the input and output clock are possible depending on the number of unit delays used in the path of the delayed output clock or the output clock.
摘要翻译：延迟锁定环电路，用于在一对时钟之间产生预定的相位关系。第一延迟锁定环包括布置在链中的延迟元件，所述链接收输入时钟，并且从每个延迟元件产生一组相位矢量，每组相移向量从相邻矢量移位单位延迟。第一延迟锁定环路使用延迟调整信号来调整延迟链中的单元延迟，使得相位矢量跨越输入时钟的预定相移。第二延迟锁定环路从第一延迟锁定环路中选择一对相对于输入时钟相位的相位矢量。相位插值器接收所选择的一对矢量，并产生输出时钟和延迟输出时钟，延迟量由第一延迟锁定环电路的延迟调整信号控制。相位检测器将延迟的输出时钟与输入时钟进行比较，并根据相位比较调节相位内插器，使得延迟输出时钟的相位与输入时钟同相。结果，在输出时钟和输入时钟之间存在预定的相位关系，相位关系是输出时钟和延迟的输出时钟之间的延迟量。根据在延迟输出时钟或输出时钟的路径中使用的单位延迟数，输入和输出时钟之间的不同相位关系是可能的。

75. 发明授权

US06369626B1 Low pass filter for a delay locked loop circuit 失效
标题翻译：用于延迟锁定环路的低通滤波器
公开(公告)号：US06369626B1
公开(公告)日：2002-04-09
申请号：US08966721
申请日：1997-11-10
申请人： Kevin S. Donnelly , Andy Chan , Thomas H. Lee , Wayne Richardson , Jared L. Zerbe , Chaofeng Huang , Clemenz L. Portmann , Grace Tsang
发明人： Kevin S. Donnelly , Andy Chan , Thomas H. Lee , Wayne Richardson , Jared L. Zerbe , Chaofeng Huang , Clemenz L. Portmann , Grace Tsang
IPC分类号： H03L300
CPC分类号： H03K5/1565 , H03L7/0896 , H03L7/093
摘要： A low pass filter having a first mode of operation and a second mode of operation. The low pass filter includes a charging circuit, a capacitor circuit, and low power circuitry coupled to the capacitor circuit and the charging circuit. The capacitor circuit stores a first differential voltage when the low pass filter is operating in the first mode of operation. The capacitor circuit stores a second differential voltage when the low pass filter is operating in the second mode of operation. The second differential voltage is substantially equal to the first differential voltage. The charging circuit may include a charging current source coupled to a current steering circuit. The low pass filter may further include a load circuit coupled to the current steering circuit and the low power circuitry. The low pass filter may be used in a delay locked loop circuit or a phase locked loop circuit.
摘要翻译：具有第一操作模式和第二操作模式的低通滤波器。低通滤波器包括充电电路，电容器电路和耦合到电容器电路和充电电路的低功率电路。当低通滤波器在第一操作模式下操作时，电容器电路存储第一差分电压。当低通滤波器在第二操作模式下工作时，电容器电路存储第二差分电压。第二差分电压基本上等于第一差分电压。充电电路可以包括耦合到电流转向电路的充电电流源。低通滤波器还可以包括耦合到电流转向电路和低功率电路的负载电路。低通滤波器可用于延迟锁定环电路或锁相环电路中。

76. 发明授权

US06340900B1 Phase detector with minimized phase detection error 失效
公开(公告)号：US06340900B1
公开(公告)日：2002-01-22
申请号：US08582045
申请日：1996-01-02
申请人： Kevin S. Donnelly , Thomas H. Lee , Tsyr-Chyang Ho
发明人： Kevin S. Donnelly , Thomas H. Lee , Tsyr-Chyang Ho
IPC分类号： H03K526
CPC分类号： G01R25/00 , H03L7/085
摘要： A phase detector is described that includes a load circuit that presents both a high differential impedance and a low common mode impedance. The load circuit is coupled to (1) a power supply and (2) a first node and a second node. The first and second nodes form an output of the phase detector. A capacitive circuit has (1) a first capacitor coupled to the first node and ground and (2) a second capacitor coupled to the second node and ground. A first circuit is coupled to the first and second nodes for detecting a phase difference between a first signal and a second signal. A second circuit is coupled to the first and second nodes for detecting the phase difference between the first and second signals and for minimizing phase detection error of the first circuit such that the phase difference between the first and second signals can be detected with minimized phase detection error. Each of the first and second circuits receives the first and second signals and a reference signal. The second circuit is cross-coupled to the first circuit such that an error current generated by the second circuit cancels that generated by the first circuit such that the phase detector detects the phase difference between the first and second signals with minimized phase detection error.

77. 发明授权

US06269277B1 System and method for designing integrated circuits 失效
标题翻译：集成电路设计系统及方法
公开(公告)号：US06269277B1
公开(公告)日：2001-07-31
申请号：US09123129
申请日：1998-07-27
申请人： Maria del Mar Hershenson , Stephen P. Boyd , Thomas H. Lee
发明人： Maria del Mar Hershenson , Stephen P. Boyd , Thomas H. Lee
IPC分类号： G06F1900
CPC分类号： G06F17/5063
摘要： A system for designing and optimizing integrated circuits. Design objectives and constraints are described as posynomial functions of the design parameters. The circuit design problem is then expressed as a special form of optimization problem called geometric programming, to which very efficient global optimization methods are applied. The present invention can thereby efficiently determine globally optimal circuit designs, or globally optimal trade-offs among competing performance measures such as, for example for an operational amplifier (op-amp), power, open-loop gain, and bandwidth. The present invention therefore yields automated synthesis of globally optimal circuit designs for a given circuit topology library, directly from specifications.
摘要翻译：集成电路设计和优化系统。设计目标和约束被描述为设计参数的函数式函数。然后将电路设计问题表示为称为几何规划的特殊形式的优化问题，其中应用了非常有效的全局优化方法。因此，本发明可以有效地确定全球最佳电路设计，或者在诸如运算放大器（运算放大器），功率，开环增益和带宽等竞争性能测量之间的全局最佳权衡。因此，本发明可以直接从规范产生给定电路拓扑库的全局最佳电路设计的自动合成。

78. 发明授权

US06185122B2 Vertically stacked field programmable nonvolatile memory and method of fabrication 有权
标题翻译：垂直堆叠现场可编程非易失性存储器和制造方法
公开(公告)号：US06185122B2
公开(公告)日：2001-02-06
申请号：US09469658
申请日：1999-12-22
申请人： Mark G. Johnson , Thomas H. Lee , Vivek Subramanian , P. Michael Farmwald , James M. Cleeves
发明人： Mark G. Johnson , Thomas H. Lee , Vivek Subramanian , P. Michael Farmwald , James M. Cleeves
IPC分类号： G11C1700
CPC分类号： H01L27/1021 , G11C11/5678 , G11C11/5692 , G11C13/003 , G11C17/16 , G11C2213/71 , G11C2213/76
摘要： A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.
摘要翻译：公开了一种非常高密度的现场可编程存储器。阵列垂直地形成在衬底上方，使用几层，其各层包括垂直制造的存储单元。 N级阵列中的单元可以形成N + 1掩蔽步骤以及接触所需的掩蔽步骤。自动对准技术的最大限度地使光刻限制最小化。在一个实施例中，外围电路形成在硅衬底中，并且在衬底上方制造N电平阵列。

79. 发明授权

US6157244A Power supply independent temperature sensor 有权
标题翻译：电源独立温度传感器
公开(公告)号：US6157244A
公开(公告)日：2000-12-05
申请号：US170335
申请日：1998-10-13
申请人： Thomas H. Lee , Mark G. Johnson , John C. Holst
发明人： Thomas H. Lee , Mark G. Johnson , John C. Holst
IPC分类号： G01K7/01 , G05F1/10
CPC分类号： G01K7/01
摘要： A temperature sensor is fabricated in an integrated circuit in combination with another device such as a microprocessor using a fabrication technology that is suitable for fabricating the device. Operation of the temperature sensor is based on the bandgap physics of semiconductors using a bandgap reference circuit and an amplifier that generate two measurement voltages, a voltage that is temperature-dependent and a voltage that is temperature-independent. The temperature sensor includes a bandgap power supply circuit that supplies a power supply voltage that is very stable to drive the temperature sensor so that the temperature sensor generates an output signal that is essentially independent of the power supply voltage.
摘要翻译：温度传感器与集成电路结合使用适合于制造该器件的制造技术的另一个器件（如微处理器）制造。温度传感器的操作基于使用带隙参考电路的半导体带隙物理学和产生两个测量电压的放大器，其是依赖于温度的电压和与温度无关的电压。温度传感器包括带隙电源电路，其提供非常稳定的驱动温度传感器的电源电压，使得温度传感器产生基本上与电源电压无关的输出信号。

80. 发明授权

US6125157A Delay-locked loop circuitry for clock delay adjustment 失效
标题翻译：用于时钟延迟调整的延迟锁定环路
公开(公告)号：US6125157A
公开(公告)日：2000-09-26
申请号：US795657
申请日：1997-02-06
申请人： Kevin S. Donnelly , Pak Shing Chau , Mark A. Horowitz , Thomas H. Lee , Mark G. Johnson , Benedict C. Lau , Leung Yu , Bruno W. Garlepp , Yiu-Fai Chan , Jun Kim , Chanh Vi Tran , Donald C. Stark
发明人： Kevin S. Donnelly , Pak Shing Chau , Mark A. Horowitz , Thomas H. Lee , Mark G. Johnson , Benedict C. Lau , Leung Yu , Bruno W. Garlepp , Yiu-Fai Chan , Jun Kim , Chanh Vi Tran , Donald C. Stark
IPC分类号： G06F1/10 , G11C7/22 , H03K5/00 , H03K5/13 , H03K5/24 , H03L7/07 , H03L7/081 , H04L7/00
CPC分类号： H03K5/133 , G06F1/10 , G11C7/22 , G11C7/222 , H03K5/2481 , H03L7/07 , H03L7/0805 , H03L7/0812 , H03L7/0814 , H04L7/0037 , H03K2005/00026 , H03K2005/00032 , H03K2005/00052 , H03K2005/00208 , H04L7/0008 , H04L7/0025
摘要： Delay-locked loop circuitry for generating a predetermined phase relationship between a pair of clocks. A first delay-locked loop includes a set of delay-producing elements arranged in a chain, the chain receiving an input clock and generating, from each delay element, a set of phase vectors, each shifted a unit delay from the adjacent vector. The first delay-locked loop adjusts the unit delays in the delay chain using a delay adjustment signal so that the phase vectors span a predetermined phase shift of the input clock. A second delay-locked loop selects, from the first delay-locked loop, a pair of phase vectors which brackets the phase of an input clock. A phase interpolator receives the selected pair of vectors and generates an output clock and a delayed output clock, the amount of the delay being controlled by the delay adjustment signal of the first delay-locked loop circuitry. A phase detector compares the delayed output clock with the input clock and adjusts the phase interpolator, based on the phase comparison, so that the phase of the delayed output clock is in phase with the input clock. As a result, there is a predetermined phase relationship between the output clock and the input clock, the phase relationship being the amount of delay between the output clock and the delayed output clock. Different phase relationships between the input and output clock are possible depending on the number of unit delays used.
摘要翻译：延迟锁定环路电路，用于在一对时钟之间产生预定的相位关系。第一延迟锁定环包括布置在链中的一组延迟产生元件，所述链接收输入时钟，并且从每个延迟元件产生一组相位矢量，每组相移向量从相邻矢量移位单位延迟。第一延迟锁定环路使用延迟调整信号来调整延迟链中的单元延迟，使得相位矢量跨越输入时钟的预定相移。第二延迟锁定环路从第一延迟锁定环路中选择一对相对于输入时钟相位的相位矢量。相位插值器接收所选择的一对矢量，并产生输出时钟和延迟输出时钟，延迟量由第一延迟锁定环电路的延迟调整信号控制。相位检测器将延迟的输出时钟与输入时钟进行比较，并根据相位比较调节相位内插器，使得延迟输出时钟的相位与输入时钟同相。结果，在输出时钟和输入时钟之间存在预定的相位关系，相位关系是输出时钟和延迟的输出时钟之间的延迟量。根据使用的单位延迟数，输入和输出时钟之间的不同相位关系是可能的。

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