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71. 发明专利

JPH02181920A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH02181920A
公开(公告)日：1990-07-16
申请号：JP254789
申请日：1989-01-09
申请人： HITACHI LTD
发明人： SAGAWA MASAKAZU , ASANO ISAMU
IPC分类号： H01L21/3205 , H01L21/28 , H01L21/768 , H01L23/522
摘要： PURPOSE:To prevent a constituent material from being diffused mutually between conductive regions formed at the upper layer and the lower layer by installing the following in an opening part formed in an interlayer insulating film: a barrier layer used to prevent the constituent material from being diffused mutually between an electrode which electrically connects the conductive regions at the upper layer and the lower layer and the conductive region in the lower layer. CONSTITUTION:A lower-layer TiSi2 film is nitrified at the bottom of contact holes 17A to 17F in required parts of an insulating film 17; a titanium nitride film 23 is formed. An electrode 24 composed of WSi2 is filled on it so as to be a level nearly equal to the insulating film 17. A diffusion coefficient of the film 23 is small; a constituent material for the electrode 24 adjacent to the film 23 or for semiconductor regions 8, 26, 27, 29, 30 is provided with a short distance which can be moved inside the film 23; accordingly, the film 23 functions as a barrier layer which prevents the constituent material from being diffused mutually between the electrode 24 and a semiconductor region formed at its lower layer. Accordingly, it is possible to prevent an increase in a resistance value immediately close to a junction part between the electrode 24 and the semiconductor region formed at its lower layer; it is possible to prevent W in the electrode 24 from being diffused into the semiconductor region; it is possible to prevent a leakage current amount in the semiconductor region from being increased undesirably.

72. 发明专利

JPH0276233A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPH0276233A
公开(公告)日：1990-03-15
申请号：JP22799588
申请日：1988-09-12
申请人： HITACHI LTD
发明人： ASANO ISAMU , AOKI HIDEO
IPC分类号： H01L21/3205 , H01L21/768 , H01L23/522
摘要： PURPOSE:To prevent a defective step coverage and disconnection due to electromigration by a method wherein wiring material such as tungsten is accumulated in a wiring layer forming groove formed on a planar interlayer insulation film and a wiring layer substantially on the same plane with the insulation film is formed. CONSTITUTION:Wiring layers 25A, 25B, 36A to 36C which are on the same plane with an insulation film 23 are formed in a groove formed on an oxide silicon insulation film 23 accumulated on a planar BPSG insulation layer 17, a wiring layer of a first layer and an interlayer insulation film 12 becoming planar. Wiring layers 42A to 42C are formed on the same plane with an insulation film 40 are formed on a groove formed on an oxide silicon insulation film 40 accumulated on a planar oxide silicon insulation film 38, a wiring layer of a second layer and an interlayer insulation film 34 becoming planar. As a result, since a wiring layer is formed in a groove formed beforehand on a planar insulation layer, pellet surfaces can be planarized. This makes it possible to prevent disconnection due to electromigration and defective step coverage resulting from irregularities of a wiring layer.

73. 发明专利

JPH0240913A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH0240913A
公开(公告)日：1990-02-09
申请号：JP19242088
申请日：1988-08-01
申请人： HITACHI LTD
发明人： OWADA NOBUO , ASANO ISAMU
IPC分类号： H01L21/3205 , H01L21/28 , H01L23/52
摘要： PURPOSE:To secure the conductivity of a contact hole and to realize the highly reliable contact hole by a method wherein, after silicide layers and a poly Si layer are etched back to flatten the aperture of the contact hole, the surface of the poly Si layer, whose aperture is exposed, is covered with a high melting point metal layer or its silicide layer. CONSTITUTION:An interlayer insulating film 7 is adhered on a field insulating film 5 adhered on a semiconductor substrate 1 through an oxide film 6. A first- layer wiring part 8 which is used as a bit line is formed by patterning on an upper layer of this film 7 and is connected to a high-concentration diffused layer 4 in the substrate 1 through a contact hole 9. This hole 9 is filled with a poly Si layer 11 and silicide layers 10a and 10b, the layer 11 consisting of a non-conductive material is covered with the layers 10a and 10b consisting of a conductive material and the wiring part 8 is formed into a two-Iayer structure, which consists of a barrier metal layer 8a consisting of TiN or the like and an AI layer 8b laminated on the surface of the layer 8a.

74. 发明专利

JPS6480045A WIRING BOARD AND MANUFACTURE THEREOF 失效
公开(公告)号：JPS6480045A
公开(公告)日：1989-03-24
申请号：JP23591287
申请日：1987-09-19
申请人： HITACHI LTD
发明人： ASANO ISAMU , HORIUCHI MITSUAKI , OGISHI HIDEJI
IPC分类号： H01L23/52 , H01L21/3205 , H01L21/768 , H01L21/822 , H01L27/04
摘要： PURPOSE:To decrease contact resistance between distributing wires at upper and lower layers, by providing a metal silicide film containing silicon at a connection between two different distributing wires; a first aluminum wiring where a migration-reduced element is added and a second aluminum wiring located at the upper layer of the first wiring. CONSTITUTION:Memory cells M, MISFETs Qn and Qp, and the like are prepared at p and n-types well regions 2 and 3 of a semiconductor substrate 1 and further, wiring 21 which is connected to semiconductor regions 9, 17, 18, and others and is extended on layer insulation films 19 is formed through connecting holes 19C. At wiring 21, barrier metal layers 21A consisting of MoSi2, aluminum films 21B where Cu, Si are added, and protective films of MoSix(0

75. 发明专利

JP2003338623A Method for manufacturing semiconductor integrated circuit device 审中-公开
标题翻译：制造半导体集成电路器件的方法
公开(公告)号：JP2003338623A
公开(公告)日：2003-11-28
申请号：JP2003114102
申请日：2003-04-18
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： TANABE YOSHIKAZU , ASANO ISAMU , YOSHIDA MAKOTO , YAMAMOTO NAOKI , SAITO MASAYOSHI , KASHU NOBUYOSHI
IPC分类号： H01L21/28 , H01L21/316 , H01L21/8242 , H01L27/108 , H01L29/423 , H01L29/49 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To prevent the oxidation of a metal film in light oxidation treatment after gate patterning in a gate working process using a polymetal, and to obtain controllability in reproducibility in oxidized film forming at the sidewall end of a gate and uniformity in the thickness of the oxidized film.
SOLUTION: A gate electrode material of polymetal structure deposited on a semiconductor wafer 1A, on which the oxidized gate film is formed, is patterned to form a gate electrode. Then, the main face of the semiconductor wafer 1A is oxidized selectively in an atomosphere which contains hydrogen and water vapor produced from hydrogen and oxygen by catalytic action, but does not contain a hydrogen radical practically, and the partitial pressure of the water vapor is lower than the partitial pressure of the hydrogen, and thereby, the profile of the sidewall end of the gate electrode is improved.
COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题：为了防止在使用聚金属的浇口加工工艺中的栅极图案化之后的光氧化处理中金属膜的氧化，并且获得在门的侧壁端部处的氧化膜形成中的再现性的可控性，以及氧化膜的厚度均匀。解决方案：沉积在其上形成有氧化栅极膜的半导体晶片1A上的多金属结构的栅电极材料被图案化以形成栅电极。然后，半导体晶片1A的主面在包含氢和氧的氢气和水蒸汽的气氛中被选择性氧化，通过催化作用，但实际上不含有氢原子，水蒸汽的初始压力较低比氢的初始压力高，从而提高了栅电极的侧壁端部的轮廓。版权所有（C）2004，JPO

76. 发明专利

JP2002076306A SEMICONDUCTOR INTEGRATED CIRCUIT AND ITS MANUFACTURING METHOD 失效
公开(公告)号：JP2002076306A
公开(公告)日：2002-03-15
申请号：JP2000262952
申请日：2000-08-31
申请人： HITACHI LTD
发明人： YUNOGAMI TAKASHI , ASANO ISAMU , IIJIMA SHINPEI , NAKAMURA YOSHITAKA , KUROKI KEIJI , IKEDA TAKENOBU , HIRATANI MASAHIKO , MATSUI YUICHI
IPC分类号： H01L21/8242 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To prevent peel-off at the interface between a platinum-family metal film for composing the lower electrode of a capacitive element and a silicon oxide film. SOLUTION: On the inner wall of a groove 29 opened in the silicon oxide film 24, the lower electrode 32 of the capacitive element C for accumulating information is formed. At the interface between an Ru film 32a for composing the lower electrode 32 and the silicon oxide film 24, the bonding layer composed by a TaN film 30 is interposed for preventing the interface between the Ru film 32a and silicon oxide film 24 from peeling off when the dielectric film 34 deposited on the lower electrode 32 is heat-treated. Also, the upper end section of the TaN film 30 for composing the bonding layer is recessed to the lower portion than the opening end section of the groove 29, and is completely covered with the Ru film 32a for composing the lower electrode 32.

77. 发明专利

JP2001267535A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JP2001267535A
公开(公告)日：2001-09-28
申请号：JP2000077779
申请日：2000-03-15
申请人： HITACHI LTD
发明人： IWASAKI TOMIO , OTA HIROYUKI , ASANO ISAMU , OJI YUZURU , NAKAMURA YOSHITAKA
IPC分类号： H01L27/108 , H01L21/8242 , H01L21/8246 , H01L27/105
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device having a capacitive element structure, which has a high reliability and high yield, and hardly causes a continuity failure. SOLUTION: The semiconductor device includes a capacitive element for storing information which is made by forming a conductive film, a first electrode in contact with the conductive film, high permittivity or ferroelectric oxide film in contact with the first electrode, and a second electrode in contact with the oxide film in this order on one principal plane of a silicon (Si) substrate. The conductive film contains an element which narrows a diffusion path of oxygen.

78. 发明专利

JP2001230385A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND ITS MANUFACTURING METHOD 失效
公开(公告)号：JP2001230385A
公开(公告)日：2001-08-24
申请号：JP2000041058
申请日：2000-02-18
申请人： HITACHI LTD
发明人： ASANO ISAMU , TSUCHIYA OSAMU
IPC分类号： H01L21/768 , H01L21/8234 , H01L21/8242 , H01L27/088 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To perform the connection between a bit line and a plug in self alignment in the direction of a word line. SOLUTION: A word line WL which functions as the gate electrode of the selective MISFET of a DRAM is made on the main surface of a semiconductor substrate, and then, plugs (a connecting plug BP and a plug made in a pattern SNCT) to be connected with the source and drain regions of the MISFET are made in the insulating film covering the word line WL. Next, an insulating film to cover the plug is made, and a bit line pattern and a tungsten film in reverse pattern are made on the insulating film. Using the tungsten film as a mask, a part of the insulating film is etched to form a wiring groove 18a. Next, a photo resist film 35, which has an opening on the connecting plug BP and is made rectilinearly in the direction of the word line WL, is made, and using the photoresist film 35 and the tungsten films as masks, the remainder of the insulating film is etched to expose the connecting plug BP.

79. 发明专利

JP2001217405A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND MANUFACTURING METHOD THEREOF 失效
公开(公告)号：JP2001217405A
公开(公告)日：2001-08-10
申请号：JP2000025226
申请日：2000-02-02
申请人： HITACHI LTD
发明人： NAKAMURA YOSHITAKA , ASANO ISAMU , YAMADA SATORU , NAGAI AKIRA , MATSUOKA HIDEYUKI , TAKAURA NORIKATSU
IPC分类号： H01L21/8242 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To form a plug of a low resistance in a self-alignment manner between fine bit lines, and to suppress increase in capacitance between bit lines. SOLUTION: A tangsten film and a silicon nitride film are deposited on a silicon oxide film, a bit line BL and a first layer wiring 32 comprising tangsten are formed by patterning the tangsten film and the silicon nitride film, and a cap insulating film 31 comprising the silicon nitride film is formed. Side walls of the bit line BL and the first layer wiring 32 are etched on the condition that the tangsten is processed on an isotropic etching. Further, the cap insulating film 31 is worked in such structure that the film 31 has some kind of hood against the bit line BL and the first layer wiring 32. A silicon oxide film is deposited, and a through hole 38 is formed on the silicon oxide film by selecting a condition that not the silicon nitride, but the silicon oxide is etched, followed by formation of a plug 39.

80. 发明专利

JP2001144267A SEMICONDUCTOR DEVICE AND METHOD OF FABRICATION 失效
公开(公告)号：JP2001144267A
公开(公告)日：2001-05-25
申请号：JP32100699
申请日：1999-11-11
申请人： HITACHI LTD
发明人： KUMAGAI YUKIHIRO , OTA HIROYUKI , ASANO ISAMU , OJI YUZURU , NAKAMURA YOSHITAKA
IPC分类号： H01L27/10 , H01L21/8242 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To realize a highly reliable semiconductor device in which generation of leak current is suppressed. SOLUTION: A storage capacitor 10 has such a cross-section as the side faces 11s of a lower electrode 11 approach each other from the lower end toward the upper end, with respect to the central axis of the storage capacitor 10 to form an upper end outer circumferential face 11c intersecting the upper face 11u and the side face 11s. The upper end outer circumferential face 11c and the upper face 11u make an angle of 120-150 deg. and the area ratio of the upper end outer circumferential face 11c to the upper face 11u is 0.2 or above. Consequently, a stress concentration field occurring in a capacitor insulation film 12 is relaxed and generation of leak current can be suppressed. Since the lower electrode 11 has a trapezoidal cross-section, the corner of the lower electrode 11 between the upper end outer circumferential part and the lower end outer circumferential part is made obtuse. Consequently, a stress concentration field in the capacitor insulation film 12 occurring at the upper end outer circumferential part and the lower end outer circumferential part is relaxed and generation of leak current can be suppressed furthermore.

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