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1. 发明专利

FR2555364A1 PROCEDE DE FABRICATION DE CONNEXIONS D'UN DISPOSITIF A CIRCUITS INTEGRES A SEMI-CONDUCTEURS COMPORTANT EN PARTICULIER UN MITSET 未知
公开(公告)号：FR2555364A1
公开(公告)日：1985-05-24
申请号：FR8414909
申请日：1984-09-28
申请人： HITACHI LTD , HITACHI LTD
发明人： TOMOZAWA AKIHIRO , AKIHIRO TOMOZAWA YOKU KAINO SHIGERU SHIMADA NOZOMI HORINO YOSHIAKI YOSHIURA OSAMU TSUCHIYA ET SHOZO , KAINO YOKU , SHIMADA SHIGERU , HORINO NOZOMI , YOSHIURA YOSHIAKI , TSUCHIYA OSAMU , HOSODA SHOZO
IPC分类号： H01L21/31 , H01L23/532 , H01L21/768 , H01L21/90 , H01L29/78
摘要： L'INVENTION CONCERNE UN PROCEDE DE FABRICATION D'UN DISPOSITIF A CIRCUITS INTEGRES A SEMI-CONDUCTEURS. CE PROCEDE CONSISTE A FORMER, SUR UN SUBSTRAT SEMI-CONDUCTEUR 1, UNE COUCHE CONDUCTRICE 9 FORMEE D'UNE COUCHE DE SILICIUM POLYCRISTALLIN 9A ET D'UNE COUCHE 9B SITUEE SUR LA PRECEDENTE ET CONTENANT UN METAL REFRACTAIRE A POINT DE FUSION ELEVE, A FORMER UNE PREMIERE PELLICULE ISOLANTE 11 RECOUVRANT LA COUCHE 9 ET D'UNE EPAISSEUR REDUISANT LA FORCE D'ECAILLEMENT DE LA COUCHE 9B A PARTIR DE LA COUCHE 9A, ET A FORMER UNE SECONDE PELLICULE ISOLANTE 12 FORMEE DE VERRE AU PHOSPHOSILICATE SUR LA PREMIERE PELLICULE ISOLANTE 11, CE VERRE AU PHOSPHOSILICATE ETANT CHAUFFE DE MANIERE A S'ECOULER LORSQU'IL A ETE DEPOSE. APPLICATION NOTAMMENT A LA FABRICATION DE MEMOIRES DYNAMIQUES A ACCES DIRECT.

2. 发明专利

GB2150349B PROCESS OF FABRICATING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 未知
公开(公告)号：GB2150349B
公开(公告)日：1987-07-08
申请号：GB8428534
申请日：1984-11-12
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： TOMOZAWA AKIHIRO , KAINO YOKU , SHIMADA SHIGERU , HORINO NOZOMI , YOSHIURA YOSHIAKI , TSUCHIYA OSAMU , HOSODA SHOZO
IPC分类号： H01L21/768 , H01L21/31 , H01L23/532 , H01L21/471
摘要： Herein disclosed is a process of fabricating a semiconductor integrated circuit device, in which there is formed between a conductive layer prepared by covering a polycrystalline silicon layer with either a layer containing a refractory metal of high melting point, i.e., a refractory metal layer or a silicide layer of the refractory metal and a first insulating film made of phosphosilicate glass flowing over said conductive layer containing the refractory metal, a second insulating film preventing the layer containing a refractory metal from peeling from the polycrystalline silicon layer by the glass flow. The second insulating film is formed by deposition to have a thickness not smaller than a predetermined value.

3. 发明专利

IT8423631D0 未知
公开(公告)号：IT8423631D0
公开(公告)日：1984-11-16
申请号：IT2363184
申请日：1984-11-16
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： TOMOZAWA AKIHIRO , KAINO YOKU , SHIMADA SHIGERU , HORINO NOZOMI , YOSHIURA YOSHIAKI , TSUCHIYA OSAMU , HOSODA SHOZO
IPC分类号： H01L21/768 , H01L21/31 , H01L23/532 , H01L

4. 发明专利

FR2555364B1 未知
公开(公告)号：FR2555364B1
公开(公告)日：1990-02-02
申请号：FR8414909
申请日：1984-09-28
申请人： HITACHI LTD
发明人： TOMOZAWA AKIHIRO , KAINO YOKU , SHIMADA SHIGERU , HORINO NOZOMI , YOSHIURA YOSHIAKI , TSUCHIYA OSAMU , HOSODA SHOZO
IPC分类号： H01L21/768 , H01L21/31 , H01L23/532 , H01L21/90 , H01L29/78
摘要： Herein disclosed is a process of fabricating a semiconductor integrated circuit device, in which there is formed between a conductive layer prepared by covering a polycrystalline silicon layer with either a layer containing a refractory metal of high melting point, i.e., a refractory metal layer or a silicide layer of the refractory metal and a first insulating film made of phosphosilicate glass flowing over said conductive layer containing the refractory metal, a second insulating film preventing the layer containing a refractory metal from peeling from the polycrystalline silicon layer by the glass flow. The second insulating film is formed by deposition to have a thickness not smaller than a predetermined value.

5. 发明专利

DE3442037A1 未知
公开(公告)号：DE3442037A1
公开(公告)日：1985-05-30
申请号：DE3442037
申请日：1984-11-16
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： TOMOZAWA AKIHIRO , KAINO YOKU , SHIMADA SHIGERU , HORINO NOZOMI , YOSHIURA YOSHIAKI , TSUCHIYA OSAMU , HOSODA SHOZO
IPC分类号： H01L21/768 , H01L21/31 , H01L23/532 , H01L21/82 , H01L21/90 , H01L21/94 , G11C11/24
摘要： Herein disclosed is a process of fabricating a semiconductor integrated circuit device, in which there is formed between a conductive layer prepared by covering a polycrystalline silicon layer with either a layer containing a refractory metal of high melting point, i.e., a refractory metal layer or a silicide layer of the refractory metal and a first insulating film made of phosphosilicate glass flowing over said conductive layer containing the refractory metal, a second insulating film preventing the layer containing a refractory metal from peeling from the polycrystalline silicon layer by the glass flow. The second insulating film is formed by deposition to have a thickness not smaller than a predetermined value.

6. 发明专利

AU6837296A Semiconductor non-volatile memory device and computer system using the same 未知
公开(公告)号：AU6837296A
公开(公告)日：1997-03-19
申请号：AU6837296
申请日：1996-08-29
申请人： HITACHI LTD
发明人： TANAKA TOSHIHIRO , KATO MASATAKA , TSUCHIYA OSAMU , NISHIMOTO TOSHIAKI
IPC分类号： G11C16/04 , G11C16/28 , G11C16/34 , G11C16/06
摘要： PCT No. PCT/JP96/02419 Sec. 371 Date Mar. 2, 1998 Sec. 102(e) Date Mar. 2, 1998 PCT Filed Aug. 29, 1996 PCT Pub. No. WO97/08707 PCT Pub. Date Mar. 6, 1997After decreasing the threshold voltages of a plurality of memory cells collectively or selectively, the presence or absence of any memory cell of which the threshold voltage has dropped below a predetermined voltage verified collectively for each of memory cell groups connected to word line (low-threshold value verification), and any memory cell of which the threshold voltage has excessively dropped is selectively written. Also, the well of each of memory cell is formed in the region of an element isolation layer for isolating it from the substrate of a memory apparatus, and a negative voltage is supplied to the memory well distributively with a positive voltage applied as a word line voltage, thus supplying them as erase operation voltages. The absolute value of the memory well voltage is set substantially equal to or lower than the word line voltage for the read operation. Sectors constituting each memory mat includes a sector (selected sector) selected for the erase operation with each word line thereof supplied with a positive voltage, a sector (non-selected sector) not selected for the erase operation with a word line voltage different from a memory well voltage, and further a sector (completely non-selected sector) not selected for the erase operation with a word line voltage equal to the voltage between a source and a drain of the memory cell.

7. 发明专利

IT1206469B 未知
公开(公告)号：IT1206469B
公开(公告)日：1989-04-27
申请号：IT2363184
申请日：1984-11-16
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： TOMOZAWA AKIHIRO , KAINO YOKU , SHIMADA SHIGERU , HORINO NOZOMI , YOSHIURA YOSHIAKI , TSUCHIYA OSAMU , HOSODA SHOZO
IPC分类号： H01L21/768 , H01L21/31 , H01L23/532 , H01L

8. 发明专利

HK84188A PROCESS OF FABRICATING A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 未知
公开(公告)号：HK84188A
公开(公告)日：1988-10-28
申请号：HK84188
申请日：1988-10-20
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： TOMOZAWA AKIHIRO , KAINO YOKU , SHIMADA SHIGERU , HORINO NOZOMI , YOSHIURA YOSHIAKI , TSUCHIYA OSAMU , HOSODA SHOZO
IPC分类号： H01L21/768 , H01L21/31 , H01L23/532 , H01L21/471
摘要： Herein disclosed is a process of fabricating a semiconductor integrated circuit device, in which there is formed between a conductive layer prepared by covering a polycrystalline silicon layer with either a layer containing a refractory metal of high melting point, i.e., a refractory metal layer or a silicide layer of the refractory metal and a first insulating film made of phosphosilicate glass flowing over said conductive layer containing the refractory metal, a second insulating film preventing the layer containing a refractory metal from peeling from the polycrystalline silicon layer by the glass flow. The second insulating film is formed by deposition to have a thickness not smaller than a predetermined value.

9. 发明专利

GB2150349A PROCESS OF FABRICATING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 未知
公开(公告)号：GB2150349A
公开(公告)日：1985-06-26
申请号：GB8428534
申请日：1984-11-12
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： TOMOZAWA AKIHIRO , KAINO YOKU , SHIMADA SHIGERU , HORINO NOZOMI , YOSHIURA YOSHIAKI , TSUCHIYA OSAMU , HOSODA SHOZO
IPC分类号： H01L21/768 , H01L21/31 , H01L23/532 , H01L21/471
摘要： Herein disclosed is a process of fabricating a semiconductor integrated circuit device, in which there is formed between a conductive layer prepared by covering a polycrystalline silicon layer with either a layer containing a refractory metal of high melting point, i.e., a refractory metal layer or a silicide layer of the refractory metal and a first insulating film made of phosphosilicate glass flowing over said conductive layer containing the refractory metal, a second insulating film preventing the layer containing a refractory metal from peeling from the polycrystalline silicon layer by the glass flow. The second insulating film is formed by deposition to have a thickness not smaller than a predetermined value.

10. 发明专利

JPH0281472A SEMICONDUCTOR MEMORY DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JPH0281472A
公开(公告)日：1990-03-22
申请号：JP23197988
申请日：1988-09-16
申请人： HITACHI LTD
发明人： SAGAWA MASAKAZU , OTSUKA FUMIO , SUGIURA JUN , TSUCHIYA OSAMU , SUWAUCHI NAOKATSU
IPC分类号： H01L21/76 , H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/10 , H01L27/108
摘要： PURPOSE:To reduce an area occupied by a gate electrode of a MISFET for memory- cell selection use and by a word line and to enhance an integration density of a semiconductor memory device by a method wherein the gate electrode (and the word line) are formed inside a narrow groove in self-alignment with the groove. CONSTITUTION:A memory cell 11 is constituted in an active island region 3 whose circumference has been surrounded by a narrow groove 2 and on its side wall; an extension direction of a complementary data line DL of this narrow groove 2 is set to a wide groove-width size WD and an extension direction of a word line WL is set to a narrow groove-width size WW. A MISFET QS for memory-cell selection use of the memory cell M is formed on a main face of the active island region 3 and at the upper part of a side wall of the active island region 3; it is constituted mainly of a semiconductor substrate 1, a gate insulating film 9, a gate electrode 10, one pair of n type semiconductor region and n type semiconductor region 11 as a source region and a drain region. The gate electrode 10 is formed in self-alignment with the active island region 3 and the narrow groove 2. Thereby, an area of the memory cell M can be reduced by an amount corresponding to an area occupied by the gate electrode 10 and to a mask-alignment margin area in a manufacturing process; an integration density of a DRAM can be enhanced.

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