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71. 发明申请

US20060246716A1 Semiconductor CMOS devices and methods with NMOS high-k dielectric formed prior to core PMOS dielectric formation 有权
标题翻译：半导体CMOS器件和方法，在核心PMOS电介质形成之前形成NMOS高k电介质
公开(公告)号：US20060246716A1
公开(公告)日：2006-11-02
申请号：US11118237
申请日：2005-04-29
申请人： Luigi Colombo , James Chambers , Mark Visokay
发明人： Luigi Colombo , James Chambers , Mark Visokay
IPC分类号： H01L21/4763
CPC分类号： H01L21/823857 , H01L27/11
摘要： The present invention facilitates semiconductor fabrication by providing methods of fabrication that selectively form high-k dielectric layers within NMOS regions. A first oxide layer is formed in core and I/O regions of a semiconductor device (506). The first oxide layer is removed (508) from the core region of the device. A high-k dielectric layer is formed (510) over the core and I/O regions. Then, the high-k dielectric layer is removed (512) from PMOS regions of the core and I/O regions. A second oxide layer is formed (516) within NMOS regions of the core and I/O regions and a nitridation process is performed (518) that nitrides the second oxide layer and the high-k dielectric layer.
摘要翻译：本发明通过提供在NMOS区内选择性地形成高k电介质层的制造方法来促进半导体制造。在半导体器件（506）的芯和I / O区域中形成第一氧化物层。第一氧化物层从器件的核心区域移除（508）。在芯和I / O区域上形成高k电介质层（510）。然后，从芯和I / O区域的PMOS区域去除高k电介质层（512）。在芯和I / O区域的NMOS区域内形成第二氧化物层（516），并且执行氮化处理（518），其氮化第二氧化物层和高k电介质层。

72. 发明申请

US20060244045A1 MOS Transistor Gates with Doped Silicide and Methods for Making the Same 审中-公开
标题翻译：具有掺杂硅化物的MOS晶体管门和制造相同的方法
公开(公告)号：US20060244045A1
公开(公告)日：2006-11-02
申请号：US11457203
申请日：2006-07-13
申请人： Mark Visokay , Luigi Colombo
发明人： Mark Visokay , Luigi Colombo
IPC分类号： H01L29/788
CPC分类号： H01L21/823842 , H01L21/823835
摘要： Semiconductor devices and fabrication methods are presented, in which transistor gate structures are created using doped metal silicide materials. Upper and lower metal silicides are formed above a gate dielectric, wherein the lower metal silicide is doped with n-type impurities for NMOS gates and with p-type impurities for PMOS gates, and wherein a silicon may, but need not be formed between the upper and lower metal silicides. The lower metal silicide can be deposited directly, or may be formed through reaction of deposited metal and poly-silicon, and the lower silicide can be doped by diffusion or implantation, before or after gate patterning.
摘要翻译：提出了半导体器件和制造方法，其中使用掺杂的金属硅化物材料制造晶体管栅极结构。上和下金属硅化物形成在栅极电介质上方，其中下部金属硅化物掺杂用于NMOS栅极的n型杂质和用于PMOS栅极的p型杂质，并且其中硅可以但不必形成在上下金属硅化物。可以直接沉积下金属硅化物，或者可以通过沉积的金属和多晶硅的反应形成下部金属硅化物，并且可以在栅极图案化之前或之后通过扩散或注入掺杂下硅化物。

73. 发明申请

US20060138556A1 Gate dielectric and method 有权
公开(公告)号：US20060138556A1
公开(公告)日：2006-06-29
申请号：US11339393
申请日：2006-01-25
申请人： Mark Visokay , Antonio Rotondaro , Luigi Colombo
发明人： Mark Visokay , Antonio Rotondaro , Luigi Colombo
IPC分类号： H01L29/94
CPC分类号： H01L21/823857 , H01L21/823842
摘要： A MOSFET structure with high-k gate dielectric layer and silicon or metal gates, amorphizing treatment of the high-k gate dielectric layer as with a plasma or ion implantation.

74. 发明申请

US20050269672A1 Gate stack and gate stack etch sequence for metal gate integration 有权
标题翻译：门堆叠和门堆叠蚀刻序列用于金属栅极集成
公开(公告)号：US20050269672A1
公开(公告)日：2005-12-08
申请号：US10860086
申请日：2004-06-02
申请人： Mark Visokay
发明人： Mark Visokay
IPC分类号： H01L21/28 , H01L21/3213 , H01L21/469 , H01L23/58
CPC分类号： H01L21/32139 , H01L21/28123
摘要： The present invention provides, in one embodiment, a process for fabricating a metal gate stack (200) for a semiconductor device (205). The process includes depositing a metal layer (210) over a gate dielectric layer (215) located over a semiconductor substrate (220). The process further includes forming a polysilicon layer (225) over the metal layer (210) and creating a protective layer (230) over the polysilicon layer (225). The process also includes placing an inorganic anti-reflective coating (235) over the protective layer (230). Other embodiments include a metal gate stack precursor structure (100) and a method of manufacturing an integrated circuit (300).
摘要翻译：本发明在一个实施例中提供一种用于制造用于半导体器件（205）的金属栅叠层（200）的工艺。该方法包括在位于半导体衬底（220）上方的栅极电介质层（215）上沉积金属层（210）。该工艺还包括在金属层（210）之上形成多晶硅层（225），并在多晶硅层（225）上形成保护层（230）。该方法还包括将无机抗反射涂层（235）放置在保护层（230）上。其他实施例包括金属栅极堆叠前体结构（100）和制造集成电路（300）的方法。

75. 发明申请

US20050136679A1 HYDROGEN FREE INTEGRATION OF HIGH-K GATE DIELECTRICS 有权
标题翻译：高K栅介质的氢自由集成
公开(公告)号：US20050136679A1
公开(公告)日：2005-06-23
申请号：US10745449
申请日：2003-12-22
申请人： Luigi Colombo , James Chambers , Mark Visokay
发明人： Luigi Colombo , James Chambers , Mark Visokay
IPC分类号： H01L21/28 , H01L21/311 , H01L21/314 , H01L21/316 , H01L21/318 , H01L21/336 , H01L29/51 , H01L21/302
CPC分类号： H01L21/28194 , H01L21/02164 , H01L21/0217 , H01L21/022 , H01L21/02271 , H01L21/02274 , H01L21/31111 , H01L21/3144 , H01L21/3145 , H01L21/31608 , H01L21/3185 , H01L29/517 , H01L29/518 , H01L29/665 , H01L29/6656 , H01L29/6659 , Y10S438/91 , Y10S438/954
摘要： The present invention pertains to forming a transistor in the absence of hydrogen, or in the presence of a significantly reduced amount of hydrogen. In this manner, a high-k material can be utilized to form a gate dielectric layer in the transistor and facilitate device scaling while mitigating defects that can be introduced into the high-k material by the presence of hydrogen and/or hydrogen containing compounds.
摘要翻译：本发明涉及在不存在氢的情况下形成晶体管，或者在显着减少量的氢的存在下。以这种方式，可以利用高k材料在晶体管中形成栅极电介质层，并且便于器件缩放，同时减轻可通过存在氢和/或含氢化合物引入高k材料的缺陷。

76. 发明申请

US20050136632A1 Implementation of split gate transistor technology with high-k gate dielectrics 有权
标题翻译：实现具有高k栅极电介质的分离栅晶体管技术
公开(公告)号：US20050136632A1
公开(公告)日：2005-06-23
申请号：US10738957
申请日：2003-12-17
申请人： Antonio Rotondaro , Mark Visokay , James Chambers , Luigi Colombo
发明人： Antonio Rotondaro , Mark Visokay , James Chambers , Luigi Colombo
IPC分类号： H01L21/28 , H01L21/3205 , H01L21/336 , H01L21/4763 , H01L29/51
CPC分类号： H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L29/513 , H01L29/518
摘要： Methods and systems are disclosed that facilitate semiconductor fabrication by fabricating transistor devices having gate dielectrics with selectable thicknesses in different regions of semiconductor devices. The thicknesses correspond to operating voltages of the corresponding transistor devices. Furthermore, the present invention also provides systems and methods that can fabricate the gate dielectrics with high-k dielectric material, which allows a thicker gate dielectric than conventional silicon dioxide.
摘要翻译：公开了通过制造具有在半导体器件的不同区域中具有可选厚度的栅极电介质的晶体管器件来促进半导体制造的方法和系统。厚度对应于相应的晶体管器件的工作电压。此外，本发明还提供了可以制造具有高k电介质材料的栅极电介质的系统和方法，其允许比常规二氧化硅更厚的栅极电介质。

77. 发明申请

US20050136605A1 MOS transistor gates with thin lower metal silicide and methods for making the same 有权
标题翻译：具有薄的下金属硅化物的MOS晶体管栅极及其制造方法
公开(公告)号：US20050136605A1
公开(公告)日：2005-06-23
申请号：US10745454
申请日：2003-12-22
申请人： Robert Murto , Luigi Colombo , Mark Visokay
发明人： Robert Murto , Luigi Colombo , Mark Visokay
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8238 , H01L29/49 , H01L21/3205 , H01L21/44
CPC分类号： H01L29/4975 , H01L21/28097 , H01L21/823835 , H01L29/665 , H01L29/6659
摘要： Methods are presented for fabricating transistor gate structures, wherein upper and lower metal suicides are formed above a gate dielectric. In one example, the lower silicide is formed by depositing a thin first silicon-containing material over the gate dielectric, which is implanted and then reacted with a first metal by annealing to form the lower silicide. A capping layer can be formed over the first metal prior to annealing, to prevent oxidation of the metal prior to silicidation, and a barrier layer can be formed over the lower silicide to prevent reaction with subsequently formed silicon material. In another example, the lower silicide is a multilayer silicide structure including a plurality of metal silicide sublayers.
摘要翻译：呈现用于制造晶体管栅极结构的方法，其中上和下金属硅化物形成在栅极电介质上方。在一个示例中，下硅化物通过在栅极电介质上沉积薄的第一含硅材料而形成，其被注入，然后通过退火与第一金属反应以形成下硅化物。在退火之前可以在第一金属上形成覆盖层，以防止在硅化物之前金属的氧化，并且可以在下硅化物上形成阻挡层以防止随后形成的硅材料的反应。在另一个实例中，下硅化物是包括多个金属硅化物层的多层硅化物结构。

78. 发明申请

US20050130442A1 Method for fabricating transistor gate structures and gate dielectrics thereof 有权
标题翻译：制造晶体管栅极结构及其栅极电介质的方法
公开(公告)号：US20050130442A1
公开(公告)日：2005-06-16
申请号：US10734708
申请日：2003-12-11
申请人： Mark Visokay , Luigi Colombo , James Chambers , Antonio Rotondaro , Haowen Bu
发明人： Mark Visokay , Luigi Colombo , James Chambers , Antonio Rotondaro , Haowen Bu
IPC分类号： H01L21/28 , H01L21/314 , H01L21/316 , H01L29/51 , H01L21/3205 , H01L21/31 , H01L21/469
CPC分类号： H01L21/28185 , H01L21/02148 , H01L21/02271 , H01L21/02332 , H01L21/02337 , H01L21/0234 , H01L21/28202 , H01L21/3144 , H01L21/3162 , H01L21/31637 , H01L21/31641 , H01L21/31645 , H01L21/31691 , H01L29/517 , H01L29/518
摘要： Methods are disclosed for treating deposited gate dielectric materials, in which the deposited dielectric is subjected to one or more non-oxidizing anneals to densify the material, one or more oxidizing anneals to mitigate material defects, and to a nitridation process to introduce nitrogen into the gate dielectric. The annealing may be performed before and/or after the nitridation to mitigate deposition and/or nitridation defects and to densify the material while mitigating formation of unwanted low dielectric constant oxides at the interface between the gate dielectric and the semiconductor substrate.
摘要翻译：公开了用于处理沉积的栅极电介质材料的方法，其中沉积的电介质经受一个或多个非氧化退火以致密化材料，一个或多个氧化退火以减轻材料缺陷，以及氮化过程以将氮引入栅电介质。可以在氮化之前和/或之后进行退火以减轻沉积和/或氮化缺陷并致密材料，同时减轻在栅极电介质和半导体衬底之间的界面处形成不想要的低介电常数氧化物。

79. 发明申请

US20050124109A1 Top surface roughness reduction of high-k dielectric materials using plasma based processes 有权
标题翻译：使用基于等离子体工艺的高k介电材料的顶表面粗糙度降低
公开(公告)号：US20050124109A1
公开(公告)日：2005-06-09
申请号：US10726987
申请日：2003-12-03
申请人： Manuel Quevedo-Lopez , James Chambers , Luigi Colombo , Mark Visokay
发明人： Manuel Quevedo-Lopez , James Chambers , Luigi Colombo , Mark Visokay
IPC分类号： C23C16/40 , C23C16/56 , H01L21/3105 , H01L21/314 , H01L21/316 , H01L21/302 , H01L21/461 , H01L21/8242 , H01L21/31
CPC分类号： H01L21/0234 , C23C16/401 , C23C16/405 , C23C16/56 , H01L21/02175 , H01L21/02181 , H01L21/02194 , H01L21/3105 , H01L21/31053 , H01L21/3143 , H01L21/3144 , H01L21/31604 , H01L21/31645 , H01L21/31691
摘要： A system and method for manufacturing semiconductor devices with dielectric layers having a dielectric constant greater than silicon dioxide includes depositing a dielectric layer on a substrate and subjecting the dielectric layer to a plasma to reduce top surface roughness in the dielectric layer.
摘要翻译：具有介电常数大于二氧化硅的电介质层的半导体器件的系统和方法包括在基片上沉积电介质层并对介电层进行等离子体以减小电介质层中的顶表面粗糙度。

80. 发明授权

US06902939B2 Integrated circuit and method 有权
标题翻译：集成电路及方法
公开(公告)号：US06902939B2
公开(公告)日：2005-06-07
申请号：US10223643
申请日：2002-08-19
申请人： Theodore S. Moise , Guoqiang Xing , Mark Visokay , Justin F. Gaynor , Stephen R. Gilbert , Francis Celii , Scott R. Summerfelt , Luigi Colombo
发明人： Theodore S. Moise , Guoqiang Xing , Mark Visokay , Justin F. Gaynor , Stephen R. Gilbert , Francis Celii , Scott R. Summerfelt , Luigi Colombo
IPC分类号： H01L21/302 , H01L21/02 , H01L21/033 , H01L21/3065 , H01L21/311 , H01L21/8242 , H01L21/8246 , H01L27/115 , H01L21/00
CPC分类号： H01L27/11502 , H01L21/0332 , H01L21/31116 , H01L21/31144 , H01L27/10852 , H01L27/11507 , H01L28/55
摘要： A via etch to contact a capacitor with ferroelectric between electrodes together with dielectric on an insulating diffusion barrier includes two-step etch with F-based dielectric etch and Cl- and F-based barrier etch.
摘要翻译：在电极之间与电介质之间的电介质与绝缘扩散阻挡层之间的电介质接触电容器的通孔蚀刻包括基于F的电介质蚀刻和基于Cl和F的势垒蚀刻的两步蚀刻。

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