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71. 发明申请

US20080003697A1 INTEGRATION PROCESSES FOR FABRICATING A CONDUCTIVE METAL OXIDE GATE FERROELECTRIC MEMORY TRANSISTOR 失效
标题翻译：用于制造导电金属氧化物栅极电介质晶体管的集成工艺
公开(公告)号：US20080003697A1
公开(公告)日：2008-01-03
申请号：US11215521
申请日：2005-08-30
申请人： Tingkai Li , Sheng Hsu , Bruce Ulrich
发明人： Tingkai Li , Sheng Hsu , Bruce Ulrich
IPC分类号： H01L21/00
CPC分类号： H01L21/28291 , H01L29/66583 , H01L29/78
摘要： A method of fabricating a conductive metal oxide gate ferroelectric memory transistor includes forming an oxide layer a substrate and removing the oxide layer in a gate area; depositing a conductive metal oxide layer on the oxide layer and on the exposed gate area; depositing a titanium layer on the metal oxide layer; patterning and etching the titanium layer and the metal oxide layer to remove the titanium layer and the metal oxide layer from the substrate except in the gate area; depositing, patterning and etching an oxide layer to form a gate trench; depositing and etching a barrier insulator layer to form a sidewall barrier in the gate trench; removing the titanium layer from the gate area; depositing, smoothing and annealing a ferroelectric layer in the gate trench; depositing, patterning and etching a top electrode; and completing the conductive metal oxide gate ferroelectric memory transistor.
摘要翻译：一种制造导电金属氧化物栅极铁电存储晶体管的方法，包括：在衬底上形成氧化物层并去除栅极区域中的氧化物层; 在氧化物层和暴露的栅极区上沉积导电金属氧化物层; 在所述金属氧化物层上沉积钛层; 图案化和蚀刻钛层和金属氧化物层以除去栅极区域之外的基板以除去钛层和金属氧化物层; 沉积，图案化和蚀刻氧化物层以形成栅极沟槽; 沉积和蚀刻阻挡绝缘体层以在栅极沟槽中形成侧壁势垒; 从栅极区域去除钛层; 沉积，平滑和退火栅极沟槽中的铁电层; 沉积，图案化和蚀刻顶部电极; 并完成导电金属氧化物栅极铁电存储晶体管。

72. 发明申请

US20070221975A1 Bipolar switching PCMO capacitor 有权
标题翻译：双极开关PCMO电容
公开(公告)号：US20070221975A1
公开(公告)日：2007-09-27
申请号：US11805177
申请日：2007-05-22
申请人： Tingkai Li , Lawrence Charneski , Wei-Wei Zhuang , David Evans , Sheng Hsu
发明人： Tingkai Li , Lawrence Charneski , Wei-Wei Zhuang , David Evans , Sheng Hsu
IPC分类号： H01L29/92
CPC分类号： H01L45/04 , H01L45/1233 , H01L45/147 , H01L45/1616
摘要： A multi-layer PrxCa1-xMnO3 (PCMO) thin film capacitor and associated deposition method are provided for forming a bipolar switching thin film. The method comprises: forming a bottom electrode; depositing a nanocrystalline PCMO layer; depositing a polycrystalline PCMO layer; forming a multi-layer PCMO film with bipolar switching properties; and forming top electrode overlying the PCMO film. If the polycrystalline layers are deposited overlying the nanocrystalline layers, a high resistance can be written with narrow pulse width, negative voltage pulses. The PCMO film can be reset to a low resistance using a narrow pulse width, positive amplitude pulse. Likewise, if the nanocrystalline layers are deposited overlying the polycrystalline layers, a high resistance can be written with narrow pulse width, positive voltage pulses, and reset to a low resistance using a narrow pulse width, negative amplitude pulse.
摘要翻译：提供了多层Pr 1 x 1 x x MnO 3（PCMO）薄膜电容器和相关的沉积方法，用于形成双极开关薄膜。该方法包括：形成底部电极; 沉积纳米晶体PCMO层; 沉积多晶的PCMO层; 形成具有双极开关特性的多层PCMO膜; 并形成覆盖PCMO膜的顶部电极。如果多晶层沉积在纳米晶层之上，则可以用窄脉冲宽度，负电压脉冲写入高电阻。 PCMO膜可以使用窄脉冲宽度，正幅度脉冲复位为低电阻。同样，如果纳米晶层沉积在多晶层上，则可以用窄脉冲宽度，正电压脉冲写入高电阻，并使用窄脉冲宽度，负幅度脉冲将其复位为低电阻。

73. 发明授权

US07259055B2 Method of forming high-luminescence silicon electroluminescence device 失效
标题翻译：形成高发光硅电致发光器件的方法
公开(公告)号：US07259055B2
公开(公告)日：2007-08-21
申请号：US11066713
申请日：2005-02-24
申请人： Tingkai Li , Pooran Chandra Joshi , Wei Gao , Yoshi Ono , Sheng Teng Hsu
发明人： Tingkai Li , Pooran Chandra Joshi , Wei Gao , Yoshi Ono , Sheng Teng Hsu
IPC分类号： H01L21/8238
CPC分类号： H01L31/03046 , Y02E10/544 , Y02P70/521
摘要： A method for forming a high-luminescence Si electroluminescence (EL) phosphor is provided, with an EL device made from the Si phosphor. The method comprises: depositing a silicon-rich oxide (SRO) film, with Si nanocrystals, having a refractive index in the range of 1.5 to 2.1, and a porosity in the range of 5 to 20%; and, post-annealing the SRO film in an oxygen atmosphere. DC-sputtering or PECVD processes can be used to deposit the SRO film. In one aspect the method further comprises: HF buffered oxide etching (BOE) the SRO film; and, re-oxidizing the SRO film, to form a SiO2 layer around the Si nanocrystals in the SRO film. In one aspect, the SRO film is re-oxidized by annealing in an oxygen atmosphere. In this manner, a layer of SiO2 is formed around the Si nanocrystals having a thickness in the range of 1 to 5 nanometers (nm).
摘要翻译：提供一种用于形成高发光Si电致发光（EL）荧光体的方法，其具有由Si荧光体制成的EL器件。该方法包括：用Si纳米晶体沉积富含氧的氧化物（SRO）膜，折射率在1.5至2.1范围内，孔隙率在5至20％的范围内; 并且在氧气氛中对SRO膜进行后退火。 DC溅射或PECVD工艺可用于沉积SRO膜。在一个方面，该方法还包括：HF缓冲氧化物蚀刻（BOE）SRO膜; 并且再次氧化SRO膜，以在SRO膜中的Si纳米晶体周围形成SiO 2层。在一个方面，SRO膜通过在氧气气氛中退火再次氧化。以这种方式，在具有1至5纳米（nm）范围内的厚度的Si纳米晶体周围形成SiO 2层。

74. 发明申请

US20060214172A1 Electroluminescence device with nanotip diodes 有权
标题翻译：具有纳米二极管的电致发光器件
公开(公告)号：US20060214172A1
公开(公告)日：2006-09-28
申请号：US11090386
申请日：2005-03-23
申请人： Sheng Hsu , Tingkai Li , Wei-Wei Zhuang
发明人： Sheng Hsu , Tingkai Li , Wei-Wei Zhuang
IPC分类号： H01L33/00 , H01L21/00
CPC分类号： H01L33/08 , B82Y20/00 , H01L33/18 , H01L33/24 , H01L33/34 , H01L33/502 , Y10S977/834
摘要： A nanotip electroluminescence (EL) diode and a method are provided for fabricating said device. The method comprises: forming a plurality of Si nanotip diodes; forming a phosphor layer overlying the nanotip diode; and, forming a top electrode overlying the phosphor layer. The nanotip diodes are formed by: forming a Si substrate with a top surface; forming a Si p-well; forming an n+ layer of Si, having a thickness in the range of 30 to 300 nanometers (nm) overlying the Si p-well; forming a reactive ion etching (RIE)-induced polymer grass overlying the substrate top surface; using the RIE-induced polymer grass as a mask, etching areas of the substrate not covered by the mask; and, forming the nanotip diodes in areas of the substrate covered by the mask.
摘要翻译：提供了一种纳米末端电致发光（EL）二极管和一种用于制造所述器件的方法。该方法包括：形成多个Si纳米二极管; 形成覆盖所述纳米二极管的磷光体层; 并且形成覆盖磷光体层的顶部电极。纳米二极管通过以下方式形成：形成具有顶表面的Si衬底; 形成Si对孔; 形成层叠Si层的厚度为30〜300纳米（nm）的Si的n +层; 形成覆盖在衬底顶表面上的反应离子蚀刻（RIE）诱导的聚合物草; 使用RIE诱导的聚合物草作为掩模，蚀刻未被掩模覆盖的基底的区域; 以及在由掩模覆盖的衬底的区域中形成纳米二极管二极管。

75. 发明申请

US20060189014A1 High-luminescence silicon electroluminescence device 失效
标题翻译：高发光硅电致发光器件
公开(公告)号：US20060189014A1
公开(公告)日：2006-08-24
申请号：US11066713
申请日：2005-02-24
申请人： Tingkai Li , Pooran Joshi , Wei Gao , Yoshi Ono , Sheng Hsu
发明人： Tingkai Li , Pooran Joshi , Wei Gao , Yoshi Ono , Sheng Hsu
IPC分类号： H01L21/00
CPC分类号： H01L31/03046 , Y02E10/544 , Y02P70/521
摘要： A method for forming a high-luminescence Si electroluminescence (EL) phosphor is provided, with an EL device made from the Si phosphor. The method comprises: depositing a silicon-rich oxide (SRO) film, with Si nanocrystals, having a refractive index in the range of 1.5 to 2.1, and a porosity in the range of 5 to 20%; and, post-annealing the SRO film in an oxygen atmosphere. DC-sputtering or PECVD processes can be used to deposit the SRO film. In one aspect the method further comprises: HF buffered oxide etching (BOE) the SRO film; and, re-oxidizing the SRO film, to form a SiO2 layer around the Si nanocrystals in the SRO film. In one aspect, the SRO film is re-oxidized by annealing in an oxygen atmosphere. In this manner, a layer of SiO2 is formed around the Si nanocrystals having a thickness in the range of 1 to 5 nanometers (nm).
摘要翻译：提供一种用于形成高发光Si电致发光（EL）荧光体的方法，其具有由Si荧光体制成的EL器件。该方法包括：用Si纳米晶体沉积富含氧的氧化物（SRO）膜，折射率在1.5至2.1范围内，孔隙率在5至20％的范围内; 并且在氧气氛中对SRO膜进行后退火。 DC溅射或PECVD工艺可用于沉积SRO膜。在一个方面，该方法还包括：HF缓冲氧化物蚀刻（BOE）SRO膜; 并且再次氧化SRO膜，以在SRO膜中的Si纳米晶体周围形成SiO 2层。在一个方面，SRO膜通过在氧气气氛中退火再次氧化。以这种方式，在具有1至5纳米（nm）范围内的厚度的Si纳米晶体周围形成SiO 2层。

76. 发明申请

US20060183305A1 Sputter-deposited rare earth element-doped silicon oxide film with silicon nanocrystals for electroluminescence applications 失效
标题翻译：溅射沉积的稀土元素掺杂氧化硅膜与硅纳米晶体用于电致发光应用
公开(公告)号：US20060183305A1
公开(公告)日：2006-08-17
申请号：US11334015
申请日：2006-01-18
申请人： Wei Gao , Tingkai Li , Robert Barrowcliff , Yoshi Ono , Sheng Hsu
发明人： Wei Gao , Tingkai Li , Robert Barrowcliff , Yoshi Ono , Sheng Hsu
IPC分类号： H01L21/425
CPC分类号： H05B33/145 , H01L21/3115 , H01L31/03046 , Y02E10/544
摘要： A method is provided for forming a rare earth (RE) element-doped silicon (Si) oxide film with nanocrystalline (nc) Si particles. The method comprises: providing a first target of Si, embedded with a first rare earth element; providing a second target of Si; co-sputtering the first and second targets; forming a Si-rich Si oxide (SRSO) film on a substrate, doped with the first rare earth element; and, annealing the rare earth element-doped SRSO film. The first target is doped with a rare earth element such as erbium (Er), ytterbium (Yb), cerium (Ce), praseodymium (Pr), or terbium (Tb). The sputtering power is in the range of about 75 to 300 watts (W). Different sputtering powers are applied to the two targets. Also, deposition can be controlled by varying the effective areas of the two targets. For example, one of the targets can be partially covered.
摘要翻译：提供了一种用于形成具有纳米晶体（nc）Si颗粒的稀土（RE）元素掺杂硅（Si）氧化物膜的方法。该方法包括：提供嵌入有第一稀土元素的Si的第一靶; 提供Si的第二个目标; 共溅射第一和第二个目标; 在掺杂有第一稀土元素的衬底上形成富Si氧化硅（SRSO）膜; 并对稀土元素掺杂的SRSO膜退火。第一靶用铒（Er），镱（Yb），铈（Ce），镨（Pr）或铽（Tb）等稀土元素掺杂。溅射功率在约75至300瓦（W）的范围内。不同的溅射功率被应用于两个目标。此外，可以通过改变两个目标的有效面积来控制沉积。例如，其中一个目标可以被部分覆盖。

77. 发明授权

US07008801B2 Method of forming ferroelectric thin films on a high-k layer 失效
公开(公告)号：US07008801B2
公开(公告)日：2006-03-07
申请号：US10453831
申请日：2003-06-02
申请人： Tingkai Li , Sheng Teng Hsu
发明人： Tingkai Li , Sheng Teng Hsu
IPC分类号： H01L21/00
CPC分类号： H01L21/28273 , C23C16/0272 , C23C16/40 , C23C16/56 , H01L21/28194 , H01L21/28291 , H01L21/31691 , H01L28/56 , H01L29/513 , H01L29/517
摘要： A method of forming a ferroelectric thin film on a high-k layer includes preparing a silicon substrate; forming a high-k layer on the substrate; depositing a seed layer of ferroelectric material at a relatively high temperature on the high-k layer; depositing a top layer of ferroelectric material on the seed layer at a relatively low temperature; and annealing the substrate, the high-k layer and the ferroelectric layers to form a ferroelectric thin film.

78. 发明申请

US20050282296A1 ASYMMETRICAL PROGRAMMING FERROELECTRIC MEMORY TRANSISTOR 失效
标题翻译：非对称编程电磁记忆晶体管
公开(公告)号：US20050282296A1
公开(公告)日：2005-12-22
申请号：US10873326
申请日：2004-06-21
申请人： Sheng Hsu , Tingkai Li
发明人： Sheng Hsu , Tingkai Li
IPC分类号： H01L21/00 , H01L29/78
CPC分类号： H01L29/78391
摘要： A method of fabricating and programming a ferroelectric memory transistor for asymmetrical programming includes fabricating a ferroelectric memory transistor having a metal oxide layer overlaying a gate region; and programming the ferroelectric memory transistor so that a low threshold voltage is about equal to the intrinsic threshold voltage of the ferrorelectric memory transistor.
摘要翻译：制造和编程用于非对称编程的铁电存储晶体管的方法包括制造具有覆盖栅极区域的金属氧化物层的铁电存储晶体管; 并且对铁电存储晶体管进行编程，使得低阈值电压约等于铁电介质存储晶体管的固有阈值电压。

79. 发明申请

US20050207265A1 Memory cell with an asymmetric crystalline structure 有权
标题翻译：具有不对称晶体结构的记忆单元
公开(公告)号：US20050207265A1
公开(公告)日：2005-09-22
申请号：US11130983
申请日：2005-05-16
申请人： Sheng Hsu , Tingkai Li , David Evans , Wei-Wei Zhuang , Wei Pan
发明人： Sheng Hsu , Tingkai Li , David Evans , Wei-Wei Zhuang , Wei Pan
IPC分类号： H01L27/10 , G11C11/15 , G11C13/00 , H01L45/00 , G11C8/02
CPC分类号： G11C13/0007 , G11C2213/31 , H01L45/04 , H01L45/1233 , H01L45/147 , H01L45/1608 , H01L45/1625
摘要： Asymmetrically structured memory cells and a fabrication method are provided. The method comprises: forming a bottom electrode; forming an electrical pulse various resistance (EPVR) first layer having a polycrystalline structure over the bottom electrode; forming an EPVR second layer adjacent the first layer, with a nano-crystalline or amorphous structure; and, forming a top electrode overlying the first and second EPVR layers. EPVR materials include CMR, high temperature super conductor (HTSC), or perovskite metal oxide materials. In one aspect, the EPVR first layer is deposited with a metalorganic spin coat (MOD) process at a temperature in the range between 550 and 700 degrees C. The EPVR second layer is formed at a temperature less than, or equal to the deposition temperature of the first layer. After a step of removing solvents, the MOD deposited EPVR second layer is formed at a temperature less than, or equal to the 550 degrees C.
摘要翻译：提供了非对称结构的存储单元和制造方法。该方法包括：形成底部电极; 在底部电极上形成具有多晶结构的电脉冲各种电阻（EPVR）第一层; 用纳米结晶或无定形结构形成邻近第一层的EPVR第二层; 并且形成覆盖在第一和第二EPVR层上的顶部电极。 EPVR材料包括CMR，高温超导体（HTSC）或钙钛矿金属氧化物材料。在一个方面，EPVR第一层在550-700℃的温度范围内用金属有机旋涂（MOD）工艺沉积.EPVR第二层是在小于或等于沉积温度的第一层。在除去溶剂的步骤之后，将MOD沉积的EPVR第二层在小于或等于550℃的温度下形成。

80. 发明授权

US06939724B2 Method for obtaining reversible resistance switches on a PCMO thin film when integrated with a highly crystallized seed layer 有权
公开(公告)号：US06939724B2
公开(公告)日：2005-09-06
申请号：US10640770
申请日：2003-08-13
申请人： Wei-Wei Zhuang , Tingkai Li , David R. Evans , Sheng Teng Hsu , Wei Pan
发明人： Wei-Wei Zhuang , Tingkai Li , David R. Evans , Sheng Teng Hsu , Wei Pan
IPC分类号： H01L27/04 , H01L21/20 , H01L21/822 , H01L45/00 , H01L21/00
CPC分类号： G11C13/0007 , G11C2213/31 , H01L45/04 , H01L45/1233 , H01L45/147 , H01L45/1608
摘要： A method for obtaining reversible resistance switches on a PCMO thin film when integrated with a highly crystallized seed layer includes depositing, by MOCVD, a seed layer of PCMO, in highly crystalline form, thin film, having a thickness of between about 50 Å to 300 Å, depositing a second PCMO thin film layer on the seed layer, by spin coating, having a thickness of between about 500 Å to 3000 Å, to form a combined PCMO layer; increasing the resistance of the combined PCMO film in a semiconductor device by applying a negative electric pulse of between about −4V to −5V, having a pulse width of between about 75 nsec to 1 μsec; and decreasing the resistance of the combined PCMO layer in a semiconductor device by applying a positive electric pulse of between about +2.5V to +4V, having a pulse width greater than 2.0 μsec.

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