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71. 发明授权

US07418163B2 Optoelectrical package 失效
标题翻译：光电封装
公开(公告)号：US07418163B2
公开(公告)日：2008-08-26
申请号：US10109313
申请日：2002-03-28
申请人： Kishore K. Chakravorty , Joseph F. Ahadian , Johanna Swan , Thomas P. Thomas , Brandon C. Barnett , Ian Young
发明人： Kishore K. Chakravorty , Joseph F. Ahadian , Johanna Swan , Thomas P. Thomas , Brandon C. Barnett , Ian Young
IPC分类号： G02B6/12
CPC分类号： G02B6/43 , G02B6/42 , G02B6/4214 , G02B6/4232 , G02B6/4249 , G02B6/4255 , G02B6/4257 , G02B6/426 , G02B6/428 , G02B6/4287
摘要： An integrated optoelectrical package for optoelectrical integrated circuits (ICs) is disclosed. The package includes a package substrate having contact receiving members on an upper surface. The contact receiving members are electrically connected to contacts on the lower surface. An optoelectronic receiver package and an optoelectronic transmitter package are each electrically mounted to respective first and second subsets of the contact receiving members. Input and output waveguide arrays are formed atop the substrate package and are optically coupled to the optoelectronic receiver package and the optoelectronic transmitter package, respectively. The contacts on the lower surface of the package substrate are designed to contact and engage the contact receiving members of a standard printed circuit board (PCB).
摘要翻译：公开了一种用于光电集成电路（IC）的集成光电封装。该封装包括在上表面上具有接触部件的封装基板。触点接收构件电连接到下表面上的触点。光电子接收器封装和光电发射器封装各自电连接到触点容纳部件的相应的第一和第二子集。输入和输出波导阵列形成在衬底封装的顶部，并分别光耦合到光电接收器封装和光电发射器封装。封装基板的下表面上的触点被设计成接触和接合标准印刷电路板（PCB）的触点接收构件。

72. 发明申请

US20080122545A1 Low power and duty cycle error free matched current phase locked loop 失效
标题翻译：低功耗和占空比无错误匹配电流锁相环
公开(公告)号：US20080122545A1
公开(公告)日：2008-05-29
申请号：US11592591
申请日：2006-11-03
申请人： Yongping Fan , Ian Young
发明人： Yongping Fan , Ian Young
IPC分类号： H03L7/099 , H03L7/085 , H03K3/353 , H03L7/089
CPC分类号： H03L7/0995 , H03K5/133 , H03K2005/00039 , H03K2005/00136 , H03L7/0891 , H03L7/18
摘要： A phase locked loop with a voltage controlled oscillator, where the voltage controlled oscillator includes a feedback loop and delay cells connected in a ring. Each delay cell has a biased pMOSFET to provide pull-up current and a biased nMOSFET to provide pull-down current. For each delay cell, the gate of the biased nMOSFET is biased by the control voltage provided by the phase locked loop, and the gate of the biased pMOSFET is biased at a bias voltage provided by the feedback loop. The biasing of the pMOSFETs is adjusted so that the pull-up and pull-down currents for each delay cell are matched, thereby providing a 50% duty cycle and good jitter performance over process, supply voltage variations, and temperature variations. Because only the feedback loop has non-zero static current, low power is expected. Other embodiments are described and claimed.
摘要翻译：具有压控振荡器的锁相环，其中压控振荡器包括反馈回路和以环形连接的延迟单元。每个延迟单元具有偏置的pMOSFET以提供上拉电流和偏置的nMOSFET以提供下拉电流。对于每个延迟单元，偏置的nMOSFET的栅极被由锁相环提供的控制电压偏置，并且偏置的pMOSFET的栅极被偏置在由反馈环路提供的偏置电压。调整pMOSFET的偏置，使得每个延迟单元的上拉和下拉电流匹配，从而提供50％的占空比以及在处理，电源电压变化和温度变化方面的良好的抖动性能。因为只有反馈回路具有非零静态电流，所以预期功耗低。描述和要求保护其他实施例。

73. 发明授权

US07068892B1 Passively aligned optical-electrical interface 有权
标题翻译：被动对准的光电接口
公开(公告)号：US07068892B1
公开(公告)日：2006-06-27
申请号：US11096504
申请日：2005-03-29
申请人： Daoqiang Lu , Henning Braunisch , Edris M. Mohammed , Ian Young
发明人： Daoqiang Lu , Henning Braunisch , Edris M. Mohammed , Ian Young
IPC分类号： G02B6/42
CPC分类号： G02B6/4292 , G02B6/423 , G02B6/4232 , G02B6/4249
摘要： An optical-electrical interface includes an alignment interface and an optoelectronic die. The alignment interface is mounted to a substrate and includes a waveguide port to receive an external waveguide from a first side. The alignment interface includes a conductor disposed on a second side of the alignment interface to couple to a conductor on the substrate. The optoelectronic die is mounted to the second side of the alignment interface. The optoelectronic die includes an electrical port coupled to the conductor disposed on the alignment interface, an optoelectronic device coupled to the electrical port and an optical port aligned to optically couple the optoelectronic device to the external waveguide through the alignment interface.
摘要翻译：光电接口包括对准接口和光电管芯。对准接口安装到基板并且包括用于从第一侧接收外部波导的波导端口。对准接口包括设置在对准接口的第二侧上的导体，以耦合到衬底上的导体。光电管芯安装在对准接口的第二侧。光电管芯包括耦合到布置在对准接口上的导体的电端口，耦合到电端口的光电子器件和对准以通过对准接口将光电子器件光耦合到外部波导的光端口。

74. 发明授权

US06968104B2 Variable bending radius H-tree distribution device 失效
标题翻译：可变弯曲半径H树分布装置
公开(公告)号：US06968104B2
公开(公告)日：2005-11-22
申请号：US10364611
申请日：2003-02-10
申请人： Jun-Fei Zheng , Ian Young , Dongwhan Ahn
发明人： Jun-Fei Zheng , Ian Young , Dongwhan Ahn
IPC分类号： G02B6/12 , G02B6/125 , G02B6/26
CPC分类号： G02B6/125 , G02B2006/12173 , G02B2006/12176
摘要： An optical network, in the form of a 1×2N splitter, includes a series of interconnected distribution devices of varying size. Each distribution device may be an H-tree distribution device having an input waveguide and four output waveguides that provide in-phase, equal intensity copies of a signal received on the input waveguide. The network may include a primary H-tree distribution device and a plurality of secondary H-tree distribution devices each of a smaller size than the primary H-tree distribution device. Individual H-tree distribution devices may have a first stage Y-branch and a second stage Y-branch each of different radii of curvature. Further still, progressively smaller radius of curvature Y-branches may be used to form the 1×2N splitter, where N may be an even or odd integer.
摘要翻译：形式为1×2 N分离器的光网络包括一系列具有不同尺寸的相互连接的分配装置。每个分配设备可以是具有输入波导和四个输出波导的H树分配设备，其提供在输入波导上接收的信号的同相等强度副本。网络可以包括主H树分发设备和每个比主H树分发设备更小的多个次H树分发设备。各个H树分配装置可以具有不同的曲率半径的第一阶段Y分支和第二阶段Y分支。此外，仍然可以使用逐渐变小的曲率半径Y分支来形成1x2分割器，其中N可以是偶数或奇数整数。

75. 发明授权

US06754407B2 Flip-chip package integrating optical and electrical devices and coupling to a waveguide on a board 失效
标题翻译：整合光学和电气设备并耦合到板上波导的倒装芯片封装
公开(公告)号：US06754407B2
公开(公告)日：2004-06-22
申请号：US10158250
申请日：2002-05-30
申请人： Kishore K. Chakravorty , Johanna Swan , Brandon C. Barnett , Joseph F. Ahadian , Thomas P. Thomas , Ian Young
发明人： Kishore K. Chakravorty , Johanna Swan , Brandon C. Barnett , Joseph F. Ahadian , Thomas P. Thomas , Ian Young
IPC分类号： G02B612
CPC分类号： G02B6/42 , G02B6/4206 , G02B6/4212 , G02B6/4214 , G02B6/4231 , G02B6/43 , H05K1/0274 , H05K3/3436 , H05K2201/10121 , H05K2201/10734
摘要： A package allowing both electrical and optical coupling between one or more integrated circuits and a printed circuit board (PCB) has an optical waveguide structures in addition to electrical connections. An optically active device is flip-chip bonded directly to an integrated circuit using solder bump technology. The optically active device has a lens attached to it to facilitate optical coupling to the optical waveguide. The integrated circuit is flip-chip bonded to a Ball Grid Array (BGA) package. The BGA package is bonded to the PCB using solder reflow technology.
摘要翻译：允许一个或多个集成电路和印刷电路板（PCB）之间的电和光耦合的封装除了电连接之外还具有光波导结构。使用焊料凸块技术将光学有源器件直接贴合到集成电路上。光学器件具有附接到其上的透镜以便于光耦合到光波导。集成电路倒装芯片结合到球栅阵列（BGA）封装。使用焊锡回流技术将BGA封装结合到PCB。

76. 发明授权

US6008644A Nuclear Polarization Enhanced Nuclear Magnetic Resonance Imaaging 失效
标题翻译：核极化增强核磁共振成像
公开(公告)号：US6008644A
公开(公告)日：1999-12-28
申请号：US888317
申请日：1997-07-03
申请人： Ib Leunbach , Ian Young , Gosta Ehnholm , Georg Hansson , Stefan Petersson , Lars-Goran Wistrand , Klaes Golman
发明人： Ib Leunbach , Ian Young , Gosta Ehnholm , Georg Hansson , Stefan Petersson , Lars-Goran Wistrand , Klaes Golman
IPC分类号： B82B1/00 , A61B5/055 , G01N24/12 , G01R33/28 , G01R33/62 , G01V3/00
CPC分类号： G01R33/5601 , G01R33/282 , G01R33/62
摘要： This invention relates to a method of electron spin resonance enhanced magnetic resonance imaging which relies on ex vivo dynamic nuclear polarisation of an MR imaging agent.
摘要翻译：本发明涉及依赖于MR成像剂的离体动态核极化的电子自旋共振增强磁共振成像方法。

77. 发明授权

US5446867A Microprocessor PLL clock circuit with selectable delayed feedback 失效
标题翻译：具有可选延迟反馈的微处理器PLL时钟电路
公开(公告)号：US5446867A
公开(公告)日：1995-08-29
申请号：US890937
申请日：1992-05-29
申请人： Ian Young , Keng L. Wong , Jeffrey Smith
发明人： Ian Young , Keng L. Wong , Jeffrey Smith
IPC分类号： G06F1/10 , H03L7/081 , H03L7/089 , G06F1/00 , G06F1/04 , G06F1/06
CPC分类号： H03L7/081 , G06F1/10 , H03L7/0891
摘要： A circuit for use in high performance microprocessor systems which eliminates skew between a clock signal internal to the microprocessor core and inputs generated by a clock signal external to the microprocessor core. The circuit includes a phase locked loop (PLL), a delay line and a clock driver. The PLL locks and deskews the external clock edge to that of the internal clock to thereby provide an overall reduction of the setup and hold time window to satisfy the tight I/O timings required by high performance microprocessor systems. By incorporating the same PLL in all the closely coupled components of the microprocessor core, similar temperature and power supply tracking of such components is achieved. The PLL is a charge-pump based circuit of the type known in the art incorporating a phase detector, charge pump, loop filter and voltage controlled oscillator (VCO). However, the inclusion of the delay line in the feedback path of the PLL provides advantages not available from PLLs without such a delay line. A programmable tap is provided in the delay line which allows the I/O circuitry of the microprocessor to work with either CMOS or TTL input specifications. Specifically, compensation is provided for the differences in propagation delay between CMOS and TTL input buffers.
摘要翻译：用于高性能微处理器系统的电路，其消除了微处理器内核内部的时钟信号与由微处理器核心外部的时钟信号产生的输入之间的偏差。该电路包括锁相环（PLL），延迟线和时钟驱动器。 PLL锁定并将外部时钟边沿撇除为内部时钟的边沿，从而提供建立和保持时间窗口的全面减少，以满足高性能微处理器系统所需的紧密I / O时序。通过将相同的PLL结合在微处理器核心的所有紧密耦合的组件中，实现了类似的温度和电源跟踪这些组件。 PLL是本领域已知的类型的基于电荷泵的电路，其包括相位检测器，电荷泵，环路滤波器和压控振荡器（VCO）。然而，在PLL的反馈路径中包括延迟线提供了在没有这样的延迟线的情况下不能从PLL获得的优点。在延迟线上提供了一个可编程分接头，允许微处理器的I / O电路工作在CMOS或TTL输入规格。具体来说，为CMOS和TTL输入缓冲器之间的传播延迟的差异提供了补偿。

78. 发明授权

US3612975A Electronic data-processing apparatus 失效
标题翻译：电子数据处理设备
公开(公告)号：US3612975A
公开(公告)日：1971-10-12
申请号：US3612975D
申请日：1969-08-05
申请人： IAN YOUNG ELECTRONIC DESIGNS L
发明人： KEEFE ARTHUR T
IPC分类号： G05D3/18 , G06G7/28 , H03K5/04 , H03K5/26 , H03M1/00 , G05B11/28
CPC分类号： H03K5/04 , G05D3/18 , G06G7/28 , H03K5/26 , H03M1/00 , H03M1/50
摘要： In a circuit for converting a signal representing by its amplitude an item of data into a signal representing the item of data by its pulse duration, or vice versa, by comparison of an input signal with a ramp signal, a calibrating signal is applied to the amplitude-to-duration converter and the resulting pulse duration is compared with a calibrating pulse having a duration corresponding, at the required conversion scale, to the amplitude of the calibrating signal; any error signal from the comparator is used to adjust the ramp slope or ramp base line in a sense such as to reduce the error.

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