会员体验
专利管家（专利管理）
工作空间（专利管理）
风险监控（情报监控）
数据分析（专利分析）
侵权分析（诉讼无效）
联系我们
交流群
官方交流：
QQ群： 891211   
微信请扫码    >>>
现在联系顾问~
下载
著录项
PDF全文
热词
    • 1. 发明授权
      US5446867A Microprocessor PLL clock circuit with selectable delayed feedback 失效
    • Microprocessor PLL clock circuit with selectable delayed feedback
    • 具有可选延迟反馈的微处理器PLL时钟电路
    • US5446867A
    • 1995-08-29
    • US890937
    • 1992-05-29
    • Ian Young , Keng L. Wong , Jeffrey Smith
    • Ian Young , Keng L. Wong , Jeffrey Smith
    • G06F1/10 , H03L7/081 , H03L7/089 , G06F1/00 , G06F1/04 , G06F1/06
    • H03L7/081 , G06F1/10 , H03L7/0891
    • A circuit for use in high performance microprocessor systems which eliminates skew between a clock signal internal to the microprocessor core and inputs generated by a clock signal external to the microprocessor core. The circuit includes a phase locked loop (PLL), a delay line and a clock driver. The PLL locks and deskews the external clock edge to that of the internal clock to thereby provide an overall reduction of the setup and hold time window to satisfy the tight I/O timings required by high performance microprocessor systems. By incorporating the same PLL in all the closely coupled components of the microprocessor core, similar temperature and power supply tracking of such components is achieved. The PLL is a charge-pump based circuit of the type known in the art incorporating a phase detector, charge pump, loop filter and voltage controlled oscillator (VCO). However, the inclusion of the delay line in the feedback path of the PLL provides advantages not available from PLLs without such a delay line. A programmable tap is provided in the delay line which allows the I/O circuitry of the microprocessor to work with either CMOS or TTL input specifications. Specifically, compensation is provided for the differences in propagation delay between CMOS and TTL input buffers.
    • 用于高性能微处理器系统的电路，其消除了微处理器内核内部的时钟信号与由微处理器核心外部的时钟信号产生的输入之间的偏差。 该电路包括锁相环（PLL），延迟线和时钟驱动器。 PLL锁定并将外部时钟边沿撇除为内部时钟的边沿，从而提供建立和保持时间窗口的全面减少，以满足高性能微处理器系统所需的紧密I / O时序。 通过将相同的PLL结合在微处理器核心的所有紧密耦合的组件中，实现了类似的温度和电源跟踪这些组件。 PLL是本领域已知的类型的基于电荷泵的电路，其包括相位检测器，电荷泵，环路滤波器和压控振荡器（VCO）。 然而，在PLL的反馈路径中包括延迟线提供了在没有这样的延迟线的情况下不能从PLL获得的优点。 在延迟线上提供了一个可编程分接头，允许微处理器的I / O电路工作在CMOS或TTL输入规格。 具体来说，为CMOS和TTL输入缓冲器之间的传播延迟的差异提供了补偿。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 2. 发明授权
      US5412349A PLL clock generator integrated with microprocessor 失效
    • PLL clock generator integrated with microprocessor
    • PLL时钟发​​生器与微处理器集成
    • US5412349A
    • 1995-05-02
    • US861288
    • 1992-03-31
    • Ian Young , Keng L. Wong , Jeffrey K. Greason
    • Ian Young , Keng L. Wong , Jeffrey K. Greason
    • H03K3/0231 , H03L7/089 , H03L7/099 , H03B5/02
    • H03L7/0995 , H03K3/0231 , H03L7/0891 , H03L2207/06
    • A PLL based deskewed clock generator which may be fully integrated on a microprocessor is disclosed. The clock generator has a skew of less than 0.1 ns with peak to peak jitter of 0.3 ns using a 0.8 .mu.m CMOS technology. The PLL comprises a phase frequency detector, charge pump, loop filter and voltage controlled oscillator from which the internal clock is generated. Since the PLL is on the same chip as the microprocessor, it is difficult to isolate the PLL from the noise generated by the microprocessor core logic and output buffers. Without an external filter, noise from the motherboard also influences the PLL. Power supply noise can cause a direct change in the frequency of the voltage controlled oscillator of the PLL. Circuits which overcome the adverse effects which would be created by such noises are also described.
    • 公开了一种可以完全集成在微处理器上的基于PLL的偏移时钟发生器。 时钟发生器的偏移小于0.1 ns，峰值抖动为0.3 ns，采用0.8μmCMOS技术。 PLL包括相位频率检测器，电荷泵，环路滤波器和产生内部时钟的压控振荡器。 由于PLL与微处理器在同一芯片上，所以难以将PLL与微处理器核心逻辑和输出缓冲器产生的噪声隔离开来。 没有外部滤波器，主板噪声也会影响PLL。 电源噪声可能导致PLL压控振荡器频率的直接变化。 还描述了克服由这种噪声产生的不利影响的电路。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 7. 发明申请
      US20100300199A1 POSITIVE DISPLACEMENT FLUID FLOW METER 失效
    • POSITIVE DISPLACEMENT FLUID FLOW METER
    • 积极位移流体流量计
    • US20100300199A1
    • 2010-12-02
    • US11990169
    • 2006-08-10
    • Ian Holmes Higgin , Ian Young , Ivor Rogers
    • Ian Holmes Higgin , Ian Young , Ivor Rogers
    • G01F3/08
    • G01F3/08
    • A positive displacement fluid flow meter comprises a chamber having a fluid inlet and a fluid outlet. A rotor is displaceable within the chamber, rotation of the rotor being related to the volume of fluid passing through the chamber. The chamber has a surface proximate which an end surface of the rotor passes, the chamber surface and/or the rotor end surface having at least one recess to retain at least a portion of debris carried by the metered fluid. The recess is preferably formed so as not to provide fluid, communication, from the inlet to the outlet across the rotor end surface. A lid closes an end of the chamber which in use is subject to the pressure of fluid within the chamber. The lid is engaged at its periphery to a wall of the chamber, and is preferably flexible adjacent its periphery to reduce the transmission of bending stresses between the periphery of the lid and the remainder thereof.
    • 正排量流体流量计包括具有流体入口和流体出口的室。 转子可在腔室内移动，转子的旋转与通过腔室的流体体积相关。 腔室具有靠近转子的端表面的表面，腔室表面和/或转子端表面具有至少一个凹部以保持由计量流体携带的碎屑的至少一部分。 凹部优选地形成为不使流体从转子端表面的入口到出口提供流体。 盖子封闭了腔室的一端，在使用过程中受到室内流体的压力的影响。 盖子在其周边处接合到室的壁上，并且优选地邻近其周边是柔性的，以减小盖的周边与其余部分之间的弯曲应力的传递。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 9. 发明授权
      US07501869B2 Low power, low phase jitter, and duty cycle error insensitive clock receiver architecture and circuits for source synchronous digital data communication 失效
    • Low power, low phase jitter, and duty cycle error insensitive clock receiver architecture and circuits for source synchronous digital data communication
    • 低功耗，低相位抖动和占空比误差不敏感的时钟接收器架构和电路用于源同步数字数据通信
    • US07501869B2
    • 2009-03-10
    • US11592594
    • 2006-11-03
    • Yongping Fan , Ian Young
    • Yongping Fan , Ian Young
    • H03L7/06
    • H03L7/0812 , H03L7/07 , H03L7/0805 , H03L7/0891
    • A clock receiver architecture for source synchronous digital data communication, the receiver including a forwarded clock amplifier to provide the received forwarded clock signal to a plurality of delay locked loops. Each delay locked loops provides to one or more phase interpolators a set of clock signals generated from the received forwarded clock, where the relative phases of the set of clock signals are uniformly spaced. Phase interpolators interpolate between two adjacent (with respect to phase) clock signals so as to provide a clock signal to sample received data at the center of the data eye. In some embodiments, an on-die voltage regulator provides a regulated supply voltage to the delay locked loops and phase interpolators. In some embodiments, pull-up currents and pull-down currents in the phase locked loops and phase interpolators are matched across process, supply voltage, and temperature variations so that the relative phases of the clock signals are insensitive across process, supply voltage, and temperature variations. Other embodiments are described and claimed.
    • 一种用于源同步数字数据通信的时钟接收器架构，接收器包括转发的时钟放大器，以将接收到的转发时钟信号提供给多个延迟锁定环路。 每个延迟锁定环路向一个或多个相位内插器提供从接收的转发时钟生成的一组时钟信号，其中该组时钟信号的相对相位是均匀间隔的。 相位插值器在两个相邻（相对于相位）时钟信号之间插值，以便提供一个时钟信号来对数据眼睛中心的接收数据进行采样。 在一些实施例中，片上电压调节器向延迟锁定环路和相位内插器提供稳定的电源电压。 在一些实施例中，锁相环和相位内插器中的上拉电流和下拉电流在过程，电源电压和温度变化之间匹配，使得时钟信号的相对相位在过程，电源电压和 温度变化。 描述和要求保护其他实施例。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
每页展示10个专利
每页展示10个专利
每页展示20个专利
每页展示50个专利
每页展示100个专利

IPRDB

最新中国发明专利 最新美国发明专利 技术领域 专利库 专利分类库 国际专利分类库

热门服务

会员版试用 API 数据接口 找代理 知嘟嘟专利交易 排行榜 大学排行榜 专利百科

关于我们

平台介绍 战略合作 网站地图

友情链接

知嘟嘟专利交易 国家知识产权局 中国商标网

联系方式


©2019-2023 上海吉码数字技术有限公司 版权所有，并保留所有权利 沪ICP备20016256号-6 沪公网安备31011702005475号