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1. 发明授权

US07851109B2 Low stress pellicle frames and reticle pellicle assemblies 有权
标题翻译：低应力防护薄膜框架和标线防护薄膜组件
公开(公告)号：US07851109B2
公开(公告)日：2010-12-14
申请号：US12060220
申请日：2008-03-31
申请人： Kishore K. Chakravorty , Frank E. Abboud , Henry Yun
发明人： Kishore K. Chakravorty , Frank E. Abboud , Henry Yun
IPC分类号： G03F1/00
CPC分类号： G03F1/64 , G03F1/50 , G03F7/70983
摘要： Low stress reticle pellicle assemblies. In accordance with certain embodiments of the present invention, a pellicle frame of reduced stiffness is employed to reduce the stress a pellicle frame induces in a reticle plate. In other embodiments, a pellicle frame of reduced adhesive surface is employed to reduce the stress a pellicle frame induces in a reticle plate. In accordance with still other embodiments, a stress compensating frame is employed to reduce the cumulative stresses in an assembly comprising the reticle plate, pellicle and stress compensating frame.
摘要翻译：低应力标线片防护膜组件。根据本发明的某些实施例，采用减小刚度的防护薄膜框架来减小防护薄膜组件框架在标线板中引起的应力。在其它实施例中，使用减小粘合剂表面的防护薄膜框架来减少防护薄膜组件框架在分划板板中引起的应力。根据其它实施例，采用应力补偿框架来减小包括光罩板，防护薄膜组件和应力补偿框架的组件中的累积应力。

2. 发明授权

US06844663B1 Structure and method for forming a multilayer electrode for a flat panel display device 失效
标题翻译：用于形成平板显示装置的多层电极的结构和方法
公开(公告)号：US06844663B1
公开(公告)日：2005-01-18
申请号：US09588115
申请日：2000-05-31
申请人： Jueng Gil Lee , Christopher J. Spindt , Johan Knall , Matthew A. Bonn , Kishore K. Chakravorty
发明人： Jueng Gil Lee , Christopher J. Spindt , Johan Knall , Matthew A. Bonn , Kishore K. Chakravorty
IPC分类号： H01J9/02 , H01J29/46 , H01J1/02
CPC分类号： H01J9/148 , H01J29/467
摘要： A structure for a multilayer electrode. Specifically, in one embodiment, a multilayer electrode for a flat panel display device is disclosed. The multilayer electrode comprises a metal alloy layer and a protective layer. The metal alloy layer includes neodymium having a concentration of between greater than three atomic percent and six atomic percent. The protective layer is disposed above the metal alloy layer to form a multilayer stack. The multilayer stack is etched to form the multilayer electrode.
摘要翻译：多层电极的结构。具体地，在一个实施例中，公开了一种用于平板显示装置的多层电极。多层电极包括金属合金层和保护层。金属合金层包括浓度大于3原子％和6原子％之间的钕。保护层设置在金属合金层上方以形成多层叠层。蚀刻多层堆叠以形成多层电极。

3. 发明授权

US06611419B1 Electronic assembly comprising substrate with embedded capacitors 有权
标题翻译：电子组件包括具有嵌入式电容器的衬底
公开(公告)号：US06611419B1
公开(公告)日：2003-08-26
申请号：US09631037
申请日：2000-07-31
申请人： Kishore K. Chakravorty
发明人： Kishore K. Chakravorty
IPC分类号： H01G4228
CPC分类号： H01L23/50 , H01L23/49822 , H01L2224/05571 , H01L2224/05573 , H01L2224/16225 , H01L2224/16235 , H01L2924/00014 , H01L2924/01078 , H01L2924/09701 , H01L2924/15311 , H05K1/0306 , H05K1/112 , H05K1/162 , H05K1/185 , H05K3/4611 , H05K3/4629 , H05K3/4688 , H05K2201/0187 , H05K2201/049 , H05K2201/10674 , H05K2201/10734 , H01L2224/05599
摘要： To reduce switching noise, the power supply terminals of an integrated circuit die can be coupled to the respective terminals of at least one embedded capacitor in a multilayer ceramic substrate. In one embodiment, the capacitor is formed of at least one high permittivity layer. In another embodiment, several high permittivity layers are interleaved with conductive layers. Alternatively, the capacitor can comprise at least one embedded discrete capacitor. Also described are an electronic system, a data processing system, and various methods of manufacture.
摘要翻译：为了降低开关噪声，集成电路管芯的电源端子可以耦合到多层陶瓷衬底中的至少一个嵌入式电容器的相应端子。在一个实施例中，电容器由至少一个高电容率层形成。在另一个实施例中，几个高介电常数层与导电层交错。或者，电容器可以包括至少一个嵌入式分立电容器。还描述了电子系统，数据处理系统和各种制造方法。

4. 发明授权

US5436504A Interconnect structures having tantalum/tantalum oxide layers 失效
标题翻译：具有钽/钽氧化物层的互连结构
公开(公告)号：US5436504A
公开(公告)日：1995-07-25
申请号：US64794
申请日：1993-05-19
申请人： Kishore K. Chakravorty , Minas H. Tanielian
发明人： Kishore K. Chakravorty , Minas H. Tanielian
IPC分类号： H01L21/288 , H01L21/48 , H01L21/768 , H05K1/02
CPC分类号： H01L21/76879 , H01L21/288 , H01L21/4846
摘要： A method of fabricating a high-density multilayer copper/polyimide interconnect structure utilizing a blanket tantalum/tantalum oxide layer that electrically connects all of the electroplating seed layers to the edge of the substrate; upon completion of the electroplating process, the excess tantalum/tantalum oxide layer is etched off to produce isolated conductor lines. A multilayer copper/polyimide interconnect structure may be fabricated by repeating this fabrication sequence for each layer.
摘要翻译：一种利用覆盖钽/钽氧化物层的高密度多层铜/聚酰亚胺互连结构的方法，所述覆盖钽/钽氧化物层将所有电镀种子层电连接到衬底的边缘; 在电镀工艺完成后，将多余的钽/钽氧化物层蚀刻掉以产生隔离导体线。多层铜/聚酰亚胺互连结构可以通过重复每个层的这种制造顺序来制造。

5. 发明授权

US5112448A Self-aligned process for fabrication of interconnect structures in semiconductor applications 失效
标题翻译：用于制造半导体应用中的互连结构的自对准工艺
公开(公告)号：US5112448A
公开(公告)日：1992-05-12
申请号：US442238
申请日：1989-11-28
申请人： Kishore K. Chakravorty
发明人： Kishore K. Chakravorty
IPC分类号： H01L21/288 , H01L21/48 , H01L21/768 , H05K3/10 , H05K3/24 , H05K3/46
CPC分类号： H01L21/76885 , H01L21/2885 , H01L21/4846 , H01L21/76877 , H05K3/107 , H05K3/243 , H05K3/4644 , Y10S205/917
摘要： A method for fabricating conductors in dielectric trenches in a self-aligned manner. Interconnect modules with a high conductor density are achieved by using a copper-polyimide system as a versatile packaging approach. A photosensitive polyimide is applied to a substrate and lithographically patterned to form polyimide steps having a characteristic positive slope, between which are defined trenches in which the substrate is exposed. A thin electroplating seed layer is deposited over the polyimide steps and the substrate. Copper is electroplated into trenches, but does not plate onto the tops of the polyimide steps, since the electroplating seed layer at that location is not electrically connected to the electroplating seed layer in the bottom of the trenches. The electroplating seed layer on top of the polyimide steps is then removed by chemical etching, plasma machining, or ion-milling. A planar structure is eventually obtained without the use of multiple coatings of polyimide layers or any additional masking layers or lift-off layers.
摘要翻译：一种以自对准方式在介质沟槽中制造导体的方法。具有高导体密度的互连模块通过使用铜 - 聚酰亚胺系统作为通用封装方法来实现。将感光性聚酰亚胺涂布在基板上并进行光刻图案化以形成具有特征正斜率的聚酰亚胺步骤，在其间形成有暴露基板的界定的沟槽。在聚酰亚胺步骤和基底上沉积薄的电镀种子层。由于在该位置处的电镀种子层不与沟槽底部的电镀种子层电连接，所以将铜电镀到沟槽中，但不会沉积在聚酰亚胺步骤的顶部上。然后通过化学蚀刻，等离子体加工或离子研磨去除聚酰亚胺步骤顶部的电镀种子层。最终获得平面结构，而不使用多层聚酰亚胺层或任何附加掩模层或剥离层。

6. 发明授权

US07339798B2 Electronic assemblies and systems comprising interposer with embedded capacitors 有权
标题翻译：电子组件和系统，包括嵌入式电容器的插入器
公开(公告)号：US07339798B2
公开(公告)日：2008-03-04
申请号：US11222320
申请日：2005-09-08
申请人： Kishore K. Chakravorty
发明人： Kishore K. Chakravorty
IPC分类号： H05K7/00 , H05K7/06 , H05K7/08 , H05K7/10
CPC分类号： H01L23/50 , H01L23/642 , H01L2224/05571 , H01L2224/05573 , H01L2224/16225 , H01L2924/00014 , H01L2924/01078 , H01L2924/09701 , H01L2924/15311 , H05K1/141 , H05K1/162 , H01L2224/05599
摘要： To reduce switching noise, the power supply terminals of an integrated circuit die are coupled to the respective terminals of at least one capacitor embedded in an interposer that lies between the die and a substrate. In an embodiment, the interposer is a multilayer ceramic structure that couples power and signal conductors on the die to corresponding conductors on the substrate. The capacitor is formed of at least one high permittivity layer and in an embodiment comprises several high permittivity layers interleaved with conductive layers. Alternatively, the capacitor can comprise at least one embedded discrete capacitor. Also described are an electronic system, a data processing system, and various methods of manufacture.
摘要翻译：为了降低开关噪声，集成电路管芯的电源端子被耦合到嵌入在管芯和衬底之间的插入器中的至少一个电容器的相应端子。在一个实施例中，插入器是将裸片上的功率和信号导体耦合到衬底上相应导体的多层陶瓷结构。电容器由至少一个高电容率层形成，并且在一个实施例中包括与导电层交错的几个高介电常数层。或者，电容器可以包括至少一个嵌入式分立电容器。还描述了电子系统，数据处理系统和各种制造方法。

7. 发明授权

US07049704B2 Flip-chip package integrating optical and electrical devices and coupling to a waveguide on a board 失效
标题翻译：整合光学和电气设备并耦合到板上波导的倒装芯片封装
公开(公告)号：US07049704B2
公开(公告)日：2006-05-23
申请号：US10840017
申请日：2004-05-06
申请人： Kishore K. Chakravorty , Johanna Swan , Brandon C. Barnett , Joseph F. Ahadian , Thomas P. Thomas , Ian Young
发明人： Kishore K. Chakravorty , Johanna Swan , Brandon C. Barnett , Joseph F. Ahadian , Thomas P. Thomas , Ian Young
IPC分类号： H01L29/40
CPC分类号： G02B6/42 , G02B6/4206 , G02B6/4212 , G02B6/4214 , G02B6/4231 , G02B6/43 , H05K1/0274 , H05K3/3436 , H05K2201/10121 , H05K2201/10734
摘要： A package allowing both electrical and optical coupling between one or more integrated circuits and a printed circuit board (PCB) has an optical waveguide structure in addition to electrical connections. An optically active device is flip-chip bonded directly to an integrated circuit using solder bump technology. The optically active device has a lens directly attached to it to facilitate optical coupling to the optical waveguide. The integrated circuit is flip-chip bonded to a Ball Grid Array (BGA) package. The BGA package is bonded to the PCB using solder reflow technology.
摘要翻译：允许一个或多个集成电路和印刷电路板（PCB）之间的电和光耦合的封装除了电连接之外还具有光波导结构。使用焊料凸块技术将光学有源器件直接贴合到集成电路上。光学器件具有直接连接到其上的透镜，以便于光耦合到光波导。集成电路倒装芯片结合到球栅阵列（BGA）封装。使用焊锡回流技术将BGA封装结合到PCB。

8. 发明授权

US06775150B1 Electronic assembly comprising ceramic/organic hybrid substrate with embedded capacitors and methods of manufacture 失效
标题翻译：包括具有嵌入式电容器的陶瓷/有机混合基板和制造方法的电子组件
公开(公告)号：US06775150B1
公开(公告)日：2004-08-10
申请号：US09650566
申请日：2000-08-30
申请人： Kishore K. Chakravorty , Paul H. Wermer , David G. Figueroa , Debabrata Gupta
发明人： Kishore K. Chakravorty , Paul H. Wermer , David G. Figueroa , Debabrata Gupta
IPC分类号： H05K118
CPC分类号： H01L23/49822 , H01L23/50 , H01L2224/16225 , H01L2924/00014 , H01L2924/01004 , H01L2924/01077 , H01L2924/01078 , H01L2924/01087 , H01L2924/09701 , H01L2924/15174 , H01L2924/3011 , H01L2924/3511 , H05K1/0231 , H05K1/0306 , H05K1/141 , H05K1/162 , H05K1/185 , H05K3/4605 , H05K3/4688 , H05K2201/0154 , H05K2201/09309 , H05K2201/10674 , H01L2224/0401
摘要： To reduce switching noise, the power supply terminals of an integrated circuit die are coupled to the respective terminals of at least one embedded capacitor in a multilayer ceramic/organic hybrid substrate. In one embodiment, a ceramic portion of the substrate includes at least one capacitor formed of a high permittivity layer sandwiched between conductive planes. An organic portion of the substrate includes suitable routing and fan-out of power and signal conductors. The organic portion includes a build-up of multiple layers of organic material overlying the ceramic portion. Also described are an electronic system, a data processing system, and various methods of manufacture.
摘要翻译：为了降低开关噪声，集成电路管芯的电源端子耦合到多层陶瓷/有机混合衬底中的至少一个嵌入式电容器的相应端子。在一个实施例中，衬底的陶瓷部分包括由夹在导电平面之间的高电容率层形成的至少一个电容器。基板的有机部分包括电源和信号导体的合适布线和扇出。有机部分包括覆盖陶瓷部分的多层有机材料的堆积。还描述了电子系统，数据处理系统和各种制造方法。

9. 发明授权

US06764366B1 Electrode structure and method for forming electrode structure for a flat panel display 有权
标题翻译：用于形成平板显示器的电极结构的电极结构和方法
公开(公告)号：US06764366B1
公开(公告)日：2004-07-20
申请号：US09999755
申请日：2001-10-31
申请人： Jueng Gil Lee , Christopher J. Spindt , Johan Knall , Matthew A. Bonn , Kishore K. Chakravorty
发明人： Jueng Gil Lee , Christopher J. Spindt , Johan Knall , Matthew A. Bonn , Kishore K. Chakravorty
IPC分类号： H01J902
CPC分类号： H01J9/148 , H01J29/467
摘要： An electrode structure for a display that includes lower electrodes and upper electrodes. In one embodiment, lower and upper electrodes are formed of either an aluminum alloy or a silver alloy. In another embodiment, upper and lower electrodes are formed using a metal alloy layer over which a cladding layer is deposited. A silicon nitride passivation layer is used to protect the upper electrodes from damage in subsequent process steps. Various other materials and structures are also disclosed that protect the upper electrodes from damage in subsequent process steps.
摘要翻译：一种用于显示器的电极结构，包括下电极和上电极。在一个实施例中，下电极和上电极由铝合金或银合金形成。在另一个实施例中，上部和下部电极使用沉积有包层的金属合金层形成。使用氮化硅钝化层来保护上电极在后续工艺步骤中不被损坏。还公开了各种其它材料和结构，其保护上电极在后续工艺步骤中不被损坏。

10. 发明授权

US06532143B2 Multiple tier array capacitor 有权
标题翻译：多层阵列电容
公开(公告)号：US06532143B2
公开(公告)日：2003-03-11
申请号：US09751612
申请日：2000-12-29
申请人： David G. Figueroa , Kishore K. Chakravorty , Huong T. Do , Larry Eugene Mosley , Jorge Pedro Rodriguez , Ken Brown
发明人： David G. Figueroa , Kishore K. Chakravorty , Huong T. Do , Larry Eugene Mosley , Jorge Pedro Rodriguez , Ken Brown
IPC分类号： H01G430
CPC分类号： H01G4/30 , H01L23/642 , H01L2224/16225 , H01L2924/00014 , H05K1/0298 , H05K1/162 , H01L2224/0401
摘要： A capacitor includes multiple tiers (302, 304, 306, 1210, 1212, 1310, 1312, 1380, FIGS. 3, 12, 13), which provide capacitance to a load at different inductance values. Each tier includes multiple layers (311-325, 1220, 1222, 1320, 1322, 1382, FIGS. 3, 12, 13) of patterned conductive material, which are separated by layers of dielectric material. In one embodiment, tiers are stacked in a vertical direction, and are electrically connected through vias (330, 332, 334, 1230, 1232, FIGS. 3, 12) that extend through some or all of the tiers. In another embodiment, one or more tiers (1310, 1312, FIG. 13) are located in a center region (1404, FIG. 14) of the capacitor, and one or more other tiers (1380, FIG. 13) are located in a peripheral region (1408, FIG. 14) of the capacitor. In that embodiment, the center tiers and peripheral tiers are electrically connected through one or more additional layers (1370, FIG. 13) of patterned conductive material. The capacitors of the various embodiments can be used as discrete devices, which are mountable on or embeddable within a housing (e.g., a package, interposer, socket or PC board), or they can be integrally fabricated within the housing.
摘要翻译：电容器包括多层（302,304,306,1210,1212,1310,1312,1380，图3,12,13），其以不同的电感值向负载提供电容。每个层包括被介电材料层隔开的图案化导电材料的多层（311-325,1220,1222,1320,1322,1382，图3,12,13）。在一个实施例中，层是沿垂直方向堆叠的，并且通过延伸穿过一些或所有层的通孔（330,332,334,1230,1232，图3,12）电连接。在另一个实施例中，一个或多个层（1310,1312，图13）位于电容器的中心区域（1404，图14）中，并且一个或多个其他层（图13中的1380）位于电容器的外围区域（1408，图14）。在该实施例中，中心层和外围层通过图案化导电材料的一个或多个附加层（1370，图13）电连接。各种实施例的电容器可以用作可安装在壳体（例如，封装，插入件，插座或PC板）中或嵌入其中的分立器件，或者它们可以一体地制造在壳体内。

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