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61. 发明授权

US08288800B2 Hybrid transistor 有权
标题翻译：混合晶体管
公开(公告)号：US08288800B2
公开(公告)日：2012-10-16
申请号：US12651487
申请日：2010-01-04
申请人： Ming Zhu , Chun Shan Yin , Elgin Quek , Shyue Seng Tan
发明人： Ming Zhu , Chun Shan Yin , Elgin Quek , Shyue Seng Tan
IPC分类号： H01L29/66
CPC分类号： H01L29/7885 , H01L21/28273 , H01L29/66795 , H01L29/66825 , H01L29/785
摘要： A method of forming a device is disclosed. The method includes providing a substrate having an active area. A gate is formed on the substrate. First and second current paths through the gate are formed. The first current path serves a first purpose and the second current path serves a second purpose. The gate controls selection of the current paths.
摘要翻译：公开了一种形成装置的方法。该方法包括提供具有活性区域的基底。在基板上形成栅极。形成通过栅极的第一和第二电流路径。第一电流通路用于第一目的，第二电流通路用于第二目的。门控制当前路径的选择。

62. 发明申请

US20120223394A1 SELF-ALIGNED CONTACT FOR REPLACEMENT METAL GATE AND SILICIDE LAST PROCESSES 有权
标题翻译：用于替换金属门和硅化物最后工艺的自对准接触件
公开(公告)号：US20120223394A1
公开(公告)日：2012-09-06
申请号：US13041134
申请日：2011-03-04
申请人： Eng Huat Toh , Elgin Quek
发明人： Eng Huat Toh , Elgin Quek
IPC分类号： H01L27/088 , H01L21/28
CPC分类号： H01L27/088 , H01L21/28518 , H01L21/76801 , H01L21/76816 , H01L21/76834 , H01L21/76897 , H01L21/823475 , H01L29/78
摘要： A high-K/metal gate semiconductor device is provided with larger self-aligned contacts having reduced resistance. Embodiments include forming a first high-k metal gate stack on a substrate between source/drain regions, a second high-k metal gate stack on an STI region, and a first ILD between the metal gate stacks, forming an etch stop layer and a second ILD sequentially over the substrate, with openings in the second ILD over the metal gate stacks, forming spacers on the edges of the openings, forming a third ILD over the second ILD and the spacers, removing the first ILD over the source/drain regions, removing the etch stop layer, the second ILD, and the third ILD over the source/drain regions, adjacent the spacers, and over a portion of the spacers, forming first trenches, removing the third ILD over the second high-k metal gate stack and over a portion of the spacers, forming second trenches, and forming contacts in the first and second trenches.
摘要翻译：高K /金属栅极半导体器件具有较大的自对准触点，电阻降低。实施例包括在源极/漏极区域之间的衬底上形成第一高k金属栅极堆叠，在STI区域上形成第二高k金属栅极堆叠以及在金属栅极堆叠之间形成第一ILD，形成蚀刻停止层和在衬底上顺序地具有第二ILD，在金属栅堆叠上的第二ILD中具有开口，在开口的边缘上形成间隔物，在第二ILD和间隔物上形成第三ILD，在源/漏区上去除第一ILD 在邻近间隔物的源极/漏极区域上以及在间隔物的一部分上方去除蚀刻停止层，第二ILD和第三ILD，形成第一沟槽，在第二高k金属栅极上去除第三ILD 堆叠和一部分间隔物，形成第二沟槽，并在第一和第二沟槽中形成接触。

63. 发明申请

US20120038009A1 Novel methods to reduce gate contact resistance for AC reff reduction 有权
标题翻译：降低栅极接触电阻的新方法
公开(公告)号：US20120038009A1
公开(公告)日：2012-02-16
申请号：US12806354
申请日：2010-08-11
申请人： Eng Huat Toh , Elgin Quek , Chunshan Yin , Chung Foong Tan , Jae Gon Lee
发明人： Eng Huat Toh , Elgin Quek , Chunshan Yin , Chung Foong Tan , Jae Gon Lee
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/28079 , H01L21/28088 , H01L21/28097 , H01L29/495 , H01L29/4966 , H01L29/4975 , H01L29/517
摘要： A method (and semiconductor device) of fabricating a semiconductor device provides a field effect transistor (FET) with reduced gate contact resistance (and series resistance) for improved device performance. An impurity is implanted or deposited in the gate stack in an impurity region between the metal gate electrode and the gate contact layer. An anneal process is performed that converts the impurity region into a segregation layer which lowers the schottky barrier height (SBH) of the interface between the metal gate electrode (e.g., silicide) and gate contact layer (e.g., amorphous silicon). This results in lower gate contact resistance and effectively lowers the device's AC Reff.
摘要翻译：制造半导体器件的方法（和半导体器件）提供具有降低的栅极接触电阻（和串联电阻）的场效应晶体管（FET），以提高器件性能。在金属栅极电极和栅极接触层之间的杂质区域中将杂质注入或沉积在栅极堆叠中。执行退火处理，其将杂质区域转换成偏析层，其降低金属栅电极（例如，硅化物）和栅极接触层（例如非晶硅）之间的界面的肖特基势垒高度（SBH）。这导致较低的栅极接触电阻并有效降低器件的AC Reff。

64. 发明申请

US20120018815A1 Semiconductor device with reduced contact resistance and method of manufacturing thereof 有权
标题翻译：具有降低的接触电阻的半导体器件及其制造方法
公开(公告)号：US20120018815A1
公开(公告)日：2012-01-26
申请号：US12804487
申请日：2010-07-22
申请人： Eng Huat Toh , Jae Gon Lee , Chung Foong Tan , Shiang Yang Ong , Elgin Quek
发明人： Eng Huat Toh , Jae Gon Lee , Chung Foong Tan , Shiang Yang Ong , Elgin Quek
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7833 , H01L21/26506 , H01L21/28556 , H01L21/324 , H01L29/0847 , H01L29/41725 , H01L29/66575
摘要： A method (and semiconductor device) of fabricating a semiconductor device provides a filed effect transistor (FET) with reduced contact resistance (and series resistance) for improved device performance. An impurity is implanted in the source/drain (S/D) regions after contact silicide formation and a spike anneal process is performed that lowers the schottky barrier height (SBH) of the interface between the silicide and the lower junction region of the S/D regions. This results in lower contact resistance and reduces the thickness (and Rs) of the region at the silicide-semiconductor interface.
摘要翻译：制造半导体器件的方法（和半导体器件）提供具有降低的接触电阻（和串联电阻）的场效应晶体管（FET），以提高器件性能。在接触硅化物形成之后，在源极/漏极（S / D）区域中注入杂质，并且进行尖峰退火处理，其降低硅化物和S / D层的下部结区之间的界面的肖特基势垒高度（SBH） D区。这导致较低的接触电阻并且减小了硅化物半导体界面处的区域的厚度（和Rs）。

65. 发明申请

US20070132032A1 Selective stress relaxation of contact etch stop layer through layout design 有权
标题翻译：通过布局设计，接触蚀刻停止层的选择性应力松弛
公开(公告)号：US20070132032A1
公开(公告)日：2007-06-14
申请号：US11302035
申请日：2005-12-13
申请人： Lee Teo , Elgin Quek , Dong Sohn
发明人： Lee Teo , Elgin Quek , Dong Sohn
IPC分类号： H01L29/78 , H01L21/8238
CPC分类号： H01L21/823807 , H01L21/76816 , H01L21/76829 , H01L21/823814 , H01L21/823871 , H01L27/0207 , H01L29/665 , H01L29/6659 , H01L29/7843
摘要： A structure and method of fabrication of a semiconductor device, where a stress layer is formed over a MOS transistor to put either tensile stress or compressive stress on the channel region. The parameters such as the location and area of the contact hole thru the stress layer are chosen to produce a desired amount of stress to improve device performance. In an example embodiment for a tensile stress layer, the PMOS S/D contact area is larger than the NMOS S/D contact area so the tensile stress on the PMOS channel is less than the tensile stress on the NMOS channel. In an example embodiment for a compressive stress layer, the NMOS contact area is larger than the PMOS contact area so that the compressive stress on the NMOS channel is less than the compressive stress on the PMOS channel.
摘要翻译：一种制造半导体器件的结构和方法，其中在MOS晶体管上形成应力层以在沟道区域上施加拉伸应力或压应力。选择诸如通过应力层的接触孔的位置和面积的参数以产生期望量的应力以改善器件性能。在拉伸应力层的示例实施例中，PMOS S / D接触面积大于NMOS S / D接触面积，因此PMOS沟道上的拉伸应力小于NMOS沟道上的拉伸应力。在压应力层的示例实施例中，NMOS接触面积大于PMOS接触面积，使得NMOS沟道上的压应力小于PMOS沟道上的压应力。

66. 发明申请

US20070117326A1 MATERIAL ARCHITECTURE FOR THE FABRICATION OF LOW TEMPERATURE TRANSISTOR 审中-公开
标题翻译：用于制造低温晶体管的材料结构
公开(公告)号：US20070117326A1
公开(公告)日：2007-05-24
申请号：US11625789
申请日：2007-01-22
申请人： Chung Tan , Jinping Liu , Hyeokjae Lee , Keng Tee , Elgin Quek
发明人： Chung Tan , Jinping Liu , Hyeokjae Lee , Keng Tee , Elgin Quek
IPC分类号： H01L27/148 , H01L21/336 , H01L21/425
CPC分类号： H01L21/26506 , H01L21/26513 , H01L21/2658 , H01L21/823807 , H01L21/823814 , H01L29/1054 , H01L29/1083 , H01L29/6659
摘要： A structure and method for forming a carbon-containing layer in at least a portion of the end of range regions of implanted PAI and/or doped regions. The C-containing layer/region getters defects from the implanted PAI region or doped region. Example embodiments show a C-containing layer under at FET. Other example embodiments show an implanted C-containing regions implanted into the EOR region of implanted doped regions, such as pocket regions, S/D regions and SDE regions. Low temperature anneals can be used because the carbon-containing layer reduces defects.
摘要翻译：在植入的PAI和/或掺杂区域的范围区域的末端的至少一部分中形成含碳层的结构和方法。含C层/区域从植入的PAI区域或掺杂区域吸收缺陷。示例性实施例示出了在FET下面的含C层。其它示例性实施方案显示了植入到植入的掺杂区域例如口袋区域，S / D区域和SDE区域的EOR区域中的植入的含C区域。可以使用低温退火，因为含碳层减少了缺陷。

67. 发明申请

US20060006427A1 Material architecture for the fabrication of low temperature transistor 有权
标题翻译：用于制造低温晶体管的材料结构
公开(公告)号：US20060006427A1
公开(公告)日：2006-01-12
申请号：US10886442
申请日：2004-07-07
申请人： Chung Tan , Jinping Liu , Hyeokjae Lee , Kheng Tee , Elgin Quek
发明人： Chung Tan , Jinping Liu , Hyeokjae Lee , Kheng Tee , Elgin Quek
IPC分类号： H01L27/148 , H01L21/425
CPC分类号： H01L29/6659 , H01L21/26506 , H01L21/26513 , H01L21/823807 , H01L21/823814 , H01L29/1054 , H01L29/1083
摘要： A structure and method for forming a carbon-containing layer in at least a portion of the end of range regions of implanted PAI and/or doped regions. The C-containing layer/region getters defects from the implanted PAI region or doped region. Example embodiments show a C-containing layer under at FET. Other example embodiments show an implanted C-containing regions implanted into the EOR region of implanted doped regions, such as pocket regions, S/D regions and SDE regions. Low temperature anneals can be used because the carbon-containing layer reduces defects.
摘要翻译：在植入的PAI和/或掺杂区域的范围区域的末端的至少一部分中形成含碳层的结构和方法。含C层/区域从植入的PAI区域或掺杂区域吸收缺陷。示例性实施例示出了在FET下面的含C层。其它示例性实施方案显示了植入到植入的掺杂区域例如口袋区域，S / D区域和SDE区域的EOR区域中的植入的含C区域。可以使用低温退火，因为含碳层减少了缺陷。

68. 发明申请

US20050101083A1 Method to produce dual gates (one metal and one poly or metal silicide) for CMOS devices using sputtered metal deposition, metallic ion implantation, or silicon implantation, and laser annealing 审中-公开
公开(公告)号：US20050101083A1
公开(公告)日：2005-05-12
申请号：US10995849
申请日：2004-11-23
申请人： Chew Ang , Eng-Hua Lim , Randall Cha , Jia Zheng , Elgin Quek , Mei-Sheng Zhou , Daniel Yen
发明人： Chew Ang , Eng-Hua Lim , Randall Cha , Jia Zheng , Elgin Quek , Mei-Sheng Zhou , Daniel Yen
IPC分类号： H01L21/268 , H01L21/28 , H01L21/8238 , H01L29/49
CPC分类号： H01L29/4933 , H01L21/268 , H01L21/28061 , H01L21/823842
摘要： A method of fabricating first and second gates comprising the following steps. A substrate having a gate dielectric layer formed thereover is provided. The substrate having a first gate region and a second gate region. A thin first gate layer is formed over the gate dielectric layer. The thin first gate layer within the second gate region is masked to expose a portion of the thin first gate layer within the first gate region. The exposed portion of the thin first gate layer is converted to a thin third gate layer portion. A second gate layer is formed over the thin first and third gate layer portions. The second gate layer and the first and third gate layer portions are patterned to form a first gate within first gate region and a second gate within second gate region.

69. 发明授权

US06380610B1 Dislocation free local oxidation of silicon with suppression of narrow space field oxide thinning effect 失效
标题翻译：无位错局部氧化硅，抑制窄空间场氧化物稀化效应
公开(公告)号：US06380610B1
公开(公告)日：2002-04-30
申请号：US09257838
申请日：1999-02-25
申请人： Igor V. Peidous , Elgin Quek , Konstantin V. Loiko , David Yeo Yong Hock
发明人： Igor V. Peidous , Elgin Quek , Konstantin V. Loiko , David Yeo Yong Hock
IPC分类号： H01L2358
CPC分类号： H01L21/32 , H01L21/0332 , H01L21/76202 , Y10S438/95
摘要： A novel design of an oxidation mask for improved control of birds beak and more specifically for tailoring and smoothing the field oxide isolation profile in the vicinity of the birds beak. The mask design is particularly advantageous for narrow field isolation spacings found in sub half-micron integrated circuit technology. The mask uses a thin silicon nitride foot along its lower edge to allow nominal expansion of the oxide during the early stages of oxidation, thereby permitting in-situ stress relief as well as a smoothing of the oxide profile. A cantilevered portion of a second, thicker silicon nitride layer suppresses the upward movement of the flexible foot during the later stages of the oxidation when the growth rate has slowed, thereby inhibiting the growth of the birds beak. Shear stresses responsible for dislocation generation are reduced as much as fifty fold. This stress reduction is accompanied by an improvement in surface topography as well as suppression of the narrow oxide thinning effect.
摘要翻译：一种用于改善鸟喙控制的氧化面罩的新颖设计，更具体地用于在鸟喙附近调整和平滑场氧化物隔离轮廓。掩模设计对于半微米集成电路技术中的窄场隔离间隔特别有利。掩模在其下边缘处使用薄的氮化硅脚，以允许在氧化的早期阶段氧化物的标称膨胀，从而允许原位应力消除以及氧化物轮廓的平滑化。第二较厚的氮化硅层的悬臂部分在生长速度减慢时在氧化的后期阶段抑制柔性脚的向上移动，由此抑制鸟喙的生长。负责位错生成的剪切应力减少了五十倍。这种应力降低伴随着表面形貌的改善以及窄的氧化物稀化效应的抑制。

70. 发明授权

US09034711B2 LDMOS with two gate stacks having different work functions for improved breakdown voltage 有权
标题翻译： LDMOS具有两个栅极叠层，具有不同的功能，可提高击穿电压
公开(公告)号：US09034711B2
公开(公告)日：2015-05-19
申请号：US13046332
申请日：2011-03-11
申请人： Eng Huat Toh , Jae Gon Lee , Chung Foong Tan , Elgin Quek
发明人： Eng Huat Toh , Jae Gon Lee , Chung Foong Tan , Elgin Quek
IPC分类号： H01L21/336 , H01L29/78 , H01L29/423 , H01L29/51 , H01L29/49 , H01L29/66
CPC分类号： H01L29/7816 , H01L29/42364 , H01L29/42368 , H01L29/42372 , H01L29/495 , H01L29/4958 , H01L29/4966 , H01L29/512 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66545 , H01L29/66681
摘要： An LDMOS is formed with a second gate stack over the n− drift region, having a common gate electrode with the gate stack, and having a higher work function than the gate stack. Embodiments include forming a first conductivity type well, having a source, surrounded by a second conductivity type well, having a drain, in a substrate, forming first and second gate stacks on the substrate over a portion of the first well and a portion of the second well, respectively, the first and second gate stacks sharing a common gate electrode, and tuning the work functions of the first and second gate stacks to obtain a higher work function for the second gate stack. Other embodiments include forming the first gate stack with a first high-k dielectric and the second gate stack with a second high-k dielectric, and forming the first and second gate stacks with asymmetric dielectrics.
摘要翻译： LDMOS在n漂移区上形成有第二栅极堆叠，其具有与栅极堆叠相同的公共栅电极，并且具有比栅极堆叠更高的功函数。实施例包括形成第一导电类型的阱，具有由第二导电类型阱包围的源，在衬底中具有漏极，在衬底上在第一阱的一部分上形成第一和第二栅极叠层，第二阱，第一和第二栅极堆叠共享公共栅极电极，并且调谐第一和第二栅极堆叠的功函数以获得用于第二栅极堆叠的较高功函数。其他实施例包括用第一高k电介质形成第一栅极堆叠，以及用第二高k电介质形成第二栅极堆叠，以及用不对称电介质形成第一和第二栅极堆叠。

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