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61. 发明专利

JPS5743466A Insulated gate type field effect transistor and manufacture thereof 失效
标题翻译：绝缘栅型场效应晶体管及其制造
公开(公告)号：JPS5743466A
公开(公告)日：1982-03-11
申请号：JP11872880
申请日：1980-08-28
申请人： Toshiba Corp
发明人： IWAHASHI HIROSHI , ASANO MASAMICHI
IPC分类号： H01L29/78 , H01L29/08
CPC分类号： H01L29/0847
摘要： PURPOSE:To enable the high speed operation of a field effect transistor by decreasing the extending amount of source and drain regions under gate electrodes. CONSTITUTION:When a source 17 and a drain 18 are formed, the extending amounts of the source and drain regions under the polysilicon layer 13 of these regions becomes approx. 80% of the depthwise extension in a substrate 11, but since the layer 13 is etched to contract its width, the extensions of the source 17 and drain 18 under the polysilicon layer (a gate electrode) 13 becomes shorter than the 80% of the depthwise extension in the substrate 11. Accordingly, capacities C2, C3 become small, thereby enabling the high speed operation of an IGFET circuit. Since the depths of the source and drain regions can be sufficiently increased, the resistance of these regions can be decrased, and the punch-through phenomenon of the electrodes can be prevented.
摘要翻译：目的：通过减小栅电极下的源极和漏极区域的扩展量来实现场效应晶体管的高速运行。构成：当形成源极17和漏极18时，这些区域的多晶硅层13下面的源极和漏极区域的延伸量变成约。在衬底11中80％的深度延伸，但由于蚀刻层13以使其宽度收缩，所以在多晶硅层（栅电极）13下方的源极17和漏极18的延伸部分变得比80％因此，电容C2，C3变小，能够实现IGFET电路的高速运转。由于源极和漏极区域的深度可以充分增加，所以可以降低这些区域的电阻，并且可以防止电极的穿通现象。

62. 发明专利

JPS5735422A Semiconductor circuit 失效
标题翻译：半导体电路
公开(公告)号：JPS5735422A
公开(公告)日：1982-02-26
申请号：JP11091280
申请日：1980-08-12
申请人： Toshiba Corp
发明人： IWAHASHI HIROSHI , ASANO MASAMICHI
IPC分类号： G11C17/00 , G11C16/06 , G11C17/18 , H01L21/822 , H01L21/8236 , H01L27/04 , H01L27/088 , H01L29/78 , H03K17/10 , H03K17/687 , H03K17/693 , H03K17/74 , H03K19/00
CPC分类号： H03K17/102
摘要： PURPOSE:To achieve a sufficiently high voltage at an output terminal, by using a diode for an element which leads a high voltage given at a signal and power supply terminal to an output terminal. CONSTITUTION:When a signal and power supply terminal (b) is used as a signal terminal, if a signal B is taken as 1, the size of each transistor can be set so that the potential at a terminal (a) can be kept near a power supply voltage Vc independently of 1.0 of a signal A. In this case, almost no current flows via a diode 31 until the diode 31 breaks down to the potential VF+ potential at terminal (a) at the terminal (b), and the terminal (b) can be used as a signal line. On the other hand, when the terminal (b) is used for the power supply, the signal B is taken as 0, a MOSFET4 is cut off, and a current from a high power supply VP to a lower power supply VC does not flow. In this case, a sufficiently higher voltage being VP-VF can be obtained at an output terminal O.
摘要翻译：目的：为了在输出端子上实现足够高的电压，通过将二极管用于将信号和电源端子上给出的高电压引导到输出端子的元件。构成：当信号和电源端子（b）用作信号端子时，如果信号B取为1，则可以设置每个晶体管的尺寸，使端子（a）的电位可以保持在接近独立于信号A的1.0的电源电压Vc。在这种情况下，几乎没有电流通过二极管31流动，直到二极管31在端子（b）处端子（a）处分解为电位VF +电位，并且端子（b）可以用作信号线。另一方面，当端子（b）用于电源时，信号B取为0，MOSFET4被截止，并且从高电源VP到下电源VC的电流不流动。在这种情况下，可以在输出端子O处获得足够高的VP-VF电压。

63. 发明专利

JPS5726925A Pulse generating circuit 失效
标题翻译：脉冲发生电路
公开(公告)号：JPS5726925A
公开(公告)日：1982-02-13
申请号：JP9298981
申请日：1981-06-18
申请人： Toshiba Corp
发明人： IWAHASHI HIROSHI , ASANO MASAMICHI
IPC分类号： H03K5/1532 , G11C11/41 , H03K5/00
CPC分类号： H03K5/00
摘要： PURPOSE:To decrease the number of elements and to make the response speed of an output signal to an input signal faster, by controlling the switching of 2 pairs of FETs with a delayed output of the input signal. CONSTITUTION:An inverting input signal inversion A'0 with different phase from an input signal A'0 is applied to the drain of enhancement type FETs 43, 44. The input signal A'0 is inverted and delayed at a resistor 46 and a capacitor 47, it is again inverted, it is applied to the gate of the FET44 and inverted and applied to the gate of a transistor 43. A pulse signal W0 is outputted from the connecting point of the sources of the transistors 43, 44.
摘要翻译：目的：通过控制输入信号的延迟输出的2对FET的切换，减少元件数量并使输出信号对输入信号的响应速度更快。构成：与输入信号A'0不同相位的反相输入信号反相A'0被施加到增强型FET43,44的漏极。输入信号A'0在电阻器46和电容器如图47所示，它再次被反相，被施加到FET44的栅极并反相并施加到晶体管43的栅极。脉冲信号W0从晶体管43,44的源极的连接点输出。

64. 发明专利

JP2010207092A Four-phase clock driven charge pump circuit 有权
标题翻译：四相时钟驱动充电泵电路
公开(公告)号：JP2010207092A
公开(公告)日：2010-09-16
申请号：JP2010141023
申请日：2010-06-21
申请人： Toppan Printing Co Ltd , Toshiba Corp , 凸版印刷株式会社 , 株式会社東芝
发明人： ASANO MASAMICHI , CHIN GYOSHO , MATOBA SHINJI , KURIYAMA MASAO , KATO HIDEO
IPC分类号： H02M3/07
摘要： PROBLEM TO BE SOLVED: To avoid breakdown of elements caused by application of a high voltage.
SOLUTION: A four-phase clock driven charge pump circuit includes capacitors C1-C(n-3), Cp1-Cp3 with one end of them to be connected, respectively, to the connective points of Nch transistors T1-T(n+1) connected in series and capacitors Cs1-Csn, Cq with one end of them to be connected, respectively, to the gates of Nch transistors T1-T(n+1). The voltage having an amplitude equal to the amplitude Vcc of a clock signal obtained through the use of a quadruple booster circuit after quadruplicating the amplitude Vcc is supplied to the other end of the capacitors C1-C(n-3). The voltage having an amplitude equal to the amplitude Vcc obtained through the use of a double booster circuit after doubling the amplitude Vcc is supplied to the other end of the capacitor Cp. The voltage having an amplitude equal to the amplitude Vcc obtained through the use of the quadruple booster circuit after quadruplicating the amplitude Vcc is supplied to the other end of the capacitors Cs1-Cs(n-3). The voltage having an amplitude equal to the amplitude Vcc obtained through the use of the quadruple booster circuit after quadruplicating the amplitude Vcc is supplied to the other end of the capacitor Cq.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：避免因应用高电压引起的元件故障。解决方案：四相时钟驱动电荷泵电路包括分别连接到Nch晶体管T1-T（n-3）的连接点的电容器C1-C（n-3），Cp1-Cp3， n + 1）和电容器Cs1-Csn，Cq分别与Nch晶体管T1-T（n + 1）的栅极连接。电容器C1-C（n-3）的另一端具有等于通过使用四次升压电路而获得的时钟信号的振幅Vcc的电压。具有等于振幅Vcc加倍后通过使用双升压电路获得的振幅Vcc的电压被提供给电容器Cp的另一端。振幅等于振幅Vcc一式四份后通过使用四极升压电路获得的振幅Vcc的电压被提供给电容器Cs1-Cs（n-3）的另一端。具有等于振幅Vcc一倍大的通过使用四极升压电路获得的振幅Vcc的电压被提供给电容器Cq的另一端。版权所有（C）2010，JPO＆INPIT

65. 发明专利

JP2007164842A Nonvolatile memory 有权
标题翻译：非易失性存储器
公开(公告)号：JP2007164842A
公开(公告)日：2007-06-28
申请号：JP2005356532
申请日：2005-12-09
申请人： Toppan Printing Co Ltd , Toshiba Corp , 凸版印刷株式会社 , 株式会社東芝
发明人： HIRANO MAKOTO , ASANO MASAMICHI , KATO HIDEO , SAITO SAKATOSHI
IPC分类号： G11C16/06
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile memory capable of reducing the chip area of a reference side, and performing high-speed reading. SOLUTION: A signal EQ is started simultaneously with a precharging start. Thus, transistors 201 to 328 and R201 to 232 are turned ON, and data lines HON1 to HON128 and reference lines REF1 to REF32 are quickly charged by a precharge circuit 401 via a common line COM. As the data lines and the reference lines are connected in common via the transistors 201 to 328 and R201 to R232 to be equalized, the data lines and the reference lines are uniformly charged. As the data lines and the reference lines are uniformly charged at a high speed, high-speed reading is carried out within a short time. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种能够减小参考侧的芯片面积并进行高速读取的非易失性存储器。
解决方案：信号EQ与预充电开始同时启动。因此，晶体管201至328和R201至232导通，并且数据线HON1至HON128和参考线REF1至REF32由预充电电路401经由公共线COM快速充电。由于数据线和参考线通过晶体管201至328和R201至R232共同连接以进行均衡，因此数据线和参考线均匀充电。由于数据线和参考线以高速均匀充电，所以在短时间内进行高速读取。版权所有（C）2007，JPO＆INPIT

66. 发明专利

JP2006101627A Two-phase clock driven charge pump circuit, four-phase clock driven charge pump circuit, and voltage boosting circuit 有权
标题翻译：两相时钟驱动充电泵电路，四相时钟驱动充电泵电路和电压升压电路
公开(公告)号：JP2006101627A
公开(公告)日：2006-04-13
申请号：JP2004284120
申请日：2004-09-29
申请人： Toppan Printing Co Ltd , Toshiba Corp , 凸版印刷株式会社 , 株式会社東芝
发明人： ASANO MASAMICHI , CHIN GIYOUSHIYOU , MATOBA SHINJI , KURIYAMA MASAO , KATO HIDEO
IPC分类号： H02M3/07 , H03K17/06 , H03K17/08 , H03K17/687 , H03K19/094
摘要： PROBLEM TO BE SOLVED: To avoid damages to an element due to the application of a high voltage. SOLUTION: A charge pump circuit has n-channel transistors T1-T(n+1) connected in series, and capacitors C1-C(n-1), Cp. The other end of the capacitors C1-C(n-1) other than a last stage is supplied with a voltage, whose amplitude is 2×Vcc level acquired by multiplying the amplitude Vcc of a clock signal by 2, using voltage doubler circuits A1-A(n-1). The other end of the capacitor Cp in the last stage is supplied with the clock signal CLK whose amplitude is of Vcc level. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：避免因施加高电压而损坏元件。解决方案：电荷泵电路具有串联连接的n沟道晶体管T1-T（n + 1）和电容器C1-C（n-1），Cp。电容器C1-C（n-1）的另一端不是最后一级被提供一个电压，其振幅是通过将时钟信号的振幅Vcc乘以2获得的2×Vcc电平，使用倍压器电路A1 -A（N-1）。在最后级的电容器Cp的另一端提供振幅为Vcc电平的时钟信号CLK。版权所有（C）2006，JPO＆NCIPI

67. 发明专利

JP2006099862A Sense amplifier circuit 有权
标题翻译：感应放大器电路
公开(公告)号：JP2006099862A
公开(公告)日：2006-04-13
申请号：JP2004284121
申请日：2004-09-29
申请人： Toppan Printing Co Ltd , Toshiba Corp , 凸版印刷株式会社 , 株式会社東芝
发明人： ASANO MASAMICHI , MATSUDA HIROYUKI , HONDA YASUHIKO , KATO HIDEO
IPC分类号： G11C16/06 , G11C16/04
摘要： PROBLEM TO BE SOLVED: To perform high-speed reading by shortening the period of overcharging. SOLUTION: This sense amplifier circuit comprises a current mirror circuit 1, a precharge circuit 2, and a load circuit 3 whose output parts are connected to the input part of the input circuit side of the current mirror circuit 1, a precharge circuit 2R and a load circuit 3R whose output parts are connected to the input part of the comparator circuit side of the current mirror circuit 1. Counter capacitor circuits 8 and 8R are provided to cancel the gate coupling of Pch transistors PTR2a and PRT2Rb constituting the precharge circuits 2 and 2R. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：通过缩短过充电周期来执行高速读取。解决方案：该感测放大器电路包括电流镜电路1，预充电电路2和负载电路3，其输出部分连接到电流镜电路1的输入电路侧的输入部分，预充电电路 2R和负载电路3R，其输出部分连接到电流镜电路1的比较器电路侧的输入部分。提供反电容电路8和8R以消除构成预充电电路的Pch晶体管PTR2a和PRT2Rb的栅极耦合 2和2R。版权所有（C）2006，JPO＆NCIPI

68. 发明专利

JP2003068100A Nonvolatile memory 有权
标题翻译：非易失性存储器
公开(公告)号：JP2003068100A
公开(公告)日：2003-03-07
申请号：JP2002220047
申请日：2002-07-29
申请人： Toshiba Corp , 株式会社東芝
发明人： NAKAI HIROTO , KATO HIDEO , ASANO MASAMICHI , TOKUSHIGE KAORU , YAMAMURA TOSHIO
IPC分类号： G11C16/02 , G11C16/04 , G11C16/06 , G11C29/00 , G11C29/14 , G11C29/56
摘要： PROBLEM TO BE SOLVED: To specify a write defective bit line. SOLUTION: A nonvolatile memory has a nonvolatile memory cell array, an address buffer for storing an address inputted from the outside, a decoder for selecting a plurality of memory cells from the memory cell array in accordance with the address stored in the address buffer, a data register to which data from the plurality of nonvolatile memory cell selected by the decoder is inputted and which outputs these inputted data, a plurality of external control signal input terminals, and data input/output terminals connected to the data register and the address buffer. A command input mode decided in accordance with the combination of a plurality of external control signals is allowed. When a register read-command is inputted to the input/output terminal in this command input mode, the contents of the address buffer are outputted to the input/ output terminal.
摘要翻译：要解决的问题：指定写入缺陷位线。解决方案：非易失性存储器具有非易失性存储单元阵列，用于存储从外部输入的地址的地址缓冲器，用于根据存储在地址缓冲器中的地址从存储单元阵列中选择多个存储单元的解码器，输入由解码器选择的多个非易失性存储单元的数据并输出这些输入数据的数据寄存器，多个外部控制信号输入端和连接到数据寄存器和地址缓冲器的数据输入/输出端。允许根据多个外部控制信号的组合决定的命令输入模式。在该命令输入模式下，当向输入/输出端子输入寄存器读取命令时，将地址缓冲器的内容输出到输入/输出端子。

69. 发明专利

JP2002093179A NON-VOLATILE SEMICONDUCTOR MEMORY 审中-公开
公开(公告)号：JP2002093179A
公开(公告)日：2002-03-29
申请号：JP2001285119
申请日：2001-09-19
申请人： TOSHIBA CORP
发明人： NAKAI HIROTO , KATO HIDEO , ASANO MASAMICHI , TOKUSHIGE KAORU , YAMAMURA TOSHIO
IPC分类号： G11C16/02 , G06F12/00 , G06F13/16 , G11C16/04 , G11C16/06
摘要： PROBLEM TO BE SOLVED: To provide a system in which an apparent access time is shortened. SOLUTION: This non-volatile semiconductor memory provided with plural non-volatile memory cells and plural data registers storing temporarily data of the memory cell, transfers data of selected one page out of the memory cells to the corresponding data register, outputs data of one page transferred to the corresponding data register to the outside, and outputs a busy signal indicating that access cannot be performed to the outside while data of one page is transferred to the corresponding data register. The device has a latch circuit connected to the data register and a buffer circuit connected to this latch circuit, and the busy signal is switched to a ready state after data of the head column address of read-out out of the data of one page is transferred to the latch circuit.

70. 发明专利

JP2001266583A NON-VOLATILE SEMICONDUCTOR MEMORY 失效
公开(公告)号：JP2001266583A
公开(公告)日：2001-09-28
申请号：JP2001029460
申请日：2001-02-06
申请人： TOSHIBA CORP
发明人： TANAKA TOMOHARU , MOMOTOMI MASAKI , KATO HIDEO , NAKAI HIROTO , TANAKA YOSHIYUKI , SHIRATA RIICHIRO , ARITOME SEIICHI , ITO YASUO , IWATA YOSHIHISA , NAKAMURA HIROSHI , OHIRA HIDEKO , OKAMOTO YUTAKA , ASANO MASAMICHI , TOKUSHIGE KAORU
IPC分类号： G11C16/06 , G11C16/02 , G11C16/04 , G11C29/00 , G11C29/12 , G11C29/44 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To shorten the time required for program-verification and erase- verification and to prevent over-variation of threshold voltage even if rewrite and reerase are performed. SOLUTION: This device is provided with a memory cell array which is arranged in a matrix state and in which memory cells having electric charges accumulating layers forms a matrix, a plurality of word lines connected commonly to the memory cells forming respective rows, a plurality of bit lines connected commonly to the memory cells forming respective columns, a means for selecting a word line and applying write voltage, and a plurality of data storage circuits which store control data of a first logic level or a second logic level deciding whether write control voltage for accumulating electric charges in the electric charge accumulating layers of the memory cells connected to the selected word line is to be applied to the bit line and which is arranged in respective bit lines. The control data of the second logic level deciding that the write control voltage is not applied to the bit line is stored in a data storage circuit other than the data storage circuit in which externally inputted control data are stored.

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