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1. 发明专利

JPH113597A NON-VOLATILE SEMICONDUCTOR MEMORY, VERIFYING METHOD FOR WRITING DATA TO NON-VOLATILE SEMICONDUCTOR, MEMORY, AND WRITING METHOD FOR DATA TO NON-VOLATILE SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPH113597A
公开(公告)日：1999-01-06
申请号：JP10465498
申请日：1998-04-15
申请人： TOSHIBA MICRO ELECTRONICS , TOSHIBA CORP
发明人： IWAHASHI HIROSHI
IPC分类号： G11C16/02 , G11C11/56
摘要： PROBLEM TO BE SOLVED: To provide a non-volatile semiconductor memory in which the difference of read-out speed in selected memory cells can be made small as much as possible. SOLUTION: This device is provided with a memory cell having a drain connected electrically to a bit line, a source, a floating gate, and a control gate connected electrically to a word line, a sense amplifier comparing given plural reference potentials with a potential of a bit line, detecting data stored in a memory cell, and outputting output 1, 2, 3, and a logic circuit deciding storage data D1, D2 from logic of the output 1, 2, 3. In this case, discrimination for whether desired data is written or not for data read out by verify-read-out performed after writing data is performed at a time TJD being later than a time TOD at which data read out at the time of normal reading is outputted to the outside.

2. 发明专利

JPH1031896A NONVOLATILE SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPH1031896A
公开(公告)日：1998-02-03
申请号：JP10130297
申请日：1997-04-18
申请人： TOSHIBA CORP , TOSHIBA MICRO ELECTRONICS
发明人： IWAHASHI HIROSHI , MINAGAWA EISHIN
IPC分类号： G11C16/02 , G11C16/06
摘要： PROBLEM TO BE SOLVED: To make a noise margin at the time of a normal reabout larger by setting a switching transistor in a nonconductive state at the time of a verification of the reading of data to set a data detecting reference at the time of the verification more strict. SOLUTION: In an EPROM, the detection output S of a high voltage detection circuit 6 is inverted by an inverter circuit 41 and the output of the circuit 41 is applied to the gate of the switching transistor 8b insertingly connected in between the 4a2 of one side of divided load transistors 4a1, 4a2 and a power source node 9. Consequently, since the number of operations of bit line load transistors is made smaller as compares with a normal reading time to lower a potential reading memory cells, the data detecting references made to become more strict.

3. 发明专利

JPH0668689A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPH0668689A
公开(公告)日：1994-03-11
申请号：JP24497492
申请日：1992-09-14
申请人： TOSHIBA CORP , TOSHIBA MICRO ELECTRONICS , TOSHIBA JOHO SYST KK
发明人： IWAHASHI HIROSHI , ASANO MASAMICHI , MOMOTOMI MASAKI , MINAGAWA EISHIN , SUZUKI KAZUTO , NARITA AKIRA
IPC分类号： G11C17/00 , G11C16/06
摘要： PURPOSE:To prevent stationary flowing of current from a power supply by suppressing a MOSFET of P channel with a second MOSFET of depression type of N channel and turning off the second MOSFET when an signal at an output terminal is made 0 level. CONSTITUTION:When an input signal IN is made 0 level, voltage close to high voltage V is obtained as an output signal OUT, and data is written. In this case, current outflow from a circuit point 27 to which VH is impressed is only a current for charging a circuit point 30, and stationary current outflow does not occur. Further, when the input signal is made 1 level, earth voltage VS, that is, voltage of 0V is obtained as the output signal OUT. In a memory cell in which this voltage is impressed to a control gate, threshold value voltage is not varied. In this case, current outflow from the circuit point 27 is only a leak current.

4. 发明专利

JPH04109494A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPH04109494A
公开(公告)日：1992-04-10
申请号：JP22866490
申请日：1990-08-30
申请人： TOSHIBA CORP , TOSHIBA MICRO ELECTRONICS , TOSBAC COMPUTER SYSTEM CO LTD
发明人： KATO HIDEO , NAKAI HIROTO , IWAHASHI HIROSHI , HIRAGA NOBUAKI
IPC分类号： G11C11/41 , G11C7/02 , G11C7/06 , G11C7/10 , G11C8/18 , G11C11/407 , G11C11/409 , G11C16/06
摘要： PURPOSE:To prevent the generation of malfunction in a data delay circuit by providing the semiconductor integrated circuit with an output buffer control circuit for setting up the output data of a data detection circuit to a state inhibiting its output from an output buffer circuit for a prescribed period based on a pulse signal outputted from an address change detecting circuit. CONSTITUTION:The data delay circuit 9 and a data latch circuit 10 are inserted between a sense amplifier circuit 7 and the output buffer circuit 8. The output buffer control circuit 11 generates a delay signal for setting up the delay time of the circuit 9 to a short value when data detected by the data detecting circuit 12 is not outputted from the circuit 8, and setting up the delay time to a longer value when data are outputted from the circuit 8. The circuit 9 is set up so as not to generate the delay signal after stopping the generation of the pulse output signal from the circuit 12. Consequently, the generation of malfunction due to power supply variation at the time of changing output data or the input of noise from the external can be prevented.

5. 发明专利

JPH03152797A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPH03152797A
公开(公告)日：1991-06-28
申请号：JP29057589
申请日：1989-11-08
申请人： TOSHIBA CORP , TOSHIBA MICRO ELECTRONICS
发明人： KIKUCHI SHINICHI , IWAHASHI HIROSHI
IPC分类号： G11C11/413 , G11C29/00 , H01L21/822 , H01L27/04
摘要： PURPOSE:To prevent an operation occurring and to accelerate the operation by detecting power source fluctuation when it occurs, and varying the potential of a signal line similarly as the fluctuation of potential generated by the power source fluctuation by stopping the input of a signal from the outside while the fluctuation occurs. CONSTITUTION:A power source fluctuation detection circuit 109 detects the power source source fluctuation when it occurs. Potential varying parts 202, 204 stop the input of the signals Ao-An, Bo-Bn while the power source fluctuation occurs when the power source fluctuation detection circuit 109 detects the power source fluctuation, and vary the potential of the signal line which transmits the signal during that time similarly as the fluctuation of a source voltage generated by the power source fluctuation, thereby, a relative potential difference between the signal line and the source voltage can be held constant. Thereby, it is possible to prevent the operation occurring and to accelerate the operation.

6. 发明专利

JPH0385770A MON-VOLATILE SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPH0385770A
公开(公告)日：1991-04-10
申请号：JP22400689
申请日：1989-08-30
申请人： TOSHIBA CORP , TOSHIBA MICRO ELECTRONICS
发明人： ASANO MASAMICHI , IWAHASHI HIROSHI
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PURPOSE:To increase operation speed, enable all memory cells to be erased collectively, uniformly, and positively, and reduce voltage used for writing by connecting a floating gate transistor and an enhancement type transistor in parallel for each memory cell. CONSTITUTION:Each floating gate 16 is placed so that it is shifted to the right and left (in the direction of extension of a control gate 17) or in zigzag. Namely, the floating gate 16 and the control gate 17 are overlapped in the upper direction at one part of the channel region of a memory cell 39, thus constituting a floating gate transistor 39a, and only the control gate 17 exists at the upper part of other parts of the channel region, thus constituting an enhancement type transistor 39b. Namely, the above two kinds of transistors are connected in parallel in some memory cells.

7. 发明专利

JPH0268797A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPH0268797A
公开(公告)日：1990-03-08
申请号：JP22022688
申请日：1988-09-02
申请人： TOSHIBA CORP , TOSHIBA MICRO ELECTRONICS , TOSBAC COMPUTER SYSTEM CO LTD
发明人： IWAHASHI HIROSHI , FUJIMOTO TOSHIYUKI , NARITA AKIRA
IPC分类号： G11C17/00 , G11C5/14 , G11C8/08 , G11C16/06 , G11C16/12 , H03K17/10
摘要： PURPOSE:To increase a break-down voltage at a drain by impressing a voltage approximately at 0V to the gate of a first load transistor and impressing an intermediate voltage smaller than a power source and larger than 0V to the gate of a second load transistor when program data are '1'. CONSTITUTION:When a signal A is '0', a transistor 3 is turned off, and nodes B1 and B2 are charged up to a boosting voltage SW through transistors 6 and 5. On the other hand, when the signal A is '1', the transistor 3 is turned on, and for such a reason, by enlarging the conducting resistance of the transistor 5 sufficiently, the node B1 is made approximately at 0V, a transistor 7 is turned on, and the node B2 is made into a value lower than the power source of an ordinary action by the degree of a threshold voltage. Thus, since the voltage of the B2 of a second load transistor 22 is raised over 0V, the break- down voltage of the drain is raised by the degree that the voltage is raised over the break-down at the time of 0V.

8. 发明专利

JPH01173387A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPH01173387A
公开(公告)日：1989-07-10
申请号：JP33005687
申请日：1987-12-28
申请人： TOSHIBA CORP
发明人： IWAHASHI HIROSHI
IPC分类号： G11C11/417 , G11C11/34 , G11C11/41
摘要： PURPOSE:To prevent malfunction due to the change of an output data level by equipping a means to detect the change of an address input and to generate a pulse, a part to transmit data from a memory cell to an output buffer and a means to control the responding speed of the transmitting part with a pulse signal. CONSTITUTION:The change of X and Y addresses from a terminal 1 is detected by a detecting circuit 9 and the new memory cell is selected. Then, the data are detected by a sense amplifier 6 and transmitted through a transmitting part 7 to an output buffer 8. At such a time, a switch SW is closed and the data are speedily transmitted. New data are outputted from the buffer 8 and the SW is opened before a noise is overlapped to a power source. After the data are outputted, the data are given from the sense amplifier 6 through a delay circuit DC to the buffer 8. The delay circuit DC is composed of R and C and the malfunction can be absorbed by the set of a delay time. Thus, the erroneous data are prevented from being outputted by the influence of a power source noise when the data are outputted from the output buffer.

9. 发明专利

JPH01138814A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPH01138814A
公开(公告)日：1989-05-31
申请号：JP19025488
申请日：1988-07-29
申请人： TOSHIBA CORP , TOSHIBA MICRO CUMPUTER ENG
发明人： TATSUMI YUICHI , IWAHASHI HIROSHI , MINAGAWA EISHIN , ASANO MASAMICHI
IPC分类号： G11C11/417 , G11C7/10 , G11C7/22 , G11C11/409 , G11C17/18 , H03K17/16 , H03K17/687 , H03K19/003 , H03K19/0175 , H03K19/0185
摘要： PURPOSE:To attain fast operation of an output circuit and to prevent malfunction due to reduced noise by providing a control means applying charge or discharge control to a prescribed node of the output circuit via a transistor(TR). CONSTITUTION:The output circuit is provided internally with an output control circuit outputting pulse signals P, P' controlling nodes 40, 47 of a buffer amplifier section BA. With the signal P going to '1', the node 40 is discharged through a path by TRs 41, 42 in addition to a current path of TRs 38, 39. Thus, the discharge speed of the node 40 is increased and a TR 51 is turned on rapidly and the leading of a data DOUT to '1' is made steep. The similar operation is applied also in the node 47 when the signal P' is '0' and the trailing of the data DOUT to '0' is made steep by the TR 52 turned on rapidly and high speed operation in the disable mode is attained. In case of the active mode, the nodes 40, 47 are charged/discharged slowly and no rapid current flows to the TRs 51, 52, then the occurrence of noise is decreased.

10. 发明专利

JPH01130397A NONVOLATILE SEMICONDUCTOR STORAGE DEVICE 失效
公开(公告)号：JPH01130397A
公开(公告)日：1989-05-23
申请号：JP28768087
申请日：1987-11-14
申请人： TOSHIBA CORP , TOSHIBA MICRO CUMPUTER ENG , TOSBAC COMPUTER SYSTEM CO LTD
发明人： NAKAI HIROTO , IWAHASHI HIROSHI , ASANO MASAMICHI , KATO HIDEO , KANAZAWA KAZUHISA , SATO ISAO , KUMAGAI SHIGERU , KIKUCHI SHINICHI , NARITA AKIRA
IPC分类号： G11C17/00 , G11C16/06
摘要： PURPOSE:To improve the stability of operation and to increase a write margin by preventing a leak current from an output line at the time of rise of the potential of the output line. CONSTITUTION:D type transistors T207-T209 are connected in series for the purpose of outputting a boosting voltage to a column decoder 12 and the output line of a data write circuit and the voltage of the output line is fed back. Consequently, the voltage is surely raised at the time of selection and is surely reduced at the time of nonselection. Thus, the power consumption is reduced regardless of the constitution of inexpensive N-channel MOS transistors, and the voltage margin is increased and the write margin is improved.

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