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1. 发明专利

JP2013200910A Semiconductor storage device and voltage output method of semiconductor storage device 审中-公开
标题翻译：半导体存储器件的半导体存储器件和电压输出方法
公开(公告)号：JP2013200910A
公开(公告)日：2013-10-03
申请号：JP2012067942
申请日：2012-03-23
申请人： Toshiba Corp , 株式会社東芝
发明人： SAKURAI KATSUAKI , IWATA YOSHIHISA
IPC分类号： G11C16/06
CPC分类号： G11C5/147 , G11C16/30
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor storage device that supplies an appropriate voltage to a non-selected source line SL without imparting temperature characteristics to a level-shifted voltage.SOLUTION: A semiconductor storage device comprises: a first comparator 100 using a first voltage and a second voltage as input voltage; a first capacitor 111 accumulating a potential of a first node; a current source 84 outputting first current to a second node; a resistance element 83 generating a third voltage at the second node; a second capacitor 112 accumulating a potential of the second node; first switches 103 and 104 that enable the first and second nodes respectively connected to the first and second capacitors to be commonly connected at a third node N62; and a second comparator 113 that defines a fourth voltage Vx obtained by charge-sharing with the first and second capacitors and a potential Vmon2 of a fourth node as input voltage, and matches the potential of the fourth node with a fourth voltage.
摘要翻译：要解决的问题：提供一种半导体存储装置，其向未选择的源极线SL提供适当的电压，而不对电平移位的电压赋予温度特性。解决方案：半导体存储装置包括：第一比较器100，电压和第二电压作为输入电压; 累积第一节点的电位的第一电容器111; 电流源84将第一电流输出到第二节点; 在第二节点处产生第三电压的电阻元件83; 累积第二节点的电位的第二电容器112; 第一开关103和104使得分别连接到第一和第二电容器的第一和第二节点在第三节点N62处共同连接; 以及第二比较器113，其限定通过与第一和第二电容器电荷共享获得的第四电压Vx和第四节点的电位Vmon2作为输入电压，并且将第四节点的电位与第四电压相匹配。

2. 发明专利

JP2008034456A Nonvolatile semiconductor memory device 审中-公开
标题翻译：非易失性半导体存储器件
公开(公告)号：JP2008034456A
公开(公告)日：2008-02-14
申请号：JP2006203325
申请日：2006-07-26
申请人： Toshiba Corp , 株式会社東芝
发明人： IWATA YOSHIHISA
IPC分类号： H01L21/8247 , G11C16/04 , G11C16/06 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/115 , G11C16/0483 , H01L27/11551 , H01L27/11578
摘要： PROBLEM TO BE SOLVED: To laminate memory cell transistors for large capacity through the microfabrication and simplification of memory cell units. SOLUTION: The nonvolatile semiconductor memory device is provided with a first source line side diode DS wherein an anode area is connected to a source line STL; a first bit line side diode DB wherein a cathode area is connected to a first bit line BL; and a first memory cell string which is connected between the cathode area of the first source line side diode DS and the anode area of the first bit line side diode DB, and to which a plurality of memory cell transistors M10, M11, ... are connected in series. The first memory cell string is arranged on a semiconductor substrate 10, and the first source line side diode DS is arranged on the semiconductor substrate 10 in the vertical direction within a contact for connecting the source line STL and the first memory cell string. The first bit line side diode DB is arranged on the semiconductor substrate 10 in the vertical direction within a contact for connecting the first bit line BL and the first memory cell string. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：通过微细加工和简化存储单元单元来叠加大容量的存储单元晶体管。解决方案：非易失性半导体存储器件设置有第一源极侧二极管DS，其中阳极区域连接到源极线STL; 第一位线侧二极管DB，其中阴极区域连接到第一位线BL; 以及第一存储单元串，其连接在第一源极侧二极管DS的阴极区域和第一位线侧二极管DB的阳极区域之间，多个存储单元晶体管M10，M11，... 串联连接。第一存储单元串被布置在半导体衬底10上，并且第一源极侧二极管DS在连接源极线STL和第一存储单元串的触点内沿垂直方向布置在半导体衬底10上。第一位线侧二极管DB在用于连接第一位线BL和第一存储单元串的触点内沿垂直方向布置在半导体衬底10上。版权所有（C）2008，JPO＆INPIT

3. 发明专利

JP2006344281A MAGNETIC RANDOM ACCESS MEMORY 审中-公开
公开(公告)号：JP2006344281A
公开(公告)日：2006-12-21
申请号：JP2005168305
申请日：2005-06-08
申请人： TOSHIBA CORP
发明人： SHIMIZU ARITAKE , IWATA YOSHIHISA
IPC分类号： G11C11/15 , H01L21/8246 , H01L27/10 , H01L27/105 , H01L43/08
摘要： PROBLEM TO BE SOLVED: To provide a magnetic random access memory with a small area. SOLUTION: The magnetic random access memory includes a plurality of memory cells 1 for storing the information, according to the inside magnetization direction. First write-in lines 2 include first extendedly provided sections 2a, second extendedly provided sections 2Aa and first connection sections 2b. The first extendedly provided sections have first ends and second ends along the first direction. The second extendedly provided sections have third ends and fourth ends, respectively on the same sides as those of the first ends and second ends. The first ends and the third ends are connected by the first connection sections. One of a plurality of memory cells 1 is held between second write-in lines 3 and the first write-in lines. A plurality of first surrounding circuits 4 for making current flow into the first write-in lines are connected to one or both of the second ends and fourth ends, and also to the first connection sections. COPYRIGHT: (C)2007,JPO&INPIT

4. 发明专利

JP2006179125A Data writing method of magnetic random address memory 有权
标题翻译：磁性随机存储器的数据写入方法
公开(公告)号：JP2006179125A
公开(公告)日：2006-07-06
申请号：JP2004371870
申请日：2004-12-22
申请人： Toshiba Corp , 株式会社東芝
发明人： IWATA YOSHIHISA
IPC分类号： G11C11/15 , H01L21/8246 , H01L27/105 , H01L43/08
CPC分类号： G11C11/15
摘要： PROBLEM TO BE SOLVED: To provide the data writing method of a magnetic random access memory in which current-magnetic field conversion efficiency can be raised. SOLUTION: In the data writing method of the magnetic random access memory, the followings are provided, i.e., a magnetoresistance effect element having an axis of easy magnetization and an axis of difficult magnetization, first writing wiring which is extended along the direction of the axis of easy magnetization and second writing wiring which is extended along the direction of the axis of difficult magnetization. The method includes a first cycle in which a first current flows in the first writing wiring in a first direction and a second current flows in the second writing wiring in a second direction, a second cycle in which flow of the first current is stopped in the first writing wiring and the second current flows in the second writing wiring in the second direction, and a third cycle in which the first current flows in a third direction that is opposite to the direction of the first direction, in the first writing wiring and the second current flows in the second direction in the second writing wiring. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供其中可提高电流 - 磁场转换效率的磁随机存取存储器的数据写入方法。解决方案：在磁性随机存取存储器的数据写入方法中，提供以下方式，即具有易磁化轴和难磁化轴的磁阻效应元件，第一写入布线沿着方向延伸的易磁化轴线和沿着难磁化轴线的方向延伸的第二写入布线。该方法包括第一周期，其中第一电流在第一方向上在第一写入布线中流动，并且第二电流在第二方向上在第二写入布线中流动，第二周期中第一电流的流动停止在第二周期中第一写入布线和第二电流沿第二方向流入第二写入布线，以及在第一写入布线中的第一个电流沿与第一方向的方向相反的第三方向流动的第三周期，并且第二电流在第二写入布线中沿第二方向流动。版权所有（C）2006，JPO＆NCIPI

5. 发明专利

JP2006165327A Magnetic random access memory 审中-公开
标题翻译：磁性随机存取存储器
公开(公告)号：JP2006165327A
公开(公告)日：2006-06-22
申请号：JP2004355682
申请日：2004-12-08
申请人： Toshiba Corp , 株式会社東芝
发明人： IWATA YOSHIHISA
IPC分类号： H01L27/105 , H01L21/8246 , H01L41/09 , H01L41/187 , H01L41/193 , H01L43/08
CPC分类号： G11C11/16 , B82Y10/00 , H01L27/228 , H01L43/08
摘要： PROBLEM TO BE SOLVED: To prevent a reduction of a write current and an erroneous write on a magnetic memory. SOLUTION: A magnetic random access memory comprises a magnetic resistance effect element MTJ; a write line WWL for use in generating a magnetic field for data write into the magnetic resistance effect element MTJ; and a strain layer 18 which is disposed corresponding to the magnetic resistance effect element MTJ, and has a function of physically deforming when data is written, for controlling a magnitude of an inverse magnetic field of the magnetic resistance effect element MTJ. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：为了防止写入电流的减少和磁存储器上的错误写入。解决方案：磁性随机存取存储器包括磁阻效应元件MTJ; 写入线WWL，用于产生用于数据写入磁阻效应元件MTJ的磁场; 以及应变层18，其对应于磁阻效应元件MTJ设置，并且具有当写入数据时物理变形的功能，用于控制磁阻效应元件MTJ的反向磁场的大小。版权所有（C）2006，JPO＆NCIPI

6. 发明专利

JP2006127672A Readout circuit of the semiconductor memory 有权
标题翻译：半导体存储器的读出电路
公开(公告)号：JP2006127672A
公开(公告)日：2006-05-18
申请号：JP2004316282
申请日：2004-10-29
申请人： Toshiba Corp , 株式会社東芝
发明人： TSUCHIDA KENJI , MIYAMOTO JUNICHI , IWATA YOSHIHISA
IPC分类号： G11C11/15
CPC分类号： G11C11/16 , G11C7/06 , G11C7/1051 , G11C7/1069 , G11C7/12 , G11C11/1673 , G11C2207/005
摘要： PROBLEM TO BE SOLVED: To propose a self reference sense method that excludes setting of a guard band, and combines reliability and high speed. SOLUTION: The readout circuit of a semiconductor memory, which is based on a self reference sense method that determines data in a memory cell MC based on first and second signal levels read out from a memory cell MC in first and second readout steps, includes a sense amplifier SA that determines the data in the memory cell MC based on potential of an input node SAIN, a transfer transistor N1 connected between the memory cell MC and the input node SAIN, a pre-charge circuit P3 that sets the input node SAIN to the pre-charge potential, and a VBIAS generator 12 that makes the transfer transistor N1 into a cutoff state based on the first signal level. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提出一种排除保护带设置的自参考感测方法，并结合可靠性和高速度。解决方案：半导体存储器的读出电路，其基于自参考检测方法，其基于在第一和第二读出步骤中从存储单元MC读出的第一和第二信号电平来确定存储器单元MC中的数据包括基于输入节点SAIN的电位确定存储单元MC中的数据的读出放大器SA，连接在存储单元MC和输入节点SAIN之间的传输晶体管N1，设置输入的预充电电路P3 节点SAIN到预充电电位，以及VBIAS发生器12，其使得转移晶体管N1基于第一信号电平进入截止状态。版权所有（C）2006，JPO＆NCIPI

7. 发明专利

JP2005317739A Magnetic storage device and method for manufacturing the same 审中-公开
标题翻译：磁性存储装置及其制造方法
公开(公告)号：JP2005317739A
公开(公告)日：2005-11-10
申请号：JP2004133445
申请日：2004-04-28
申请人： Toshiba Corp , 株式会社東芝
发明人： IWATA YOSHIHISA , FUKUZUMI YOSHIAKI , KAI TADASHI
IPC分类号： H01L27/105 , G11C11/00 , G11C11/16 , H01L21/8246 , H01L27/108 , H01L27/22 , H01L29/76 , H01L29/94 , H01L31/119 , H01L43/08 , H01L43/12
CPC分类号： G11C11/16 , B82Y10/00 , H01L27/228 , H01L43/08 , H01L43/12
摘要： PROBLEM TO BE SOLVED: To provide a magnetic storage device effective for microstructure and a method for manufacturing the magnetic storage device. SOLUTION: The magnetic storage device is provided with: magneto-resistance effect elements MTJ each being arranged on an intersecting position between a first writing wire WL and a second writing wire BL, and including an easy axis disposed in an extended direction of the first writing wire WL; and first conductive layers 15 each connecting the magneto-resistance effect element MTJ to another wiring layer. At least parts 20-1, 20-2 of sidewalls of the conductive layers 15 and the magneto-resistance effect elements MTJ are continued. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种对微结构有效的磁存储装置和一种用于制造磁存储装置的方法。解决方案：磁存储装置设置有：磁阻效应元件MTJ，其各自布置在第一写入线WL和第二写入线BL之间的交叉位置，并且包括沿着延伸方向第一写入线WL; 以及将磁阻效应元件MTJ连接到另一布线层的第一导电层15。至少导电层15的侧壁部分20-1,20-2和磁阻效应元件MTJ继续。版权所有（C）2006，JPO＆NCIPI

8. 发明专利

JP2005251336A Magnetoresistive random access memory and driving method therefor 有权
标题翻译：磁性随机访问存储器及其驱动方法
公开(公告)号：JP2005251336A
公开(公告)日：2005-09-15
申请号：JP2004062788
申请日：2004-03-05
申请人： Toshiba Corp , 株式会社東芝
发明人： IKEGAWA SUMIO , IWATA YOSHIHISA , TSUCHIDA KENJI
IPC分类号： G11C11/15 , G11C11/00
CPC分类号： G11C11/16
摘要： PROBLEM TO BE SOLVED: To provide a magnetoresistive random access memory with which read errors are reduced as far as possible and a large reproduction signal can be obtained.
SOLUTION: The driving method of a magnetoresistive random access memory having a memory cell which changes between binary resister values by the same write pulse comprises: a step for reading the resister value of the selected memory cell and making the read resister value a 1st resister value; a step for performing a 1st writing operation to the selected memory cell using a write pulse; a step for reading the resister value of the selected memory cell and making the read resister value a 2nd resister value; a step for comparing the 2nd resister value with the 1st resister value and deciding a data originally stored in the selected memory cell on the basis of the result of this comparison; and a step for performing 2nd write operation to the selected memory cell using the write pulse.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供尽可能减少读取误差的磁阻随机存取存储器，并且可以获得大的再现信号。解决方案：具有通过相同写入脉冲在二进制寄存器值之间变化的存储单元的磁阻随机存取存储器的驱动方法包括：读取所选存储单元的寄存器值并使读取寄存器值为a 第一名使用写入脉冲对选择的存储单元执行第一写入操作的步骤; 读取所选存储单元的寄存器值并使读取寄存器值为第二寄存器值的步骤; 将第二寄存器值与第一寄存器值进行比较的步骤，并且基于该比较的结果来决定原来存储在所选存储器单元中的数据; 以及使用写脉冲对选择的存储单元执行第二写操作的步骤。版权所有（C）2005，JPO＆NCIPI

9. 发明专利

JP2005191451A Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：JP2005191451A
公开(公告)日：2005-07-14
申请号：JP2003433930
申请日：2003-12-26
申请人： Toshiba Corp , 株式会社東芝
发明人： YAMADA TAKASHI , HORIGUCHI FUMIO , OSAWA TAKASHI , IWATA YOSHIHISA , ASAO YOSHIAKI
IPC分类号： H01L27/108 , G11C11/24 , G11C11/404 , H01L21/8239 , H01L21/8242 , H01L21/84 , H01L27/105 , H01L27/12
CPC分类号： H01L27/108 , H01L21/84 , H01L27/105 , H01L27/1052 , H01L27/1203 , H01L29/7841 , H01L29/785
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory device that can improve reliability.
SOLUTION: The semiconductor memory device is arranged at each intersection between a first word line WL and a bit-line BL provided on an SOI substrate, and each has a plurality of MIS transistors MC that each compose a memory cell. The plurality of MIS transistors are each formed in a semiconductor layer on an insulation film 12 having an electrically floating channel body 13, a first pullout region 17 formed in contact with the channel body in the semiconductor layer and arranged along the first word line, a gate insulation film 14 prepared on the channel body, a gate electrode electrically arranged on the gate insulation film and electrically connected to the first word line, and a source region 16 and drain region 15 arranged and separated in the bit-line direction so as to sandwich the channel body in the semiconductor layer.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：解决的问题：提供可提高可靠性的半导体存储器件。解决方案：半导体存储器件布置在第一字线WL和设置在SOI衬底上的位线BL之间的每个交叉处，并且每个具有各自构成存储单元的多个MIS晶体管MC。多个MIS晶体管分别形成在具有电浮动通道体13的绝缘膜12上的半导体层中，与半导体层中的沟道本体形成并沿第一字线布置的第一拉出区域17，栅极绝缘膜14，其形成在栅极绝缘膜上并与第一字线电连接的栅极，以及沿位线方向排列和分离的源极区域16和漏极区域15，将沟道体夹在半导体层中。版权所有（C）2005，JPO＆NCIPI

10. 发明专利

JP2004118923A Magnetic random access memory 审中-公开
公开(公告)号：JP2004118923A
公开(公告)日：2004-04-15
申请号：JP2002279745
申请日：2002-09-25
申请人： Toshiba Corp , 株式会社東芝
发明人： FUJITA KATSUYUKI , IWATA YOSHIHISA
IPC分类号： G11C11/15 , G11C8/08 , G11C11/16 , H01L21/8246 , H01L27/105 , H01L43/08
CPC分类号： G11C11/16 , G11C8/08
摘要： PROBLEM TO BE SOLVED: To prevent incorrect writing at power-on, and destruction of a cell at writing.
SOLUTION: One end of a writing wordline WWL1 is connected to a decoder driver unit 12-1. The decoder driver unit 12-1 consists of a P channel MOS transistor P1, an N channel MOS transistor N1 and a NAND circuit ND1. When all of WRITE, CHDRY and RA1 become "H", an output signal of NAND circuit ND1 becomes "H", and the writing electric current flows into the writing wordline WWL1. The CHRDY is a signal to become "H" after an initialization operation of all internal circuits is completed after power-on. A limiting circuit 15 is composed of a clamping circuit which restricts the potential of writing wordline WWL1 to below a prefixed value.
COPYRIGHT: (C)2004,JPO

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