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61. 发明授权

US06586842B1 Dual damascene integration scheme for preventing copper contamination of dielectric layer 有权
标题翻译：用于防止介电层铜污染的双镶嵌一体化方案
公开(公告)号：US06586842B1
公开(公告)日：2003-07-01
申请号：US09793993
申请日：2001-02-28
申请人： Lu You , Fei Wang , Christy Woo
发明人： Lu You , Fei Wang , Christy Woo
IPC分类号： H01L2352
CPC分类号： H01L21/76831 , H01L21/76804 , H01L21/76813 , H01L21/76832 , H01L21/76834 , H01L23/5226 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a first metallization layer, a first diffusion barrier layer, a second etch stop layer, a first dielectric layer, a first etch stop layer, a second dielectric layer, a trench extending through the second dielectric layer and the first etch stop layer, and a via extending through the first dielectric layer, the second etch stop layer, and the first diffusion barrier layer. The first diffusion barrier layer is disposed over the first metallization layer. The second etch stop layer is disposed over and spaced from the first diffusion barrier layer, and the first dielectric layer is disposed over the second etch stop layer. The via can also have rounded corners. A third etch stop layer can also be disposed between the first diffusion barrier layer and the second etch stop layer. A sidewall diffusion barrier layer can be disposed on sidewalls of the via and trench, and the sidewall diffusion barrier layer is formed from the same material as the first diffusion barrier layer. A method of manufacturing the semiconductor device is also disclosed.
摘要翻译：半导体器件包括第一金属化层，第一扩散阻挡层，第二蚀刻停止层，第一介电层，第一蚀刻停止层，第二介电层，延伸穿过第二介电层的沟槽和第一蚀刻停止层层，以及延伸穿过第一介电层，第二蚀刻停止层和第一扩散阻挡层的通孔。第一扩散阻挡层设置在第一金属化层上。第二蚀刻停止层设置在第一扩散阻挡层之上并与第一扩散阻挡层隔开，并且第一介电层设置在第二蚀刻停止层上。通孔也可以有圆角。第三蚀刻停止层也可以设置在第一扩散阻挡层和第二蚀刻停止层之间。侧壁扩散阻挡层可以设置在通孔和沟槽的侧壁上，并且侧壁扩散阻挡层由与第一扩散阻挡层相同的材料形成。还公开了制造半导体器件的方法。

62. 发明授权

US06577009B1 Use of sic for preventing copper contamination of dielectric layer 有权
标题翻译：使用sic来防止介电层的铜污染
公开(公告)号：US06577009B1
公开(公告)日：2003-06-10
申请号：US09776718
申请日：2001-02-06
申请人： Lu You , Fei Wang , Minh Van Ngo
发明人： Lu You , Fei Wang , Minh Van Ngo
IPC分类号： H01L2352
CPC分类号： H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a first metallization layer, a first diffusion barrier layer, a first etch stop layer, a dielectric layer and a via extending through the dielectric layer, the first etch stop layer, and the first diffusion barrier layer. The first diffusion barrier layer is disposed over the first metallization layer. The first etch stop layer is disposed over the first diffusion barrier layer, and the dielectric layer is disposed over the first etch stop layer. The via can also have rounded corners. A sidewall diffusion barrier layer can be disposed on sidewalls of the via, and the sidewall diffusion barrier layer is formed from the same material.as the first diffusion barrier layer. The first diffusion barrier layer can be formed from silicon carbide. A method of manufacturing the semiconductor device is also disclosed.
摘要翻译：半导体器件包括第一金属化层，第一扩散阻挡层，第一蚀刻停止层，介电层和延伸穿过介电层的通孔，第一蚀刻停止层和第一扩散阻挡层。第一扩散阻挡层设置在第一金属化层上。第一蚀刻停止层设置在第一扩散阻挡层上，并且电介质层设置在第一蚀刻停止层上。通孔也可以有圆角。侧壁扩散阻挡层可以设置在通孔的侧壁上，并且侧壁扩散阻挡层由第一扩散阻挡层中的相同材料形成。第一扩散阻挡层可以由碳化硅形成。还公开了制造半导体器件的方法。

63. 发明授权

US06576982B1 Use of sion for preventing copper contamination of dielectric layer 失效
标题翻译：使用硫化物防止介电层的铜污染
公开(公告)号：US06576982B1
公开(公告)日：2003-06-10
申请号：US09776746
申请日：2001-02-06
申请人： Lu You , Dawn M. Hopper , Minh Van Ngo
发明人： Lu You , Dawn M. Hopper , Minh Van Ngo
IPC分类号： H01L2358
CPC分类号： H01L21/76831 , H01L21/76802 , H01L21/76804 , H01L21/76813 , H01L21/76877 , H01L23/5226 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a first metallization layer, a first diffusion barrier layer, a first etch stop layer, a dielectric layer and a via extending through the dielectric layer, the first etch stop layer, and the first diffusion barrier layer. The first diffusion barrier layer is disposed over the first metallization layer. The first etch stop layer is disposed over the first diffusion barrier layer, and the dielectric layer is disposed over the first etch stop layer. The via can also have rounded corners. A sidewall diffusion barrier layer can be disposed on sidewalls of the via, and the sidewall diffusion barrier layer is formed from the same material as the first diffusion barrier layer. The first etch stop layer can be formed from silicon oxynitride. A method of manufacturing the semiconductor device is also disclosed.
摘要翻译：半导体器件包括第一金属化层，第一扩散阻挡层，第一蚀刻停止层，介电层和延伸穿过介电层的通孔，第一蚀刻停止层和第一扩散阻挡层。第一扩散阻挡层设置在第一金属化层上。第一蚀刻停止层设置在第一扩散阻挡层上，并且电介质层设置在第一蚀刻停止层上。通孔也可以有圆角。侧壁扩散阻挡层可以设置在通孔的侧壁上，并且侧壁扩散阻挡层由与第一扩散阻挡层相同的材料形成。第一蚀刻停止层可以由氮氧化硅形成。还公开了制造半导体器件的方法。

64. 发明授权

US06465361B1 Method for preventing damage of low-k dielectrics during patterning 有权
标题翻译：在图案化期间防止低k电介质损坏的方法
公开(公告)号：US06465361B1
公开(公告)日：2002-10-15
申请号：US09785444
申请日：2001-02-20
申请人： Lu You , Steve Avanzino , Fei Wang
发明人： Lu You , Steve Avanzino , Fei Wang
IPC分类号： H01L21302
CPC分类号： H01L21/76802
摘要： A process for manufacturing a semiconductor device includes forming a first metallization level, forming a first etch stop layer, forming a low-k dielectric layer, forming a cap layer, depositing a resist, forming an opening; removing the resist, curing the dielectric material, etching the first etch stop layer, and filing the opening with metal. The first etch stop layer is formed over the first metallization level, and the low-k dielectric layer material is formed over the first etch stop layer. The cap layer is formed over the low-k dielectric layer material, and the resist is formed over the dielectric layer. Etching is used to form the opening. The resist is removed with an O2 stripping process. Curing of the dielectric material forms a dielectric layer and occurs after the resist is removed.
摘要翻译：制造半导体器件的工艺包括形成第一金属化层，形成第一蚀刻停止层，形成低k电介质层，形成覆盖层，沉积抗蚀剂，形成开口; 去除抗蚀剂，固化电介质材料，蚀刻第一蚀刻停止层，并用金属填充开口。在第一金属化层上形成第一蚀刻停止层，并且在第一蚀刻停止层上形成低k电介质层材料。盖层形成在低k电介质层材料上，并且抗蚀剂形成在介电层上。蚀刻用于形成开口。用O2剥离工艺除去抗蚀剂。电介质材料的固化形成电介质层，并且在抗蚀剂除去之后发生。

65. 发明授权

US06445051B1 Method and system for providing contacts with greater tolerance for misalignment in a flash memory 有权
标题翻译：用于提供触点的方法和系统，其具有对于闪存中未对准的更大容限
公开(公告)号：US06445051B1
公开(公告)日：2002-09-03
申请号：US09563797
申请日：2000-05-02
申请人： Mark S. Chang , Hao Fang , King Wai Kelwin Ko , John Jianshi Wang , Michael K. Templeton , Lu You , Angela T. Hui
发明人： Mark S. Chang , Hao Fang , King Wai Kelwin Ko , John Jianshi Wang , Michael K. Templeton , Lu You , Angela T. Hui
IPC分类号： H01L2976
CPC分类号： H01L21/76897 , H01L21/28273
摘要： A method and system for providing a plurality of contacts in a flash memory device is disclosed. The flash memory device includes a plurality of gate stacks and a plurality of field insulating regions adjacent to a portion of the plurality of gate stacks. The method and system include providing an etch stop layer covering the plurality of field insulating regions. The etch stop layer has an etch selectivity different from a field insulating region etch selectivity of the plurality of field insulating regions. The method and system also include providing an insulating layer covering the plurality of gate stacks, the plurality of field insulating regions and the etch stop layer. The method and system further include etching the insulating layer to provide a plurality of contact holes. The insulating layer etching step uses the etch stop layer to ensure that the insulating etching step does not etch through the plurality of field insulating regions. The method and system also include filling the plurality of contact holes with a conductor.
摘要翻译：公开了一种用于在闪速存储器件中提供多个触点的方法和系统。闪存器件包括多个栅极堆叠和与多个栅极堆叠的一部分相邻的多个场绝缘区域。该方法和系统包括提供覆盖多个场绝缘区域的蚀刻停止层。蚀刻停止层具有与多个场绝缘区域的场绝缘区蚀刻选择性不同的蚀刻选择性。该方法和系统还包括提供覆盖多个栅极叠层，多个场绝缘区域和蚀刻停止层的绝缘层。该方法和系统还包括蚀刻绝缘层以提供多个接触孔。绝缘层蚀刻步骤使用蚀刻停止层来确保绝缘蚀刻步骤不会蚀刻穿过多个场绝缘区域。该方法和系统还包括用导体填充多个接触孔。

66. 发明授权

US5888898A HSQ baking for reduced dielectric constant 失效
标题翻译： HSQ烘烤用于降低介电常数
公开(公告)号：US5888898A
公开(公告)日：1999-03-30
申请号：US956588
申请日：1997-10-23
申请人： Minh V. Ngo , Khanh Q. Tran , Terri J. Kitson , Lu You , Simon S. Chan , Jean Y. Yang
发明人： Minh V. Ngo , Khanh Q. Tran , Terri J. Kitson , Lu You , Simon S. Chan , Jean Y. Yang
IPC分类号： H01L21/314 , H01L21/316 , H01L21/768 , H01L23/522 , H01L23/532 , H01L21/4763
CPC分类号： H01L21/02134 , H01L21/02164 , H01L21/02211 , H01L21/02274 , H01L21/02282 , H01L21/02337 , H01L21/316 , H01L21/31612 , H01L21/76801 , H01L21/76826 , H01L21/76828 , H01L23/5226 , H01L23/5329 , H01L2924/0002
摘要： A patterned metal layer is gap filled with HSQ, an oxide formed thereon by PECVD, e.g., silicon dioxide derived from silane and N.sub.2 O, and planarized. The dielectric constant of the HSQ layer is minimized by baking the deposited HSQ layer in an inert atmosphere, e.g., N.sub.2, before heat soaking in an N.sub.2 O-containing atmosphere for no more than about 10 seconds and subsequent PECVD.
摘要翻译：图案化的金属层是间隙填充有HSQ，其是通过PECVD在其上形成的氧化物，例如来自硅烷和N 2 O的二氧化硅，并且被平坦化。通过在惰性气氛例如N 2中烘烤沉积的HSQ层，在含N2O的气氛中热浸泡不超过约10秒并随后的PECVD之后，使HSQ层的介电常数最小化。

67. 发明授权

US5268202A Vapor deposition of parylene-F using 1,4-bis (trifluoromethyl) benzene 失效
标题翻译：使用1,4-双（三氟甲基）苯气相沉积聚对二甲苯
公开(公告)号：US5268202A
公开(公告)日：1993-12-07
申请号：US960089
申请日：1992-10-09
申请人： Lu You , Guang-Rong Yang , Toh-Ming Lu , James A. Moore , John F. P. McDonald
发明人： Lu You , Guang-Rong Yang , Toh-Ming Lu , James A. Moore , John F. P. McDonald
IPC分类号： B05D7/24 , C23C16/448 , C23C16/00
CPC分类号： B05D1/60 , C23C16/4488
摘要： A PA-F polymer film is formed using a mixture of 1,4-bis (trifluoromethyl) benzene (TFB) and a halogen initiator. This mixture is provided to a low pressure reactor containing a metal catalyst. The reactor is operated at a sufficient temperature to form a reactive monomer by a chemical reaction at the surface of the catalyst. The reactive monomer is condensed on the surface of a substrate cooled to a temperature sufficiently low to induce polymerization of the reactive monomer to form a PA-F polymer film. In general, the proportion of halogen initiator is about 0.25 to 50% by volume relative to the total volume of the TFB/halogen initiator mixture. The reactor is operated at a temperature of about 200.degree. to 700.degree. C. and a pressure of less than about one torr. In addition, the surface of the substrate is maintained at a temperature of about -30.degree. C. to room temperature. In the preferred approach, the halogen initiator is dibromotetrafluoro-p-xylene (DBX) and the proportion of DBX is about 1 to 5%.
摘要翻译：使用1,4-双（三氟甲基）苯（TFB）和卤素引发剂的混合物形成PA-F聚合物膜。将该混合物提供至含有金属催化剂的低压反应器。反应器在足够的温度下操作以通过催化剂表面的化学反应形成反应性单体。反应性单体在冷却到足够低的温度的基材的表面上冷凝以引发反应性单体的聚合以形成PA-F聚合物膜。通常，相对于TFB /卤素引发剂混合物的总体积，卤素引发剂的比例为约0.25至50体积％。反应器在约200℃至700℃的温度和小于约一乇的压力下操作。此外，将基板的表面保持在约-30℃至室温的温度。在优选的方法中，卤素引发剂是二溴四氟对二甲苯（DBX），DBX的比例为约1至5％。

68. 发明授权

US07378310B1 Method for manufacturing a memory device having a nanocrystal charge storage region 有权
标题翻译：一种具有纳米晶体电荷存储区域的存储器件的制造方法
公开(公告)号：US07378310B1
公开(公告)日：2008-05-27
申请号：US11116551
申请日：2005-04-27
申请人： Connie Pin-Chin Wang , Zoran Krivokapic , Suzette Keefe Pangrle , Robert Chiu , Lu You
发明人： Connie Pin-Chin Wang , Zoran Krivokapic , Suzette Keefe Pangrle , Robert Chiu , Lu You
IPC分类号： H01L21/8242
CPC分类号： H01L21/28273 , B82Y10/00 , H01L29/42332 , H01L29/7881
摘要： A method for manufacturing a memory device having a metal nanocrystal charge storage structure. A substrate is provided and a first layer of dielectric material is grown on the substrate. A layer of metal oxide having a first heat of formation is formed on the first layer of dielectric material. A metal layer having a second heat of formation is formed on the metal oxide layer. The second heat of formation is greater than the first heat of formation. The metal oxide layer and the metal layer are annealed which causes the metal layer to reduce the metal oxide layer to metallic form, which then agglomerates to form metal islands. The metal layer becomes oxidized thereby embedding the metal islands within an oxide layer to form a nanocrystal layer. A control oxide is formed over the nanocrystal layer and a gate electrode is formed on the control oxide.
摘要翻译：一种具有金属纳米晶电荷存储结构的存储器件的制造方法。提供衬底并且在衬底上生长第一介电材料层。在第一绝缘材料层上形成具有第一形成热的金属氧化物层。在金属氧化物层上形成具有第二次形成热的金属层。第二次形成的热量大于第一次形成的热量。金属氧化物层和金属层被退火，这导致金属层将金属氧化物层还原成金属形式，然后使其聚集形成金属岛。金属层变得氧化，从而将金属岛嵌入氧化物层中以形成纳米晶层。在纳米晶体层上形成控制氧化物，在控制氧化物上形成栅电极。

69. 发明授权

US07001840B1 Interconnect with multiple layers of conductive material with grain boundary between the layers 有权
标题翻译：与层之间具有晶界的多层导电材料互连
公开(公告)号：US07001840B1
公开(公告)日：2006-02-21
申请号：US10361332
申请日：2003-02-10
申请人： Minh Quoc Tran , Lu You , Fei Wang , Lynne Okada
发明人： Minh Quoc Tran , Lu You , Fei Wang , Lynne Okada
IPC分类号： H01L21/44
CPC分类号： H01L21/76879 , H01L21/2885
摘要： An interconnect structure is formed with a plurality of layers of a conductive material with a grain boundary between any two adjacent layers of the conductive material. Such grain boundaries between layers of conductive material act as shunt by-pass paths for migration of atoms of the conductive material to minimize migration of atoms of the conductive material along the interface between a dielectric passivation or capping layer and the interconnect structure. When the interconnect structure is a via structure, each of the layers of the conductive material and each of the grain boundary are formed to be perpendicular to a direction of current flow through the via structure. Such grain boundaries formed between the plurality of layers of conductive material in the via structure minimize charge carrier wind-force along the direction of current flow through the via structure to further minimize electromigration failure of the via structure.
摘要翻译：互连结构形成有导电材料的多层，在导电材料的任何两个相邻层之间具有晶界。导电材料层之间的这种晶界作为用于迁移导电材料的原子的分流旁通路径，以最小化导电材料原子沿着介电钝化层或覆盖层与互连结构之间的界面的迁移。当互连结构是通孔结构时，导电材料的每个层和每个晶界形成为垂直于通过过孔结构的电流的方向。在通孔结构中的多个导电材料层之间形成的这种晶界沿着通过通孔结构的电流流动的方向最小化载流子的风力，以进一步最小化通孔结构的电迁移故障。

70. 发明授权

US06677679B1 Use of SiO2/Sin for preventing copper contamination of low-k dielectric layers 有权
标题翻译：使用SiO2 / Sin来防止低k电介质层的铜污染
公开(公告)号：US06677679B1
公开(公告)日：2004-01-13
申请号：US09776749
申请日：2001-02-06
申请人： Lu You , Fei Wang , Dawn M. Hopper
发明人： Lu You , Fei Wang , Dawn M. Hopper
IPC分类号： H01L214763
CPC分类号： H01L21/76832 , H01L21/76802 , H01L21/76804 , H01L21/76807 , H01L21/76831 , H01L21/76834
摘要： A semiconductor device includes a first metallization level, a first diffusion barrier layer, a first etch stop layer, a second etch top layer, a dielectric layer and an opening extending through the dielectric layer, the first and second etch stop layers, and the first diffusion barrier layer. The first diffusion barrier layer is disposed over the first metallization level. The second etch stop layer is disposed over the first diffusion barrier layer, and the first etch stop layer is disposed on the second etch stop layer with a first interface therebetween. The dielectric layer is disposed over the first etch stop layer. The opening can also have rounded corners. A sidewall diffusion barrier layer can be disposed on sidewalls of the opening, and the sidewall diffusion barrier layer is formed from the same material as the first diffusion barrier layer. The first etch stop layer and the barrier diffusion layer can be formed from silicon nitride, and the second etch stop layer can be formed from silicon oxide. Metal within the opening forms a second metal feature, and the metal can comprise copper or a copper alloy. A method of manufacturing the semiconductor device is also disclosed.
摘要翻译：半导体器件包括第一金属化水平，第一扩散阻挡层，第一蚀刻停止层，第二蚀刻顶层，介电层和延伸穿过介电层的开口，第一和第二蚀刻停止层以及第一蚀刻停止层扩散阻挡层。第一扩散阻挡层设置在第一金属化层上。第二蚀刻停止层设置在第一扩散阻挡层上，并且第一蚀刻停止层设置在第二蚀刻停止层上，其间具有第一界面。介电层设置在第一蚀刻停止层上。开口也可以有圆角。侧壁扩散阻挡层可以设置在开口的侧壁上，并且侧壁扩散阻挡层由与第一扩散阻挡层相同的材料形成。第一蚀刻停止层和阻挡扩散层可以由氮化硅形成，并且第二蚀刻停止层可以由氧化硅形成。开口内的金属形成第二金属特征，金属可以包括铜或铜合金。还公开了制造半导体器件的方法。

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