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1. 发明授权

US06939793B1 Dual damascene integration scheme for preventing copper contamination of dielectric layer 有权
标题翻译：用于防止介电层铜污染的双镶嵌一体化方案
公开(公告)号：US06939793B1
公开(公告)日：2005-09-06
申请号：US10422784
申请日：2003-04-25
申请人： Lu You , Fei Wang , Christy Woo
发明人： Lu You , Fei Wang , Christy Woo
IPC分类号： H01L21/768 , H01L23/522 , H01L23/532 , H01L21/4763
CPC分类号： H01L21/76831 , H01L21/76804 , H01L21/76813 , H01L21/76832 , H01L21/76834 , H01L23/5226 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a first metallization layer, a first diffusion barrier layer, a second etch stop layer, a first dielectric layer, a first etch stop layer, a second dielectric layer, a trench extending through the second dielectric layer and the first etch stop layer, and a via extending through the first dielectric layer, the second etch stop layer, and the first diffusion barrier layer. The first diffusion barrier layer is disposed over the first metallization layer. The second etch stop layer is disposed over and spaced from the first diffusion barrier layer, and the first dielectric layer is disposed over the second etch stop layer. The via can also have rounded corners. A third etch stop layer can also be disposed between the first diffusion barrier layer and the second etch stop layer. A sidewall diffusion barrier layer can be disposed on sidewalls of the via and trench, and the sidewall diffusion barrier layer is formed from the same material as the first diffusion barrier layer. A method of manufacturing the semiconductor device is also disclosed.
摘要翻译：半导体器件包括第一金属化层，第一扩散阻挡层，第二蚀刻停止层，第一介电层，第一蚀刻停止层，第二介电层，延伸穿过第二介电层的沟槽和第一蚀刻停止层层，以及延伸穿过第一介电层，第二蚀刻停止层和第一扩散阻挡层的通孔。第一扩散阻挡层设置在第一金属化层上。第二蚀刻停止层设置在第一扩散阻挡层之上并与第一扩散阻挡层隔开，并且第一介电层设置在第二蚀刻停止层上。通孔也可以有圆角。第三蚀刻停止层也可以设置在第一扩散阻挡层和第二蚀刻停止层之间。侧壁扩散阻挡层可以设置在通孔和沟槽的侧壁上，并且侧壁扩散阻挡层由与第一扩散阻挡层相同的材料形成。还公开了制造半导体器件的方法。

2. 发明授权

US06586842B1 Dual damascene integration scheme for preventing copper contamination of dielectric layer 有权
标题翻译：用于防止介电层铜污染的双镶嵌一体化方案
公开(公告)号：US06586842B1
公开(公告)日：2003-07-01
申请号：US09793993
申请日：2001-02-28
申请人： Lu You , Fei Wang , Christy Woo
发明人： Lu You , Fei Wang , Christy Woo
IPC分类号： H01L2352
CPC分类号： H01L21/76831 , H01L21/76804 , H01L21/76813 , H01L21/76832 , H01L21/76834 , H01L23/5226 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a first metallization layer, a first diffusion barrier layer, a second etch stop layer, a first dielectric layer, a first etch stop layer, a second dielectric layer, a trench extending through the second dielectric layer and the first etch stop layer, and a via extending through the first dielectric layer, the second etch stop layer, and the first diffusion barrier layer. The first diffusion barrier layer is disposed over the first metallization layer. The second etch stop layer is disposed over and spaced from the first diffusion barrier layer, and the first dielectric layer is disposed over the second etch stop layer. The via can also have rounded corners. A third etch stop layer can also be disposed between the first diffusion barrier layer and the second etch stop layer. A sidewall diffusion barrier layer can be disposed on sidewalls of the via and trench, and the sidewall diffusion barrier layer is formed from the same material as the first diffusion barrier layer. A method of manufacturing the semiconductor device is also disclosed.
摘要翻译：半导体器件包括第一金属化层，第一扩散阻挡层，第二蚀刻停止层，第一介电层，第一蚀刻停止层，第二介电层，延伸穿过第二介电层的沟槽和第一蚀刻停止层层，以及延伸穿过第一介电层，第二蚀刻停止层和第一扩散阻挡层的通孔。第一扩散阻挡层设置在第一金属化层上。第二蚀刻停止层设置在第一扩散阻挡层之上并与第一扩散阻挡层隔开，并且第一介电层设置在第二蚀刻停止层上。通孔也可以有圆角。第三蚀刻停止层也可以设置在第一扩散阻挡层和第二蚀刻停止层之间。侧壁扩散阻挡层可以设置在通孔和沟槽的侧壁上，并且侧壁扩散阻挡层由与第一扩散阻挡层相同的材料形成。还公开了制造半导体器件的方法。

3. 发明授权

US06663787B1 Use of ta/tan for preventing copper contamination of low-k dielectric layers 有权
标题翻译：使用ta / tan来防止低k电介质层的铜污染
公开(公告)号：US06663787B1
公开(公告)日：2003-12-16
申请号：US09776747
申请日：2001-02-06
申请人： Lu You , Christy Woo , Pin Chin Connie Wang
发明人： Lu You , Christy Woo , Pin Chin Connie Wang
IPC分类号： H01L214763
CPC分类号： H01L21/76844 , H01L21/76802 , H01L21/76804 , H01L21/76813 , H01L21/76831 , H01L21/76838 , H01L21/76862 , H01L21/76865
摘要： A semiconductor device includes a first metallization level, a first diffusion barrier layer, a first etch stop layer, a dielectric layer and an opening extending through the dielectric layer, the first etch stop layer, and the first diffusion barrier layer. The first diffusion barrier layer is disposed over the first metallization level. The first etch stop layer is disposed over the first diffusion barrier layer, and the dielectric layer is disposed over the first etch stop layer. The opening can also have rounded corners. A sidewall diffusion barrier layer can be disposed on sidewalls of the opening, and the sidewall diffusion barrier layer is formed from the same material as the first diffusion barrier layer. The first etch stop layer can be formed from a material different than the first barrier layer, and the material of the first barrier layer can be selected from the group consisting of tantalum, titanium, tantalum nitride, titanium nitride, and tungsten nitride. Metal within the opening form a second metal feature, and the metal can comprise copper or a copper alloy. A method of manufacturing the semiconductor device is also disclosed.
摘要翻译：半导体器件包括第一金属化水平，第一扩散阻挡层，第一蚀刻停止层，电介质层和延伸穿过介电层的开口，第一蚀刻停止层和第一扩散阻挡层。第一扩散阻挡层设置在第一金属化层上。第一蚀刻停止层设置在第一扩散阻挡层上，并且电介质层设置在第一蚀刻停止层上。开口也可以有圆角。侧壁扩散阻挡层可以设置在开口的侧壁上，并且侧壁扩散阻挡层由与第一扩散阻挡层相同的材料形成。第一蚀刻停止层可以由不同于第一阻挡层的材料形成，并且第一阻挡层的材料可以选自钽，钛，氮化钽，氮化钛和氮化钨。开口内的金属形成第二金属特征，金属可以包括铜或铜合金。还公开了制造半导体器件的方法。

4. 发明授权

US06699792B1 Polymer spacers for creating small geometry space and method of manufacture thereof 有权
标题翻译：用于产生小几何空间的聚合物间隔物及其制造方法
公开(公告)号：US06699792B1
公开(公告)日：2004-03-02
申请号：US09907398
申请日：2001-07-17
申请人： Fei Wang , Lu You , Lynne Okada
发明人： Fei Wang , Lu You , Lynne Okada
IPC分类号： H01L21311
CPC分类号： H01L21/32139 , H01L21/0271 , H01L21/0338 , H01L21/31144
摘要： In forming an opening or space in a substrate, a layer of photoresist is provided on the substrate, and the photoresist is patterned to provide photoresist bodies having respective adjacent sidewalls. A polymer layer is provided on the resulting structure through a low temperature conformal CVD process. The polymer layer is anisotropically etched to form spacers on the respective adjacent sidewalls of the photoresist bodies. The substrate is then etched using the spacers as a mask.
摘要翻译：在形成衬底中的开口或空间时，在衬底上提供光致抗蚀剂层，并且对光致抗蚀剂进行图案化以提供具有相应相邻侧壁的光致抗蚀剂体。通过低温保形CVD工艺在所得结构上提供聚合物层。聚合物层被各向异性蚀刻以在光致抗蚀剂体的各个相邻侧壁上形成间隔物。然后使用间隔物作为掩模蚀刻衬底。

5. 发明授权

US06417090B1 Damascene arrangement for metal interconnection using low k dielectric constant materials for etch stop layer 有权
标题翻译：用于蚀刻停止层的低k介电常数材料的金属互连的镶嵌装置
公开(公告)号：US06417090B1
公开(公告)日：2002-07-09
申请号：US09225008
申请日：1999-01-04
申请人： Fei Wang , Lu You
发明人： Fei Wang , Lu You
IPC分类号： H01L214763
CPC分类号： H01L21/76802 , H01L21/31116 , H01L21/31138 , H01L21/76829
摘要： A method of forming a damascene structure in a semiconductor device arrangement uses a low k dielectric material in an etch stop layer that overlays a metal interconnect layer. The etch stop layer protects the metal interconnect layer, made of copper, for example, during the etching of a dielectric layer that overlays the etch stop layer. Following the etching of the dielectric layer, which stops on the etch stop layer, the etch stop layer is then etched with a chemistry that does not damage the underlying copper in the metal interconnect layer. The lower dielectric constant material employed in the etch stop layer reduces the overall dielectric constant of the film, thereby improving the operating performance of the chip.
摘要翻译：在半导体器件布置中形成镶嵌结构的方法使用覆盖金属互连层的蚀刻停止层中的低k电介质材料。蚀刻停止层例如在蚀刻覆盖在蚀刻停止层的介电层的蚀刻期间保护由铜制成的金属互连层。在蚀刻停止层上停止的介电层的蚀刻之后，用不会损坏金属互连层中的下面的铜的化学物质蚀刻蚀刻停止层。在蚀刻停止层中使用的较低介电常数材料降低了膜的总介电常数，从而提高了芯片的操作性能。

6. 发明授权

US06756300B1 Method for forming dual damascene interconnect structure 有权
标题翻译：双镶嵌互连结构的形成方法
公开(公告)号：US06756300B1
公开(公告)日：2004-06-29
申请号：US10324259
申请日：2002-12-18
申请人： Fei Wang , Jerry Cheng , Lynne A. Okada , Minh Quoc Tran , Lu You
发明人： Fei Wang , Jerry Cheng , Lynne A. Okada , Minh Quoc Tran , Lu You
IPC分类号： H01L214763
CPC分类号： H01L21/76811 , H01L21/76813
摘要： For forming a dual damascene opening within a dielectric material, a via mask material and a trench mask material are formed over the dielectric material. A trench opening is formed through the trench mask material, and a via opening is formed through a via mask patterning material disposed over the via and trench mask materials. The via and trench mask materials exposed through the via opening of the via mask patterning material are etched away, and the via mask patterning material is etched away. A portion of the dielectric material exposed through the via opening is etched down to the underlying interconnect structure, and a portion of the dielectric material exposed through the trench opening is etched, to form the dual damascene opening.
摘要翻译：为了在介电材料内形成双镶嵌开口，在电介质材料上形成通孔掩模材料和沟槽掩模材料。通过沟槽掩模材料形成沟槽开口，并且通过布置在通孔和沟槽掩模材料上方的通孔掩模图案形成材料形成通孔开口。通过通孔掩模图形材料的通路孔露出的通孔和沟槽掩模材料被蚀刻掉，并且通孔掩模图案材料被蚀刻掉。通过通孔开口暴露的介电材料的一部分被蚀刻到下面的互连结构上，并且蚀刻通过沟槽开口露出的电介质材料的一部分，以形成双镶嵌开口。

7. 发明授权

US06632707B1 Method for forming an interconnect structure using a CVD organic BARC to mitigate via poisoning 有权
标题翻译：使用CVD有机BARC形成互连结构以减轻中毒的方法
公开(公告)号：US06632707B1
公开(公告)日：2003-10-14
申请号：US10058227
申请日：2002-01-29
申请人： Fei Wang , Lynne A. Okada , Ramkumar Subramanian , James K. Kai , Calvin T. Gabriel , Lu You
发明人： Fei Wang , Lynne A. Okada , Ramkumar Subramanian , James K. Kai , Calvin T. Gabriel , Lu You
IPC分类号： H01L2144
CPC分类号： H01L21/76808
摘要： A method for forming a metal interconnect structure in a semiconductor device with the elimination of via poisoning during trench mask formation employs a CVD organic BARC that isolates the low k dielectric film. The CVD organic BARC is deposited over the low k dielectric film and in the via hole. Once the trench mask has been formed on the CVD organic BARC, the CVD organic BARC may be removed in the same process as the photoresist of the trench mask layer. A properly formed trench will have been created since the via poisoning and resist scumming were substantially eliminated by the presence of the CVD organic BARC.
摘要翻译：在沟槽掩模形成期间消除通孔中毒的在半导体器件中形成金属互连结构的方法使用隔离低k绝缘膜的CVD有机BARC。 CVD有机BARC沉积在低k电介质膜和通孔中。一旦在CVD有机BARC上形成了沟槽掩模，就可以以与沟槽掩模层的光致抗蚀剂相同的工艺去除CVD有机BARC。由于CVD有机BARC的存在基本上消除了通孔中毒和抵抗浮渣，所以将形成一个正确形成的沟槽。

8. 发明授权

US07001840B1 Interconnect with multiple layers of conductive material with grain boundary between the layers 有权
标题翻译：与层之间具有晶界的多层导电材料互连
公开(公告)号：US07001840B1
公开(公告)日：2006-02-21
申请号：US10361332
申请日：2003-02-10
申请人： Minh Quoc Tran , Lu You , Fei Wang , Lynne Okada
发明人： Minh Quoc Tran , Lu You , Fei Wang , Lynne Okada
IPC分类号： H01L21/44
CPC分类号： H01L21/76879 , H01L21/2885
摘要： An interconnect structure is formed with a plurality of layers of a conductive material with a grain boundary between any two adjacent layers of the conductive material. Such grain boundaries between layers of conductive material act as shunt by-pass paths for migration of atoms of the conductive material to minimize migration of atoms of the conductive material along the interface between a dielectric passivation or capping layer and the interconnect structure. When the interconnect structure is a via structure, each of the layers of the conductive material and each of the grain boundary are formed to be perpendicular to a direction of current flow through the via structure. Such grain boundaries formed between the plurality of layers of conductive material in the via structure minimize charge carrier wind-force along the direction of current flow through the via structure to further minimize electromigration failure of the via structure.
摘要翻译：互连结构形成有导电材料的多层，在导电材料的任何两个相邻层之间具有晶界。导电材料层之间的这种晶界作为用于迁移导电材料的原子的分流旁通路径，以最小化导电材料原子沿着介电钝化层或覆盖层与互连结构之间的界面的迁移。当互连结构是通孔结构时，导电材料的每个层和每个晶界形成为垂直于通过过孔结构的电流的方向。在通孔结构中的多个导电材料层之间形成的这种晶界沿着通过通孔结构的电流流动的方向最小化载流子的风力，以进一步最小化通孔结构的电迁移故障。

9. 发明授权

US06689684B1 Cu damascene interconnections using barrier/capping layer 有权
标题翻译：铜镶嵌互连使用屏障/覆盖层
公开(公告)号：US06689684B1
公开(公告)日：2004-02-10
申请号：US09783619
申请日：2001-02-15
申请人： Lu You , Fei Wang , Richard J. Huang
发明人： Lu You , Fei Wang , Richard J. Huang
IPC分类号： H01L214763
CPC分类号： H01L21/76844 , H01L21/76804 , H01L21/7681 , H01L21/76834 , H01L21/76849 , H01L21/76862 , H01L21/76865
摘要： Interconnects to an underlying Cu feature are formed with improved reliability by replacing a portion of the capping layer in the bottom of an opening in an overlying dielectric layer, e.g., an ILD, with a barrier material, such as Ta or TaN. During Ar sputter etching to round the ILD corners, the exposed barrier layer portion is removed and redeposited to form a liner on the side surfaces of the dielectric layer defining the opening, thereby avoiding Cu redeposition on, and/or penetration through, the side surfaces of the dielectric layer.
摘要翻译：通过用诸如Ta或TaN的阻挡材料替换上覆电介质层（例如ILD）中的开口底部的覆盖层的一部分，形成具有改进的可靠性的互连件。在Ar溅射蚀刻以绕过ILD拐角期间，暴露的阻挡层部分被去除并重新沉积以在限定开口的电介质层的侧表面上形成衬垫，从而避免Cu再沉积和/或穿透侧面的介电层。

10. 发明授权

US06677679B1 Use of SiO2/Sin for preventing copper contamination of low-k dielectric layers 有权
标题翻译：使用SiO2 / Sin来防止低k电介质层的铜污染
公开(公告)号：US06677679B1
公开(公告)日：2004-01-13
申请号：US09776749
申请日：2001-02-06
申请人： Lu You , Fei Wang , Dawn M. Hopper
发明人： Lu You , Fei Wang , Dawn M. Hopper
IPC分类号： H01L214763
CPC分类号： H01L21/76832 , H01L21/76802 , H01L21/76804 , H01L21/76807 , H01L21/76831 , H01L21/76834
摘要： A semiconductor device includes a first metallization level, a first diffusion barrier layer, a first etch stop layer, a second etch top layer, a dielectric layer and an opening extending through the dielectric layer, the first and second etch stop layers, and the first diffusion barrier layer. The first diffusion barrier layer is disposed over the first metallization level. The second etch stop layer is disposed over the first diffusion barrier layer, and the first etch stop layer is disposed on the second etch stop layer with a first interface therebetween. The dielectric layer is disposed over the first etch stop layer. The opening can also have rounded corners. A sidewall diffusion barrier layer can be disposed on sidewalls of the opening, and the sidewall diffusion barrier layer is formed from the same material as the first diffusion barrier layer. The first etch stop layer and the barrier diffusion layer can be formed from silicon nitride, and the second etch stop layer can be formed from silicon oxide. Metal within the opening forms a second metal feature, and the metal can comprise copper or a copper alloy. A method of manufacturing the semiconductor device is also disclosed.
摘要翻译：半导体器件包括第一金属化水平，第一扩散阻挡层，第一蚀刻停止层，第二蚀刻顶层，介电层和延伸穿过介电层的开口，第一和第二蚀刻停止层以及第一蚀刻停止层扩散阻挡层。第一扩散阻挡层设置在第一金属化层上。第二蚀刻停止层设置在第一扩散阻挡层上，并且第一蚀刻停止层设置在第二蚀刻停止层上，其间具有第一界面。介电层设置在第一蚀刻停止层上。开口也可以有圆角。侧壁扩散阻挡层可以设置在开口的侧壁上，并且侧壁扩散阻挡层由与第一扩散阻挡层相同的材料形成。第一蚀刻停止层和阻挡扩散层可以由氮化硅形成，并且第二蚀刻停止层可以由氧化硅形成。开口内的金属形成第二金属特征，金属可以包括铜或铜合金。还公开了制造半导体器件的方法。

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