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61. 发明申请

US20130016564A1 ERASE TECHNIQUES AND CIRCUITS THEREFOR FOR NON-VOLATILE MEMORY DEVICES 失效
标题翻译：用于非易失性存储器件的擦除技术和电路
公开(公告)号：US20130016564A1
公开(公告)日：2013-01-17
申请号：US13181988
申请日：2011-07-13
申请人： Vincenzo Ferragina , Stefano Surico , Giuseppe Moioli , Simone Bartoli
发明人： Vincenzo Ferragina , Stefano Surico , Giuseppe Moioli , Simone Bartoli
IPC分类号： G11C16/14 , G11C16/16
CPC分类号： G11C16/3445 , G11C16/0483 , G11C16/16 , G11C16/3418
摘要： Disclosed herein is a method that comprises applying a first voltage to a memory cell, applying again the first voltage to the memory cell when the memory cell have not been shifted to an erased condition, and applying a second voltage to the memory cell when the memory cell have not still been shifted to an erased condition, the second voltage being higher than the first voltage.
摘要翻译：本文公开了一种方法，其包括向存储器单元施加第一电压，当存储器单元未被移位到擦除状态时再次将第一电压施加到存储器单元，以及当存储器向存储器单元施加第二电压时，单元还没有被移动到擦除状态，第二电压高于第一电压。

62. 发明申请

US20080250191A1 FLEXIBLE, LOW COST APPARATUS AND METHOD TO INTRODUCE AND CHECK ALGORITHM MODIFICATIONS IN A NON-VOLATILE MEMORY 有权
标题翻译：灵活，低成本的设备和方法来引导和检查非易失性存储器中的算法修改
公开(公告)号：US20080250191A1
公开(公告)日：2008-10-09
申请号：US11696288
申请日：2007-04-04
申请人： Stefano Surico , Stefano Sivero , Simone Bartoli , Marco Passerini
发明人： Stefano Surico , Stefano Sivero , Simone Bartoli , Marco Passerini
IPC分类号： G06F12/00
CPC分类号： G11C16/10
摘要： A flash memory includes input/output buffers, a memory array having memory cells coupled to the input/output buffers, and row and column decoders, and a voltage-generator circuit coupled to the row and column decoders. A microcontroller is coupled to the command user interface. Switch-instruction circuitry selectively provides instructions to the microcontroller from the read-only memory and from off chip through on-board t-latches coupled to the input/output buffers under control of a command user interface.
摘要翻译：闪速存储器包括输入/输出缓冲器，具有耦合到输入/输出缓冲器的存储器单元的存储器阵列以及行和列解码器，以及耦合到行和列解码器的电压发生器电路。微控制器耦合到命令用户界面。开关指令电路在命令用户界面的控制下，从只读存储器和从芯片到板上t锁存器选择性地向微控制器提供指令，耦合到输入/输出缓冲器。

63. 发明申请

US20080165585A1 ERASE VERIFY METHOD FOR NAND-TYPE FLASH MEMORIES 有权
标题翻译：用于NAND型闪存存储器的擦除验证方法
公开(公告)号：US20080165585A1
公开(公告)日：2008-07-10
申请号：US11619978
申请日：2007-01-04
申请人： Stefano Surico , Marco Passerini , Fabio Tassan Caser , Simone Bartoli
发明人： Stefano Surico , Marco Passerini , Fabio Tassan Caser , Simone Bartoli
IPC分类号： G11C16/06
CPC分类号： G11C16/344 , G11C16/0483
摘要： An erase-verify method for a NAND flash memory includes a serial double-step erase verify. A verify operation is performed on cells in the unit connected to even word lines by biasing all the even word lines at the read voltage value used in read mode, and by biasing all the odd word lines at the pass voltage value used in read mode of the selected unit. A verify operation is performed on the cells connected to odd word lines by biasing all the odd word lines at the read voltage value used in read mode and by biasing the all even word lines at the pass voltage value used in read mode of the selected unit. Verifying the odd and even word lines may be performed in either order.
摘要翻译： NAND闪存的擦除验证方法包括串行双步擦除验证。通过在读取模式下使用的读取电压值偏置所有偶数字线，并且通过在读取模式中使用的通过电压值偏置所有奇数字线，对连接到偶数字线的单元中的单元执行验证操作所选单位。通过在读取模式中使用的读取电压值偏置所有奇数字线并且通过在所选择的单元的读取模式中使用的通过电压值偏置所有偶数字线来对连接到奇数字线的单元执行验证操作。验证奇数和偶数字线可以以任何顺序执行。

64. 发明授权

US07333389B2 Column decoding architecture for flash memories 有权
标题翻译：闪存的列解码架构
公开(公告)号：US07333389B2
公开(公告)日：2008-02-19
申请号：US11126441
申请日：2005-05-11
申请人： Stefano Sivero , Simone Bartoli , Fabio Tassan Caser , Riccardo Riva Reggiori
发明人： Stefano Sivero , Simone Bartoli , Fabio Tassan Caser , Riccardo Riva Reggiori
IPC分类号： G11C8/00
CPC分类号： G11C8/10 , G11C16/26
摘要： An improved method and device for column decoding for flash memory devices utilizes a burst page with a length greater than the length of a logical page. When a misalignment of an initial address occurs, valid reads across logical page boundaries are possible. The memory device enters the wait state only when a read crosses a burst page boundary. This minimizes the amount of time in which the memory device enters the wait state. In the preferred embodiment, this is achieved with a different management of the control signals that feed the third level of a three-level decoding stage column decoder. Changes to the architecture or in the number of column decoder selectors are not required. The memory access time during synchronous reads is thus improved.
摘要翻译：用于闪存器件的列解码的改进方法和装置利用长度大于逻辑页长度的突发页。当发生初始地址的错位时，跨逻辑页面边界的有效读取是可能的。只有当读取跨越突发页面边界时，存储器件才进入等待状态。这使存储器件进入等待状态的时间量最小化。在优选实施例中，这通过对馈送三电平解码级列解码器的第三电平的控制信号的不同管理来实现。不需要对架构或列解码器选择器的数量进行更改。因此，同步读取期间的存储器访问时间得到改善。

65. 发明申请

US20070083699A1 System for configuring parameters for a flash memory 有权
标题翻译：用于配置闪存的参数的系统
公开(公告)号：US20070083699A1
公开(公告)日：2007-04-12
申请号：US11635315
申请日：2006-12-07
申请人： Stefano Surico , Simone Bartoli , Mirella Marsella , Giorgio Bosisio
发明人： Stefano Surico , Simone Bartoli , Mirella Marsella , Giorgio Bosisio
IPC分类号： G06F12/00
CPC分类号： G11C16/20 , G11C16/04 , G11C29/02 , G11C29/021 , G11C29/028 , G11C2029/4402
摘要： System for configuring parameters used in flash memory devices. A load instruction and associated address are retrieved from a memory, and the address is used to select a configuration register storing a configuration value. The configuration value is loaded to an associated dedicated register to configure a parameter of the flash memory in a flash memory operation.
摘要翻译：用于配置闪存设备中使用的参数的系统。从存储器检索加载指令和相关联的地址，并且该地址用于选择存储配置值的配置寄存器。配置值加载到相关联的专用寄存器，以在闪存操作中配置闪存的参数。

66. 发明授权

US07181565B2 Method and system for configuring parameters for flash memory 有权
标题翻译：闪存配置参数的方法和系统
公开(公告)号：US07181565B2
公开(公告)日：2007-02-20
申请号：US11272206
申请日：2005-11-10
申请人： Stefano Surico , Simone Bartoli , Mirella Marsella , Giorgio Bosisio
发明人： Stefano Surico , Simone Bartoli , Mirella Marsella , Giorgio Bosisio
IPC分类号： G06F12/00
CPC分类号： G11C16/20 , G11C16/04 , G11C29/02 , G11C29/021 , G11C29/028 , G11C2029/4402
摘要： Method and system for configuring parameters used in flash memory devices. A load instruction and associated address are retrieved from a read-only memory, and the address is used to select a configuration register storing a configuration value. The configuration value is loaded to an associated dedicated register to configure a parameter of the flash memory in a flash memory operation. In another aspect, one or more selected configuration values not stored in a ROM are changed if a tested flash memory operation is not within desired specifications.
摘要翻译：用于配置闪存设备中使用的参数的方法和系统。从只读存储器检索加载指令和相关联的地址，并且该地址用于选择存储配置值的配置寄存器。配置值加载到相关联的专用寄存器，以在闪存操作中配置闪存的参数。在另一方面，如果测试的闪速存储器操作不在期望的规格内，则不存储在ROM中的一个或多个选择的配置值被改变。

67. 发明申请

US20060161727A1 Method and system for managing a suspend request in a flash memory 有权
标题翻译：用于管理闪存中的挂起请求的方法和系统
公开(公告)号：US20060161727A1
公开(公告)日：2006-07-20
申请号：US11145457
申请日：2005-06-02
申请人： Stefano Surico , Simone Bartoli , Monica Marziani , Luca Figini
发明人： Stefano Surico , Simone Bartoli , Monica Marziani , Luca Figini
IPC分类号： G06F12/00
CPC分类号： G06F12/0246
摘要： System and method for the managing of suspend requests in flash memory devices. The system includes a microcontroller performing a modify operation on a flash memory array, a memory coupled to the microcontroller and storing suspend sequence code for causing a suspension of the modify operation when executed by the microcontroller, and suspend circuitry that receives a suspend request from a user to suspend the modify operation and starts the execution of the suspend sequence code.
摘要翻译：用于管理闪存设备中的挂起请求的系统和方法。该系统包括微控制器，对闪速存储器阵列执行修改操作，耦合到微控制器的存储器和存储用于在由微控制器执行时引起修改操作暂停的暂停序列代码，以及从微控制器接收暂停请求的暂停电路用户暂停修改操作并开始执行挂起序列代码。

68. 发明授权

US06195290B1 Method of avoiding disturbance during the step of programming and erasing an electrically programmable, semiconductor non-volatile storage device 有权
标题翻译：在编程和擦除电可编程的半导体非易失性存储装置的步骤期间避免干扰的方法
公开(公告)号：US06195290B1
公开(公告)日：2001-02-27
申请号：US09407135
申请日：1999-09-27
申请人： Marco Dallabora , Corrado Villa , Simone Bartoli , Marco Defendi
发明人： Marco Dallabora , Corrado Villa , Simone Bartoli , Marco Defendi
IPC分类号： G11C1134
CPC分类号： G11C16/344 , G11C16/10 , G11C16/16 , G11C16/3418 , G11C16/3427 , G11C16/3445 , G11C16/3459
摘要： A method of avoiding disturbance during the step of programming and erasing an electrically programmable, semiconductor integrated non-volatile memory device which includes a matrix of memory cells divided into sectors and programmable in a byte mode is disclosed. An operation of verification of the contents of the byte to be programmed, to be carried out for each individual bit, is provided even before the first program pulse is applied. The method also provides for the parallel erasing of several sectors during an erase step, and a verification of the erase step for each sector in the matrix. If the verification shows that a sector has been erased, the sector is applied no further erase pulses.
摘要翻译：公开了一种在编程和擦除电可编程的半导体集成非易失性存储器件的步骤中避免干扰的方法，其包括被划分成扇区并以字节模式编程的存储器单元矩阵。即使在施加第一编程脉冲之前，也提供对要被编程的要被编程的字节的内容的验证的操作。该方法还提供了在擦除步骤期间并行擦除几个扇区，以及对矩阵中的每个扇区的擦除步骤的验证。如果验证显示扇区已被擦除，则扇区不再施加擦除脉冲。

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