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61. 发明申请

US20080315304A1 Thin silicon-on-insulator high voltage auxiliary gated transistor 有权
标题翻译：薄绝缘体上的高压辅助门控晶体管
公开(公告)号：US20080315304A1
公开(公告)日：2008-12-25
申请号：US11821681
申请日：2007-06-25
申请人： Sheng Teng Hsu , Jong-Jan Lee
发明人： Sheng Teng Hsu , Jong-Jan Lee
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L29/7824 , H01L29/0657 , H01L29/66689 , H01L29/66772 , H01L29/7831 , H01L29/78624 , H01L29/78645 , H01L29/78654
摘要： A silicon (Si)-on-insulator (SOI) high voltage transistor is provided with an associated fabrication process. The method provides a SOI substrate with a Si top layer. A control channel and an adjacent auxiliary channel are formed in the Si top layer. A control gate overlies the control channel and an auxiliary gate overlies the auxiliary channel. A source region is formed adjacent the control channel, and a lightly doped drain (LDD) region is interposed between the auxiliary channel and the drain. An interior drain region is interposed between the control and auxiliary channels. Typically, the Si top layer has a thickness in the range of 20 to 1000 nm. In one aspect, the Si top layer in the source, control channel, interior drain, and auxiliary channel regions is thinned to a thickness in the range of 5 to 200 nm, and raised source, drain, LDD, and interior drain regions are formed.
摘要翻译：硅（Si）绝缘体（SOI）高压晶体管具有相关的制造工艺。该方法提供具有Si顶层的SOI衬底。控制通道和相邻的辅助通道形成在Si顶层中。控制门覆盖控制通道，辅助门覆盖辅助通道。在控制通道附近形成源极区，并且在辅助沟道和漏极之间插入轻掺杂漏极（LDD）区域。内部漏极区域介于控制和辅助通道之间。通常，Si顶层的厚度在20至1000nm的范围内。在一个方面，源极，控制沟道，内部漏极和辅助沟道区域中的Si顶层被薄化到5至200nm范围内的厚度，并且形成升高的源极，漏极，LDD和内部漏极区域。

62. 发明申请

US20080303072A1 CMOS Active Pixel Sensor 有权
标题翻译： CMOS有源像素传感器
公开(公告)号：US20080303072A1
公开(公告)日：2008-12-11
申请号：US12178169
申请日：2008-07-23
申请人： Jong-Jan Lee , Sheng Teng Hsu , Douglas James Tweet , Jer-Shen Maa
发明人： Jong-Jan Lee , Sheng Teng Hsu , Douglas James Tweet , Jer-Shen Maa
IPC分类号： H01L31/113
CPC分类号： H01L27/14647
摘要： A CMOS active pixel sensor includes a silicon-on-insulator substrate having a silicon substrate with an insulator layer formed thereon and a top silicon layer formed on the insulator layer. A stacked pixel sensor cell includes a bottom photodiode fabricated on the silicon substrate, for sensing light of a longest wavelength; a middle photodiode fabricated on the silicon substrate, for sensing light of a medium wavelength, which is stacked above the bottom photodiode; and a top photodiode fabricated on the top silicon layer, for sensing light of a shorter wavelength, which is stacked above the middle and bottom photodiodes. Pixel transistor sets are fabricated on the top silicon layer and are associated with each pixel sensor cell by electrical connections which extend between each of the photodiodes and respective pixel transistor(s). CMOS control circuitry is fabricated adjacent to an array of active pixel sensor cells and electrically connected thereto.
摘要翻译： CMOS有源像素传感器包括具有在其上形成有绝缘体层的硅衬底和形成在绝缘体层上的顶部硅层的绝缘体上硅衬底。层叠像素传感器单元包括：制造在硅衬底上的底部光电二极管，用于感测最长波长的光; 制造在硅衬底上的中间光电二极管，用于感测中等波长的光; 和制造在顶部硅层上的顶部光电二极管，用于感测较短波长的光，该光被层叠在中间和底部光电二极管的上方。像素晶体管组被制造在顶部硅层上，并且通过在每个光电二极管和相应的像素晶体管之间延伸的电连接与每个像素传感器单元相关联。 CMOS控制电路与有源像素传感器单元的阵列相邻并且与其电连接。

63. 发明授权

US07390725B2 Strained silicon on insulator from film transfer and relaxation by hydrogen implantation 有权
标题翻译：绝缘体上的应变硅通过氢注入从膜转移和弛豫
公开(公告)号：US07390725B2
公开(公告)日：2008-06-24
申请号：US11284326
申请日：2005-11-21
申请人： Jer-shen Maa , Jong-Jan Lee , Douglas J. Tweet , David R. Evans , Allen W. Burmaster , Sheng Teng Hsu
发明人： Jer-shen Maa , Jong-Jan Lee , Douglas J. Tweet , David R. Evans , Allen W. Burmaster , Sheng Teng Hsu
IPC分类号： H01L21/46 , H01L21/30
CPC分类号： H01L21/76254
摘要： Transistors fabricated on SSOI (Strained Silicon On Insulator) substrate, which comprises a strained silicon layer disposed directly on an insulator layer, have enhanced device performance due to the strain-induced band modification of the strained silicon device channel and the limited silicon volume because of the insulator layer. The present invention discloses SSOI substrate fabrication processes comprising various novel approaches. One is the use of a thin relaxed SiGe layer as the strain-induced seed layer to facilitate integration and reduce processing cost. Another is the formation of split implant microcracks deep in the silicon substrate to reduce the number of threading dislocations reaching the strained silicon layer. And lastly is a two step annealing/thinning process for the strained silicon/SiGe multilayer film transfer without blister or flaking formation.
摘要翻译：包含直接设置在绝缘体层上的应变硅层的SSOI（应变绝缘体硅）基板上制造的晶体管由于应变诱导的应变硅器件通道的带隙修改而增加了器件性能，并且由于绝缘体层。本发明公开了包含各种新颖方法的SSOI衬底制造工艺。一个是使用薄的松弛SiGe层作为应变诱导的种子层，以促进整合并降低加工成本。另一个是在硅衬底深部形成分裂的植入物微裂纹，以减少到达应变硅层的穿透位错的数量。最后是对应变硅/ SiGe多层膜转移进行两步退火/变薄处理，无需起泡或剥落形成。

64. 发明授权

US07323349B2 Self-aligned cross point resistor memory array 有权
标题翻译：自对准交叉点电阻存储器阵列
公开(公告)号：US07323349B2
公开(公告)日：2008-01-29
申请号：US11120385
申请日：2005-05-02
申请人： Sheng Teng Hsu , Jong-Jan Lee , Jer-Shen Maa , Douglas J. Tweet , Wei-Wei Zhuang
发明人： Sheng Teng Hsu , Jong-Jan Lee , Jer-Shen Maa , Douglas J. Tweet , Wei-Wei Zhuang
IPC分类号： H01L21/00 , H01L21/8242
CPC分类号： H01L27/101 , H01L27/2409 , H01L27/2481 , H01L45/04 , H01L45/1233 , H01L45/147 , H01L45/1683
摘要： A method of fabricating resistor memory array includes preparing a silicon substrate; depositing a bottom electrode, a sacrificial layer, and a hard mask layer on a substrate P+ layer; masking, patterning and etching to remove, in a first direction, a portion of the hard mask, the sacrificial material, the bottom electrode; depositing a layer of silicon oxide; masking, patterning and etching to remove, in a second direction perpendicular to the first direction, a portion of the hard mask, the sacrificial material, the bottom electrode;, and over etching to an N+ layer and at least 100 nm of the silicon substrate; depositing of a layer of silicon oxide; etching to remove any remaining hard mask and any remaining sacrificial material; depositing a layer of CMR material; depositing a top electrode; applying photoresist, patterning the photoresist and etching the top electrode; and incorporating the memory array into an integrated circuit.
摘要翻译：制造电阻器存储器阵列的方法包括制备硅衬底; 在衬底P +层上沉积底部电极，牺牲层和硬掩模层; 掩模，图案化和蚀刻以在第一方向上去除硬掩模，牺牲材料，底部电极的一部分; 沉积一层氧化硅; 掩模，图案化和蚀刻以在垂直于第一方向的第二方向上去除硬掩模，牺牲材料，底部电极的一部分，并且对N +层和至少100nm的硅衬底进行过蚀刻 ; 沉积一层氧化硅; 蚀刻以除去任何剩余的硬掩模和任何剩余的牺牲材料; 沉积一层CMR材料; 沉积顶部电极; 施加光致抗蚀剂，图案化光致抗蚀剂并蚀刻顶部电极; 并将存储器阵列并入集成电路中。

65. 发明申请

US20070278574A1 Compound semiconductor-on-silicon wafer with a thermally soft insulator 审中-公开
标题翻译：具有热软绝缘体的复合半导体硅片
公开(公告)号：US20070278574A1
公开(公告)日：2007-12-06
申请号：US11443144
申请日：2006-05-30
申请人： Sheng Teng Hsu , Tingkai Li , Jong-Jan Lee
发明人： Sheng Teng Hsu , Tingkai Li , Jong-Jan Lee
IPC分类号： H01L27/12 , H01L21/84
CPC分类号： H01L21/02381 , H01L21/0245 , H01L21/02488 , H01L21/02505 , H01L21/02529 , H01L21/02538 , H01L21/7624
摘要： A method is provided for forming a compound semiconductor-on-silicon (Si) wafer with a thermally soft insulator. The method forms a Si substrate, with a thermally soft insulator layer overlying the Si substrate. A silicon oxide layer is formed immediately overlying the thermally soft insulator layer, a top Si layer overlies the silicon oxide, and a lattice mismatch buffer layer overlies the top Si layer. A compound semiconductor layer is formed overlying the lattice mismatch buffer layer. The thermally soft insulator has a liquid phase temperature lower than the liquid phase temperatures of Si and the compound semiconductor. For example, the thermally soft insulator may have a flow temperature in the range of about 500° C. to 900° C., where the flow temperature is greater than the solid phase temperature and less than the liquid phase temperature.
摘要翻译：提供了一种用热软性绝缘体形成硅化合物半导体（Si）晶片的方法。该方法形成Si衬底，具有覆盖Si衬底的热软绝缘层。形成刚好覆盖在热软绝缘体层上的氧化硅层，顶部Si层覆盖在氧化硅上，并且晶格失配缓冲层覆盖在顶部Si层上。形成覆盖晶格失配缓冲层的化合物半导体层。该热软绝缘体的液相温度低于Si和化合物半导体的液相温度。例如，热软绝缘体可以具有在约500℃至900℃的范围内的流动温度，其中流动温度大于固相温度并且小于液相温度。

66. 发明授权

US07297564B1 Fabrication of vertical sidewalls on (110) silicon substrates for use in Si/SiGe photodetectors 有权
标题翻译：在Si / SiGe光电探测器中用于（110）硅衬底上的垂直侧壁的制造
公开(公告)号：US07297564B1
公开(公告)日：2007-11-20
申请号：US11416985
申请日：2006-05-02
申请人： Douglas J. Tweet , Jong-Jan Lee , Jer-Shen Maa , Sheng Teng Hsu
发明人： Douglas J. Tweet , Jong-Jan Lee , Jer-Shen Maa , Sheng Teng Hsu
IPC分类号： H01L21/00
CPC分类号： H01L31/1812 , Y02E10/50
摘要： A method of fabricating vertical sidewalls on silicon (110) substrates for use in Si/SiGe photodetectors includes preparing a silicon (110) layer wherein the silicon (110) plane is parallel to an underlying silicon wafer surface. Masking the silicon (110) layer with mask sidewalls parallel to a silicon (111) layer plane and etching the silicon (110) layer to remove an un-masked portion thereof, leaving a patterned silicon (110) layer having vertical silicon (111) sidewalls. Removing the mask; growing SiGe-containing layers on the patterned silicon (110) layer; and fabricating a photodetector.
摘要翻译：在Si / SiGe光电探测器中使用的在硅（110）衬底上制造垂直侧壁的方法包括制备硅（110）层，其中硅（110）平面平行于下面的硅晶片表面。屏蔽具有平行于硅（111）层平面的掩模侧壁的硅（110）层并蚀刻硅（110）层以去除其未掩蔽部分，留下具有垂直硅（111）的图案化硅（110）层，侧壁取下面罩; 在图案化的硅（110）层上生长含SiGe的层; 并制造光电检测器。

67. 发明申请

US20070218613A1 Fully isolated photodiode stack 失效
标题翻译：完全隔离的光电二极管堆叠
公开(公告)号：US20070218613A1
公开(公告)日：2007-09-20
申请号：US11657152
申请日：2007-01-24
申请人： Jong-Jan Lee , Douglas J. Tweet , Sheng Teng Hsu
发明人： Jong-Jan Lee , Douglas J. Tweet , Sheng Teng Hsu
IPC分类号： H01L21/8234
CPC分类号： H01L27/14647 , H01L27/1463 , H01L27/14689
摘要： An array of fully isolated multi-junction complimentary metal-oxide-semiconductor (CMOS) filterless color imager cells is provided, together with an associated fabrication method. The method provides a bulk silicon (Si) substrate. A plurality of color imager cells are formed, either in the Si substrate, or in a single epitaxial Si layer formed over the substrate. Each color imager cell includes a photodiode set with a first, second, and third photodiode formed as a stacked multi-junction structure. A U-shaped (in cross-section) well liner, fully isolates the photodiode set from adjacent photodiode sets in the array. For example, each photodiode is formed from a p doped Si layer physically interfaced to a first wall. A well bottom physically interfaces to the first wall, and the p doped Si layer of the third, bottom-most, photodiode is part of the well bottom. Then, the photodiode sets may be formed from an n/p/n/p/n/p or n/p/p−/p/p−/p layered structure.
摘要翻译：提供了完全隔离的多结互补金属氧化物半导体（CMOS）无滤膜彩色成像器单元的阵列，以及相关的制造方法。该方法提供体硅（Si）衬底。在Si衬底中或在衬底上形成的单个外延Si层中形成多个彩色成像器单元。每个彩色成像器单元包括具有形成为堆叠多结结构的第一，第二和第三光电二极管。 U形（横截面）井衬管，将阵列中的光电二极管组与相邻的光电二极管组完全隔离。例如，每个光电二极管由物理上与第一壁物理连接的p掺杂Si层形成。阱底部与第一壁物理接口，第三，最底部的光电二极管的p掺杂Si层是阱底部的一部分。然后，光电二极管组可以由n / p / n / p / n / p或n / p / p / p / p / p层叠结构形成。

68. 发明授权

US07157300B2 Fabrication of thin film germanium infrared sensor by bonding to silicon wafer 有权
标题翻译：通过粘合到硅晶片制造薄膜锗红外传感器
公开(公告)号：US07157300B2
公开(公告)日：2007-01-02
申请号：US10993533
申请日：2004-11-19
申请人： Jong-Jan Lee , Jer-Shen Maa , Sheng Teng Hsu , Douglas J. Tweet
发明人： Jong-Jan Lee , Jer-Shen Maa , Sheng Teng Hsu , Douglas J. Tweet
IPC分类号： H01L21/00
CPC分类号： H01L31/1804 , H01L21/187 , H01L21/76254 , H01L27/1443 , H01L31/02327 , H01L31/105 , Y02E10/547 , Y02P70/521
摘要： A method of fabricating a thin film germanium photodetector includes preparing a silicon substrate; fabricating a CMOS device on the silicon substrate; preparing a germanium substrate; preparing surfaces of each substrate for bonding; bonding the germanium substrate to the CMOS-bearing silicon substrate to form a bonded structure; removing a portion of the germanium substrate from the bonded structure; forming a PIN diode in the germanium substrate; removing a portion of the germanium layer by etching; and completing the germanium photo detector.
摘要翻译：制造薄膜锗光电探测器的方法包括制备硅衬底; 在硅衬底上制造CMOS器件; 制备锗衬底; 准备每个基板的表面以进行接合; 将锗衬底结合到具有CMOS的硅衬底以形成结合结构; 从结合结构去除锗衬底的一部分; 在锗衬底中形成PIN二极管; 通过蚀刻去除锗层的一部分; 并完成锗光电检测器。

69. 发明授权

US07115945B2 Strained silicon fin structure 有权
公开(公告)号：US07115945B2
公开(公告)日：2006-10-03
申请号：US11327092
申请日：2006-01-06
申请人： Jong-Jan Lee , Sheng Teng Hsu , Douglas J. Tweet , Jer-Shen Maa
发明人： Jong-Jan Lee , Sheng Teng Hsu , Douglas J. Tweet , Jer-Shen Maa
IPC分类号： H01L29/786
CPC分类号： H01L29/785 , H01L29/1054 , H01L29/66795 , H01L29/78687
摘要： Disclosing is a strained silicon finFET device having a strained silicon fin channel in a double gate finFET structure. The disclosed finFET device is a double gate MOSFET consisting of a silicon fin channel controlled by a self-aligned double gate for suppressing short channel effect and enhancing drive current. The silicon fin channel of the disclosed finFET device is a strained silicon fin channel, comprising a strained silicon layer deposited on a seed fin having different lattice constant, for example, a silicon layer deposited on a silicon germanium seed fin, or a carbon doped silicon layer deposited on a silicon seed fin. The lattice mismatch between the silicon layer and the seed fin generates the strained silicon fin channel in the disclosed finFET device to improve hole and electron mobility enhancement, in addition to short channel effect reduction characteristic inherently in a finFET device.

70. 发明授权

US07078298B2 Silicon-on-nothing fabrication process 失效
标题翻译：无硅制造工艺
公开(公告)号：US07078298B2
公开(公告)日：2006-07-18
申请号：US10441674
申请日：2003-05-20
申请人： Jong-Jan Lee , Sheng Teng Hsu
发明人： Jong-Jan Lee , Sheng Teng Hsu
IPC分类号： H01L21/336
CPC分类号： H01L29/66772 , H01L21/76264 , H01L21/76283 , H01L21/76289 , H01L21/764 , H01L21/84 , H01L27/1203 , H01L29/78639 , H01L29/78654
摘要： A method to fabricate a silicon-on-nothing device on a silicon substrate is provided. The disclosed silicon-on-nothing device is fabricated on an isolated floating silicon active area, thus completely isolated from the silicon substrate by an air gap. The isolated floating silicon active area is fabricated on a silicon germanium layer with a surrounding isolation trench. A plurality of anchors is then fabricated to anchor the silicon active area to the silicon substrate before selectively etching the silicon germanium layer to form the air gap. Isolation trench fill and planarization complete the formation of the isolated floating silicon active area. The silicon-on-nothing device on the isolated floating silicon active area can be polysilicon gate or metal gate and with or without raised source and drain regions.
摘要翻译：提供了一种在硅衬底上制造无硅器件的方法。公开的无硅无源器件制造在隔离的浮动硅有源区上，因此通过气隙与硅衬底完全隔离。隔离的浮动硅有源区域在具有周围隔离沟槽的硅锗层上制造。然后在选择性地蚀刻硅锗层以形成气隙之前，制造多个锚固件以将硅有源区域锚定到硅衬底。隔离沟填充和平坦化完成隔离浮动硅活性区的形成。隔离浮置硅有源区上的无硅器件可以是多晶硅栅极或金属栅极，并且具有或不具有升高的源极和漏极区域。

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