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61. 发明申请

US20070047293A1 DUAL PORT GAIN CELL WITH SIDE AND TOP GATED READ TRANSISTOR 有权
标题翻译：双端口增益单元与侧面和顶部读取晶体管
公开(公告)号：US20070047293A1
公开(公告)日：2007-03-01
申请号：US11161962
申请日：2005-08-24
申请人： Jack Mandelman , Kangguo Cheng , Ramachandra Divakaruni , Carl Radens , Geng Wang
发明人： Jack Mandelman , Kangguo Cheng , Ramachandra Divakaruni , Carl Radens , Geng Wang
IPC分类号： G11C11/24
CPC分类号： H01L27/108 , H01L27/10829 , H01L27/10867 , H01L27/1203
摘要： A DRAM memory cell and process sequence for fabricating a dense (20 or 18 square) layout is fabricated with silicon-on-insulator (SOI) CMOS technology. Specifically, the present invention provides a dense, high-performance SRAM cell replacement that is compatible with existing SOI CMOS technologies. Various gain cell layouts are known in the art. The present invention improves on the state of the art by providing a dense layout that is fabricated with SOI CMOS. In general terms, the memory cell includes a first transistor provided with a gate, a source, and a drain respectively; a second transistor having a first gate, a second gate, a source, and a drain respectively; and a capacitor having a first terminal, wherein the first terminal of said capacitor and the second gate of said second transistor comprise a single entity.
摘要翻译：使用绝缘体上硅（SOI）CMOS技术制造用于制造致密（20或18平方）布局的DRAM存储单元和工艺顺序。具体地，本发明提供了与现有SOI CMOS技术兼容的致密的高性能SRAM单元替换。各种增益单元布局在本领域中是已知的。本发明通过提供利用SOI CMOS制造的致密布局来改善现有技术的状态。通常，存储单元包括分别设置有栅极，源极和漏极的第一晶体管; 分别具有第一栅极，第二栅极，源极和漏极的第二晶体管; 以及具有第一端子的电容器，其中所述电容器的第一端子和所述第二晶体管的第二栅极包括单个实体。

62. 发明授权

US07122437B2 Deep trench capacitor with buried plate electrode and isolation collar 有权
标题翻译：深沟槽电容器，埋置电极和隔离环
公开(公告)号：US07122437B2
公开(公告)日：2006-10-17
申请号：US10741203
申请日：2003-12-19
申请人： Thomas W. Dyer , Chun-yung Sung , Ravikumar Ramachandran , Ramachandra Divakaruni , Carl Radens
发明人： Thomas W. Dyer , Chun-yung Sung , Ravikumar Ramachandran , Ramachandra Divakaruni , Carl Radens
IPC分类号： H01L21/8242
CPC分类号： H01L27/1087 , H01L29/945
摘要： A deep trench capacitor used in a trench DRAM includes a buried plate and an isolation collar. The deep trench is bottle-shaped, and the isolation collar is formed in upper portion of the wider region of the bottle-shaped trench. The buried plate surrounds the lower portion of the wider part of the bottle-shaped trench, and hemispherical grain polysilicon lines the walls of at least the lower portion of the wider part of the trench. A nitride liner layer lines the inner walls of the oxide collar and prevents diffusion of dopant through the oxide collar into the substrate when the HSG polysilicon and the doped buried plate are formed. The buried plate region is self-aligned to the isolation collar. The depth of the top of the wider part of the bottle shape and the bottom depth of the isolation collar are determined by successive resist deposition and recessing steps.
摘要翻译：在沟槽DRAM中使用的深沟槽电容器包括掩埋板和隔离环。深沟是瓶形的，并且隔离套环形成在瓶形沟槽的较宽区域的上部。掩埋板围绕瓶形沟槽的较宽部分的下部，半球状晶粒多晶硅线路至少沟槽较宽部分的下部的壁。当形成HSG多晶硅和掺杂掩埋板时，氮化物衬垫层线化氧化物环的内壁并防止掺杂剂通过氧化物环到衬底中的扩散。掩埋板区域与隔离套环自对准。通过连续的抗蚀剂沉积和凹陷步骤确定瓶子形状的较宽部分的顶部的深度和隔离环的底部深度。

63. 发明申请

US20060226481A1 SIMPLIFIED VERTICAL ARRAY DEVICE DRAM/eDRAM INTEGRATION: METHOD AND STRUCTURE 有权
标题翻译：简化的垂直阵列设备DRAM / eDRAM集成：方法和结构
公开(公告)号：US20060226481A1
公开(公告)日：2006-10-12
申请号：US10907630
申请日：2005-04-08
申请人： Deok-kee Kim , Ramachandra Divakaruni , Carl Radens , Dae-Gyu Park
发明人： Deok-kee Kim , Ramachandra Divakaruni , Carl Radens , Dae-Gyu Park
IPC分类号： H01L27/12
CPC分类号： H01L27/12 , H01L27/10841 , H01L27/10891
摘要： The present invention provides a semiconductor structure that includes an active wordline located above a semiconductor memory device and a passive wordline located adjacent to said active wordline and above an active area of a substrate. In accordance with the present invention, the passive wordline is separated from the active area by a pad nitride. The present invention also provides methods that are capable of forming the inventive semiconductor structure.
摘要翻译：本发明提供一种半导体结构，其包括位于半导体存储器件上方的有源字线和位于所述有源字线附近并位于衬底的有效区域之上的被动字线。根据本发明，被动字线通过衬垫氮化物与有源区分离。本发明还提供了能够形成本发明的半导体结构的方法。

64. 发明授权

US07115921B2 Nano-scaled gate structure with self-interconnect capabilities 失效
标题翻译：具有自相互连接能力的纳米级栅极结构
公开(公告)号：US07115921B2
公开(公告)日：2006-10-03
申请号：US10930989
申请日：2004-08-31
申请人： Lawrence A. Clevenger , Timothy Joseph Dalton , Louis L. Hsu , Carl Radens , Keith Kwong Hon Wong , Chih-Chao Yang
发明人： Lawrence A. Clevenger , Timothy Joseph Dalton , Louis L. Hsu , Carl Radens , Keith Kwong Hon Wong , Chih-Chao Yang
IPC分类号： H01L29/80 , H01L29/76 , H01L21/337 , H01L21/336
CPC分类号： H01L21/28114 , H01L21/76895 , H01L21/823425 , H01L21/823437 , H01L21/823475 , H01L27/0629 , H01L27/088 , H01L29/41783 , H01L29/6653 , H01L29/66545
摘要： Gate conductors on an integrated circuit are formed with enlarged upper portions which are utilized to electrically connect the gate conductors with other devices. A semiconductor device comprises a gate conductor with an enlarged upper portion which electrically connects the gate conductor to a local diffusion region. Another semiconductor device comprises two gate conductors with enlarged upper portions which merge to create electrically interconnected gate conductors. Methods for forming the above semiconductor devices are also described and claimed.
摘要翻译：集成电路上的栅极导体形成有用于将栅极导体与其它器件电连接的较大的上部。半导体器件包括具有扩大上部的栅极导体，该栅极导体将栅极导体电连接到局部扩散区。另一个半导体器件包括两个栅极导体，其具有扩大的上部，其合并以产生电互连的栅极导体。还描述和要求保护形成上述半导体器件的方法。

65. 发明申请

US20060175660A1 VERTICAL BODY-CONTACTED SOI TRANSISTOR 有权
标题翻译：垂直接触式SOI晶体管
公开(公告)号：US20060175660A1
公开(公告)日：2006-08-10
申请号：US10906238
申请日：2005-02-10
申请人： Kangguo Cheng , Gary Bronner , Ramachandra Divakaruni , Carl Radens
发明人： Kangguo Cheng , Gary Bronner , Ramachandra Divakaruni , Carl Radens
IPC分类号： H01L27/12
CPC分类号： H01L27/1203 , H01L21/84 , H01L29/66666 , H01L29/78642
摘要： A vertical field effect transistor (“FET”) is provided which includes a transistor body region and source and drain regions disposed in a single-crystal semiconductor-on-insulator (“SOI”) region of a substrate adjacent a sidewall of a trench. The substrate includes a buried insulator layer underlying the SOI region and a bulk region underlying the buried insulator layer. A buried strap conductively connects the SOI region to a lower node disposed below the SOI region and a body contact extends from the transistor body region to the bulk region of the substrate, the body contact being insulated from the buried strap.
摘要翻译：提供了垂直场效应晶体管（“FET”），其包括晶体管本体区域和设置在与沟槽的侧壁相邻的衬底的绝缘体上的单晶半导体（“SOI”）区域中的源极和漏极区域。衬底包括在SOI区域下面的掩埋绝缘体层和埋在掩埋绝缘体层下面的主体区域。掩埋带导电地将SOI区域连接到设置在SOI区域下方的下部节点，并且主体接触从晶体管本体区域延伸到衬底的主体区域，身体接触部与掩埋带绝缘。

66. 发明申请

US20050180521A1 REDUNDANCY STRUCTURE AND METHOD FOR HIGH-SPEED SERIAL LINK 失效
标题翻译：用于高速串行链路的冗余结构和方法
公开(公告)号：US20050180521A1
公开(公告)日：2005-08-18
申请号：US10708240
申请日：2004-02-18
申请人： Louis Hsu , Carl Radens , Li-Kong Wang
发明人： Louis Hsu , Carl Radens , Li-Kong Wang
IPC分类号： H04L1/22 , H04L25/02 , H04L25/08 , H04L27/04
CPC分类号： H04L1/22 , H04L25/029 , H04L25/08
摘要： An integrated circuit is provided having a plurality of data transmitters, including a plurality of default data transmitters for transmitting data from a plurality of data sources and at least one redundancy data transmitter. A plurality of connection elements are provided having a first, low impedance connecting state and having a second, high impedance, disconnecting state. The connection elements are operable to disconnect a failing data transmitter from a corresponding output signal line and to connect the redundancy data transmitter to that output signal line in place of the failing data transmitter. In one preferred form, the connection elements include a fuse and an antifuse. In another form, the connection elements include micro-electromechanical (MEM) switches. The connecting elements preferably present the low impedance connecting state at frequencies which include signal switching frequencies above about 500 MHz.
摘要翻译：提供了具有多个数据发送器的集成电路，包括用于从多个数据源发送数据的多个默认数据发送器和至少一个冗余数据发送器。提供了具有第一低阻抗连接状态并且具有第二高阻抗断开状态的多个连接元件。连接元件可操作以将故障数据发射器与相应的输出信号线断开连接，并将冗余数据发射机连接到该输出信号线来代替故障数据发射机。在一个优选形式中，连接元件包括保险丝和反熔丝。在另一种形式中，连接元件包括微机电（MEM）开关。连接元件优选地在包括高于约500MHz的信号切换频率的频率处呈现低阻抗连接状态。

67. 发明授权

US06762447B1 Field-shield-trench isolation for gigabit DRAMs 有权
标题翻译：用于千兆位DRAM的场屏蔽沟槽隔离
公开(公告)号：US06762447B1
公开(公告)日：2004-07-13
申请号：US09245269
申请日：1999-02-05
申请人： Jack A. Mandelman , Rama Divakaruni , Giuseppe Larosa , Ulrike Gruening , Carl Radens
发明人： Jack A. Mandelman , Rama Divakaruni , Giuseppe Larosa , Ulrike Gruening , Carl Radens
IPC分类号： H01L27108
CPC分类号： H01L27/10861 , H01L21/763 , H01L21/765 , H01L27/10829 , H01L27/10897 , H01L2924/0002 , H01L2924/00
摘要： A dynamic random access memory (DRAM) formed in a semiconductor body has individual pairs of memory cells that are isolated from one another by a vertical electrical isolation trench and are isolated from support circuitry. The isolation trench has sidewalls and upper and lower portions, and encircles an area of the semiconductor body which contains the memory cells. This electrically isolates pairs of memory cells from each other and from the support circuitry contained within the semiconductor body but not located within the encircled area. The lower portion of the isolation trench is filled with an electrically conductive material that has sidewall portions thereof which are at least partly separated from the sidewalls of the lower portion of the trench by a first electrical insulator, and that has a lower portion that is in electrical contact with the semiconductor body. The upper portion of the isolation trench is filled with a second electrical insulator.
摘要翻译：形成在半导体主体中的动态随机存取存储器（DRAM）具有通过垂直电隔离沟槽彼此隔离并且与支持电路隔离的各对存储单元。隔离沟槽具有侧壁和上部和下部，并且包围包含存储单元的半导体主体的区域。这使得存储器单元对彼此和从包含在半导体本体内但不位于包围区域内的支撑电路电隔离。隔离沟槽的下部填充有导电材料，该导电材料具有其侧壁部分，其侧壁部分通过第一电绝缘体至少部分地与沟槽的下部的侧壁分离，并且其具有位于与半导体本体电接触。隔离沟槽的上部填充有第二电绝缘体。

68. 发明授权

US06420749B1 Trench field shield in trench isolation 失效
标题翻译：沟槽隔离屏蔽沟槽
公开(公告)号：US06420749B1
公开(公告)日：2002-07-16
申请号：US09602427
申请日：2000-06-23
申请人： Ramachandra Divakaruni , Jeffrey P. Gambino , Edward W. Kiewra , Jack A. Mandelman , Carl Radens , William R. Tonti
发明人： Ramachandra Divakaruni , Jeffrey P. Gambino , Edward W. Kiewra , Jack A. Mandelman , Carl Radens , William R. Tonti
IPC分类号： H01L27108
CPC分类号： H01L21/823481 , H01L21/743 , H01L21/76232 , H01L21/76895 , H01L21/823475 , H01L27/10897
摘要： A method and structure for a semiconductor device which includes a substrate comprising trenches, a plurality of devices on the substrate isolated by the trenches, conductive sidewall spacers within the trenches, and an insulator filling the trenches between the conductive sidewall spacers. A first conductive sidewall spacer is electrically connected to a first device of said plurality of devices and a second conductive sidewall spacer is electrically connected to a second device of the plurality of devices. The first device can be biased independently of the second device. A contact extends above a surface of the substrate. A first contact abuts a first device and a first conductive sidewall spacer. An insulator separates the conductive sidewall spacers. A first contact may be equidistant between the first conductor and the second conductor. The conductive sidewall spacers comprise field shields.
摘要翻译：一种用于半导体器件的方法和结构，其包括：衬底，其包括沟槽，在衬底上隔离的衬底上的多个器件，沟槽内的导电侧壁间隔物，以及填充导电侧壁间隔物之间的沟槽的绝缘体。第一导电侧壁间隔件电连接到所述多个器件中的第一器件，并且第二导电侧壁间隔件电连接到多个器件中的第二器件。第一装置可以独立于第二装置而被偏置。接触件在衬底的表面上方延伸。第一接触件邻接第一器件和第一导电侧壁间隔物。绝缘体将导电侧墙隔离开。第一接触件可以在第一导体和第二导体之间等距。导电侧壁间隔件包括场屏蔽。

69. 发明授权

US06265279B1 Method for fabricating a trench capacitor 失效
标题翻译：沟槽电容器的制造方法
公开(公告)号：US06265279B1
公开(公告)日：2001-07-24
申请号：US09404906
申请日：1999-09-24
申请人： Carl Radens , Jack A. Mandelman , Joachim Hoepfner
发明人： Carl Radens , Jack A. Mandelman , Joachim Hoepfner
IPC分类号： H01L2120
CPC分类号： H01L27/10861 , H01L27/10867 , H01L29/945
摘要： A trench capacitor, in accordance with the present invention, includes a trench formed in a substrate. The trench has a buried plate formed adjacent to a lower portion of the trench. A dielectric collar is formed along vertical sidewalls of the trench. A node diffusion region is formed adjacent to the trench for connecting to a storage node in the trench. A dopant region is formed laterally outward from the trench and adjacent to the collar, and the dopant region includes a profile having a lower portion extending further laterally outward from the trench than an upper portion of the profile wherein operation of a parasitic transistor formed adjacent to the trench between the node diffusion and the buried plate is disrupted by the dopant region. Methods for forming the dopant region are also disclosed and claimed.
摘要翻译：根据本发明的沟槽电容器包括形成在衬底中的沟槽。沟槽具有邻近沟槽下部形成的掩埋板。沿着沟槽的垂直侧壁形成介电环。在沟槽附近形成节点扩散区域，以连接到沟槽中的存储节点。掺杂剂区域从沟槽横向向外形成并且与套环相邻，并且掺杂剂区域包括轮廓，该轮廓具有比轮廓的上部更远离沟槽进一步横向向外延伸的轮廓，其中形成为邻近节点扩散和掩埋板之间的沟槽被掺杂剂区域破坏。还公开并要求保护形成掺杂剂区域的方法。

70. 发明授权

US6143599A Method for manufacturing memory cell with trench capacitor 有权
标题翻译：具有沟槽电容器的存储单元的制造方法
公开(公告)号：US6143599A
公开(公告)日：2000-11-07
申请号：US235621
申请日：1999-01-22
申请人： Byeong Y. Kim , Carl Radens , Jochen Beintner
发明人： Byeong Y. Kim , Carl Radens , Jochen Beintner
IPC分类号： H01L21/8242
CPC分类号： H01L27/10867
摘要： A memory cell includes a transistor and a capacitor that is a doped polysilicon filled trench. A doped polycrystalline strap provides a low resistance connection between a source region of the transistor and the polysilicon fill and is shaped to overlie both a top surface and a side surface of the source region of the transistor.
摘要翻译：存储单元包括晶体管和作为掺杂多晶硅填充沟槽的电容器。掺杂的多晶带提供了晶体管的源极区域和多晶硅填充物之间的低电阻连接，并且被成形为覆盖晶体管的源极区域的顶表面和侧表面。

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