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1. 发明授权

US06420749B1 Trench field shield in trench isolation 失效
标题翻译：沟槽隔离屏蔽沟槽
公开(公告)号：US06420749B1
公开(公告)日：2002-07-16
申请号：US09602427
申请日：2000-06-23
申请人： Ramachandra Divakaruni , Jeffrey P. Gambino , Edward W. Kiewra , Jack A. Mandelman , Carl Radens , William R. Tonti
发明人： Ramachandra Divakaruni , Jeffrey P. Gambino , Edward W. Kiewra , Jack A. Mandelman , Carl Radens , William R. Tonti
IPC分类号： H01L27108
CPC分类号： H01L21/823481 , H01L21/743 , H01L21/76232 , H01L21/76895 , H01L21/823475 , H01L27/10897
摘要： A method and structure for a semiconductor device which includes a substrate comprising trenches, a plurality of devices on the substrate isolated by the trenches, conductive sidewall spacers within the trenches, and an insulator filling the trenches between the conductive sidewall spacers. A first conductive sidewall spacer is electrically connected to a first device of said plurality of devices and a second conductive sidewall spacer is electrically connected to a second device of the plurality of devices. The first device can be biased independently of the second device. A contact extends above a surface of the substrate. A first contact abuts a first device and a first conductive sidewall spacer. An insulator separates the conductive sidewall spacers. A first contact may be equidistant between the first conductor and the second conductor. The conductive sidewall spacers comprise field shields.
摘要翻译：一种用于半导体器件的方法和结构，其包括：衬底，其包括沟槽，在衬底上隔离的衬底上的多个器件，沟槽内的导电侧壁间隔物，以及填充导电侧壁间隔物之间的沟槽的绝缘体。第一导电侧壁间隔件电连接到所述多个器件中的第一器件，并且第二导电侧壁间隔件电连接到多个器件中的第二器件。第一装置可以独立于第二装置而被偏置。接触件在衬底的表面上方延伸。第一接触件邻接第一器件和第一导电侧壁间隔物。绝缘体将导电侧墙隔离开。第一接触件可以在第一导体和第二导体之间等距。导电侧壁间隔件包括场屏蔽。

2. 发明授权

US06380027B2 Dual tox trench dram structures and process using V-groove 失效
标题翻译：双毒tox沟结构和工艺采用V型槽
公开(公告)号：US06380027B2
公开(公告)日：2002-04-30
申请号：US09225127
申请日：1999-01-04
申请人： Toshiharu Furukawa , Jeffrey P. Gambino , Edward W. Kiewra , Jack A. Mandelman , Carl J. Radens , William R. Tonti , Mary E. Weybright
发明人： Toshiharu Furukawa , Jeffrey P. Gambino , Edward W. Kiewra , Jack A. Mandelman , Carl J. Radens , William R. Tonti , Mary E. Weybright
IPC分类号： H01L21242
CPC分类号： H01L27/10876 , H01L27/10823 , H01L27/10829 , H01L27/10894
摘要： A structure and method for simultaneously forming array structures and support structures on a substrate comprises forming the array structures to have a V-groove, forming the support structures to have a planar surface, and simultaneously forming a first oxide in the V-groove and a second oxide in the planar surface, wherein the first oxide is thicker than the second oxide.
摘要翻译：用于在衬底上同时形成阵列结构和支撑结构的结构和方法包括：形成阵列结构以具有V形槽，形成支撑结构以具有平坦表面，同时在V形槽中形成第一氧化物，以及其中所述第一氧化物比所述第二氧化物厚。

3. 发明授权

US06150212A Shallow trench isolation method utilizing combination of spacer and fill 失效
标题翻译：使用间隔物和填充物的组合的浅沟槽隔离方法
公开(公告)号：US06150212A
公开(公告)日：2000-11-21
申请号：US359287
申请日：1999-07-22
申请人： Ramachandra Divakaruni , Jeffrey P. Gambino , Jack A. Mandelman , Carl J. Radens , William R. Tonti
发明人： Ramachandra Divakaruni , Jeffrey P. Gambino , Jack A. Mandelman , Carl J. Radens , William R. Tonti
IPC分类号： H01L21/762 , H01L21/8242
CPC分类号： H01L21/76232 , H01L27/10861 , H01L27/1087
摘要： A method for forming an isolation trench region in a semiconductor substrate includes providing the trench region in the semiconductor substrate, adding spacer material at least to sidewalls of the trench region, and etching the trench region at a bottom surface thereof to extend the trench region below the bottom surface and form a crevice region. The spacer material may be subsequently heated such that the spacer material flows from the sidewalls and into the crevice region.
摘要翻译：一种用于在半导体衬底中形成隔离沟槽区域的方法包括：在半导体衬底中设置沟槽区域，至少在沟槽区域的侧壁上添加衬垫材料，并在其底表面处蚀刻沟槽区域，以将沟槽区域延伸到下面底面并形成缝隙区域。间隔物材料可以随后被加热，使得间隔物材料从侧壁流入缝隙区域。

4. 发明授权

US06258689B1 Low resistance fill for deep trench capacitor 失效
标题翻译：深沟槽电容器的低电阻填充
公开(公告)号：US06258689B1
公开(公告)日：2001-07-10
申请号：US09626328
申请日：2000-07-26
申请人： Gary B. Bronner , Jeffrey P. Gambino , Jack A. Mandelman , Rick L. Mohler , Carl Radens , William R. Tonti
发明人： Gary B. Bronner , Jeffrey P. Gambino , Jack A. Mandelman , Rick L. Mohler , Carl Radens , William R. Tonti
IPC分类号： H01L2120
CPC分类号： H01L27/10861 , H01L29/66181
摘要： Trench capacitors are fabricated utilizing a method which results in a metallic nitride as a portion of a node electrode in a lower region of the trench. The metallic nitride-containing trench electrode exhibits reduced series resistance compared to conventional trench electrodes of similar dimensions, thereby enabling reduced ground rule memory cell layouts and/or reduced cell access time. The trench capacitors of the invention are especially useful as components of DRAM memory cells having various trench configuration and design.
摘要翻译：使用导致在沟槽的下部区域中作为节点电极的一部分的金属氮化物的方法来制造沟槽电容器。与具有类似尺寸的常规沟槽电极相比，含金属氮化物的沟槽电极显示出降低的串联电阻，从而能够减少接地规则存储器单元布局和/或降低的单元访问时间。本发明的沟槽电容器特别可用作具有各种沟槽结构和设计的DRAM存储单元的组件。

5. 发明授权

US06426247B1 Low bitline capacitance structure and method of making same 失效
标题翻译：低位线电容结构及其制作方法
公开(公告)号：US06426247B1
公开(公告)日：2002-07-30
申请号：US09764824
申请日：2001-01-17
申请人： Ramachandra Divakaruni , Jeffrey P. Gambino , Jack A. Mandelman , Rajesh Rengarajan
发明人： Ramachandra Divakaruni , Jeffrey P. Gambino , Jack A. Mandelman , Rajesh Rengarajan
IPC分类号： H01L21338
CPC分类号： H01L27/10888 , H01L23/485 , H01L27/10861 , H01L27/10885 , H01L2924/0002 , H01L2924/00
摘要： A method for forming a memory device having low bitline capacitance, comprising: providing a gate conductor stack structure on a silicon substrate, said gate stack structure having a gate oxide layer, a polysilicon layer, a silicide layer, and a top dielectric nitride layer; oxidizing sidewalls of said gate oxide stack; forming sidewall spacers on the sidewalls of said gate conductor stack, said sidewall spacers comprising a thin layer of nitride having a thickness ranging from about 50 to about 250 angstroms; overlaying the gate structure with a thin nitride liner having a thickness ranging from about 25 to about 150 angstroms; depositing an insulative oxide layer over the gate structure; polishing the insulative oxide layer down to the level of the nitride liner of the gate structure; patterning and etching the insulative oxide layer to expose said nitride liner; forming second sidewall spacers over said first sidewall spacers, said second sidewall spacers comprising an oxide layer having a thickness ranging from about 100 to about 400 angstroms; and, depositing and planarizing a layer of polysilicon covering said gate structure and the sidewall spacers.
摘要翻译：一种用于形成具有低位线电容的存储器件的方法，包括：在硅衬底上提供栅极导体堆叠结构，所述栅堆叠结构具有栅极氧化层，多晶硅层，硅化物层和顶部电介质氮化物层; 氧化所述栅极氧化层的侧壁; 在所述栅极导体堆叠的侧壁上形成侧壁间隔物，所述侧壁间隔物包括厚度范围为约50至约250埃的薄氮化物层; 用具有约25至约150埃的厚度的薄氮化物衬垫覆盖栅极结构; 在栅极结构上沉积绝缘氧化物层; 将绝缘氧化物层抛光到栅极结构的氮化物衬垫的水平面; 图案化和蚀刻绝缘氧化物层以暴露所述氮化物衬垫; 在所述第一侧壁间隔物上形成第二侧壁间隔物，所述第二侧壁间隔物包括厚度范围为约100至约400埃的氧化物层; 并且沉积和平坦化覆盖所述栅极结构和侧壁间隔物的多晶硅层。

6. 发明授权

US06350653B1 Embedded DRAM on silicon-on-insulator substrate 有权
标题翻译：绝缘体上硅衬底上的嵌入式DRAM
公开(公告)号：US06350653B1
公开(公告)日：2002-02-26
申请号：US09689096
申请日：2000-10-12
申请人： James W. Adkisson , Ramachandra Divakaruni , Jeffrey P. Gambino , Jack A. Mandelman
发明人： James W. Adkisson , Ramachandra Divakaruni , Jeffrey P. Gambino , Jack A. Mandelman
IPC分类号： H01L21336
CPC分类号： H01L27/10864 , H01L21/84 , H01L27/1087 , H01L27/1203 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device is presented which is directed to a method of forming embedded DRAM and logic devices, where the DRAM devices are formed in bulk, single crystalline semiconductor regions and logic devices are formed in silicon-on-insulator (“SOI”) regions and where buried, doped glass is used as a mask to form deep trenches for storage in the bulk region. The resulting structure is also disclosed.
摘要翻译：提出了一种半导体器件，其涉及一种形成嵌入式DRAM和逻辑器件的方法，其中DRAM器件以块状形成，单晶半导体区域和逻辑器件形成在绝缘体上硅（“SOI”）区域中，其中掩埋的掺杂玻璃用作掩模以形成用于存储在本体区域中的深沟槽。还公开了所得到的结构。

7. 发明授权

US06590259B2 Semiconductor device of an embedded DRAM on SOI substrate 有权
标题翻译： SOI衬底上嵌入式DRAM的半导体器件
公开(公告)号：US06590259B2
公开(公告)日：2003-07-08
申请号：US10000198
申请日：2001-11-02
申请人： James W. Adkisson , Ramachandra Divakaruni , Jeffrey P. Gambino , Jack A. Mandelman
发明人： James W. Adkisson , Ramachandra Divakaruni , Jeffrey P. Gambino , Jack A. Mandelman
IPC分类号： H01L2701
CPC分类号： H01L27/10864 , H01L21/84 , H01L27/1087 , H01L27/1203 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device is presented which is directed to a method of forming embedded DRAM and logic devices, where the DRAM devices are formed in bulk, single crystalline semiconductor regions and logic devices are formed in silicon-on-insulator (“SOI”) regions and where buried, doped glass is used as a mask to form deep trenches for storage in the bulk region. The resulting structure is also disclosed.
摘要翻译：提出了一种半导体器件，其涉及一种形成嵌入式DRAM和逻辑器件的方法，其中DRAM器件以块状形成，单晶半导体区域和逻辑器件形成在绝缘体上硅（“SOI”）区域中，其中掩埋的掺杂玻璃用作掩模以形成用于存储在本体区域中的深沟槽。还公开了所得到的结构。

8. 发明授权

US06674134B2 Structure and method for dual gate oxidation for CMOS technology 失效
标题翻译：用于CMOS技术的双栅极氧化的结构和方法
公开(公告)号：US06674134B2
公开(公告)日：2004-01-06
申请号：US09173430
申请日：1998-10-15
申请人： Wayne S. Berry , Jeffrey P. Gambino , Jack A. Mandelman , William R. Tonti
发明人： Wayne S. Berry , Jeffrey P. Gambino , Jack A. Mandelman , William R. Tonti
IPC分类号： H01L2976
CPC分类号： H01L21/823481 , H01L21/76224 , H01L21/823462
摘要： The present invention provides an integrated circuit which comprises a substrate having a plurality of device regions formed therein, said plurality of device regions being electrically isolated from each other by shallow trench isolation (STI) regions and said plurality of device regions each having opposing edges abutting its corresponding STI region; selected ones of said devices regions having a preselected first device width such that an oxide layer formed thereon includes substantially thicker perimeter regions, along said opposing edges, compared to a thinner central region that does not abut its corresponding STI region; and selected other ones of the device regions having a preselected device width substantially narrower in width than the first device width such that an oxide layer formed thereon includes perimeter regions, along opposing edges, that abut each other over its central region thereby preventing formation of a corresponding thinner central region.
摘要翻译：本发明提供一种集成电路，其包括其中形成有多个器件区的衬底，所述多个器件区通过浅沟槽隔离（STI）区域彼此电隔离，并且所述多个器件区域各自具有相对的边缘邻接其对应的STI区域; 所选择的所述器件区域具有预先选择的第一器件宽度，使得形成在其上的氧化物层与不相邻其对应的STI区的较薄的中心区域相比，沿着所述相对的边缘包括基本上较厚的周边区域; 以及选定的其它器件区域具有基本上比第一器件宽度窄的宽度的预选器件宽度，使得形成在其上的氧化物层包括沿相对边缘的周边区域，该周边区域在其中心区域上彼此邻接，从而防止形成相应较薄的中心区域。

9. 发明授权

US06436749B1 Method for forming mixed high voltage (HV/LV) transistors for CMOS devices using controlled gate depletion 失效
标题翻译：用于使用受控栅极耗尽的CMOS器件形成混合高压（HV / LV）晶体管的方法
公开(公告)号：US06436749B1
公开(公告)日：2002-08-20
申请号：US09658655
申请日：2000-09-08
申请人： William R. Tonti , Claude L. Bertin , Jeffrey P. Gambino , Russell J. Houghton , Jack A. Mandelman , Wilbur D. Pricer
发明人： William R. Tonti , Claude L. Bertin , Jeffrey P. Gambino , Russell J. Houghton , Jack A. Mandelman , Wilbur D. Pricer
IPC分类号： H01L218238
CPC分类号： H01L27/092 , H01L21/823842
摘要： A method for forming mixed high voltage/low voltage (HV/LV) transistors for CMOS devices is disclosed. In an exemplary embodiment, depletion of the gate conductor is controlled by leaving a fixed region of the gate conductor intrinsic, or lightly doped, thus separating the heavily doped low resistivity portion of the electrode with an intrinsic region by use of a conducting dopant barrier. The barrier is conductive in nature, but acts as a well-controlled diffusion barrier, stopping the “fast” diffusion which normally takes place in polysilicon, and eliminating diffusion between the conductors. Thereby, the device performance may be precisely predicted by carefully controlling the gate conductor thickness.
摘要翻译：公开了一种用于形成用于CMOS器件的混合高压/低压（HV / LV）晶体管的方法。在示例性实施例中，通过将栅极导体的固定区域固有或轻掺杂来控制栅极导体的耗尽，从而通过使用导电掺杂剂屏障将本征区域的重掺杂低电阻率部分与本征区域分离。阻挡层本质上是导电的，但是作为良好控制的扩散屏障，停止通常在多晶硅中发生的“快速”扩散，并消除导体之间的扩散。因此，可以通过仔细地控制栅极导体厚度来精确地预测器件性能。

10. 发明授权

US06538295B1 Salicide device with borderless contact 有权
标题翻译：自杀式装置与无边界接触
公开(公告)号：US06538295B1
公开(公告)日：2003-03-25
申请号：US09645499
申请日：2000-08-25
申请人： Gary B. Bronner , Jeffrey P. Gambino , Louis L. Hsu , Jack A. Mandelman , Carl J. Radens , William R. Tonti
发明人： Gary B. Bronner , Jeffrey P. Gambino , Louis L. Hsu , Jack A. Mandelman , Carl J. Radens , William R. Tonti
IPC分类号： H01L2976
CPC分类号： H01L21/76897 , H01L27/10873 , H01L29/665
摘要： A method and structure for a field effect transistor structure for dynamic random access memory integrated circuit devices has a gate conductor, salicide regions positioned along sides of the gate conductor, a gate cap positioned above the gate conductor and at least one self-aligned contact adjacent the gate conductor.
摘要翻译：用于动态随机存取存储器集成电路器件的场效应晶体管结构的方法和结构具有栅极导体，沿着栅极导体的侧面定位的自对准硅化物区域，位于栅极导体上方的栅极帽和邻近的至少一个自对准接触门导体。

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