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61. 发明授权

US08318015B2 Stormwater filtration systems 有权
标题翻译：雨水过滤系统
公开(公告)号：US08318015B2
公开(公告)日：2012-11-27
申请号：US13352977
申请日：2012-01-18
申请人： Vaikko P. Allen, II , Jeremiah M. Lehman , James H. Lenhart, Jr. , Hong Lin , Daniel P. Cobb , Gregory W Byrne
发明人： Vaikko P. Allen, II , Jeremiah M. Lehman , James H. Lenhart, Jr. , Hong Lin , Daniel P. Cobb , Gregory W Byrne
IPC分类号： C02F3/32
CPC分类号： C02F3/32 , C02F1/004 , C02F3/327 , C02F2103/001 , E03F1/002 , Y02A10/37 , Y02W10/18
摘要： A stormwater filtration system suitable for treatment of stormwater runoff in a developed environment uses a primary treatment bay that includes a filtration bed with live plant matter. A second treatment bay treats water that exceeds the maximum throughput of the primary bay. A reservoir stores treated runoff to water the plants during dry weather. Removable trays on the surface of the primary filtration bed provide plants suitable for ground cover. Additional bays expand the filtration bed throughput and accommodate extended root systems. A flow control may be provided for the primary treatment bay.
摘要翻译：适用于在发达环境中治理雨水径流的雨水过滤系统使用包括带有活植物物质的过滤床的初级处理室。第二处理舱处理超过主舱的最大吞吐量的水。在干燥天气期间，水库存储处理的径流给植物。主滤床表面的可移动托盘提供适合地面覆盖的植物。额外的海湾扩大了过滤床的吞吐量并适应了扩展的根系统。可以为主处理室提供流量控制。

62. 发明申请

US20120116054A1 CONCENTRATED PROTEIN LYOPHILATES, METHODS, AND USES 审中-公开
标题翻译：浓缩蛋白柠檬酸盐，方法和用途
公开(公告)号：US20120116054A1
公开(公告)日：2012-05-10
申请号：US13102733
申请日：2011-05-06
申请人： Sampathkumar Krishnan , Monica Pallitto , Margaret Ricci , Wenjin Cao , Hong Lin , Yong Xie , Samantha Nagle , Shon Lee Crampton
发明人： Sampathkumar Krishnan , Monica Pallitto , Margaret Ricci , Wenjin Cao , Hong Lin , Yong Xie , Samantha Nagle , Shon Lee Crampton
IPC分类号： C07K19/00 , C07K16/18
CPC分类号： A61K38/17 , F26B5/06
摘要： The invention provides, among other things, lyophilized compositions of high surface area that comprise a protein and that reconstitute quickly and efficiently to solution of high protein concentration with minimal formation, if any, of foam, effervescence, bubbles, turbidity, or particulates that might be deleterious. The invention also provides, among other things, methods for making the lyophilized compositions. The invention in additional aspects also provides Raman Imaging Spectrographic methods for real time analyses of polymorphs in a sample using PLS algorithms. By way of particular example, the use of the method for the analysis of mannitol polymorphs is described, and the use of the analysis to determine optimum compositions and lyophilization methods for producing lyophilates of pharmaceutical proteins having a predefined distribution of mannitol polymorphs and having the aforementioned reconstitution properties is also described.
摘要翻译：本发明尤其提供了包含蛋白质的高表面积的冻干组合物，并且可以快速且有效地重构高蛋白质浓度溶液，同时发生泡沫，泡腾，气泡，混浊或微粒的形成有害本发明还提供了用于制备冻干组合物的方法。本发明的其它方面还提供拉曼成像光谱方法，用于使用PLS算法实时分析样品中的多晶型物。作为具体实例，描述了用于分析甘露醇多晶型物的方法的使用，并且使用分析来确定用于制备具有预定分布的甘露醇多晶型物并具有前述物质的药物蛋白质的冷冻干燥剂的最佳组合物和冻干方法还描述了重构性质。

63. 发明授权

US07816261B2 MOSFETS comprising source/drain recesses with slanted sidewall surfaces, and methods for fabricating the same 有权
标题翻译：包括具有倾斜侧壁表面的源极/漏极凹部的MOSFET，及其制造方法
公开(公告)号：US07816261B2
公开(公告)日：2010-10-19
申请号：US11928356
申请日：2007-10-30
申请人： Huilong Zhu , Hong Lin
发明人： Huilong Zhu , Hong Lin
IPC分类号： H01L21/44
CPC分类号： H01L29/66636 , H01L29/045 , H01L29/665 , H01L29/66772 , H01L29/7843 , H01L29/78618 , Y10S257/902
摘要： The present invention relates to improved metal-oxide-semiconductor field effect transistor (MOSFET) devices with stress-inducing structures located at the source and drain (S/D) regions. Specifically, each MOSFET comprises source and drain regions located in a semiconductor substrate. Such source and drain regions comprise recesses with one or more sidewall surfaces that are slanted in relation to an upper surface of the semiconductor substrate. A stress-inducing dielectric layer is located over the slanted sidewall surfaces of the recesses at the source and drain regions. Such MOSFETs can be readily formed by crystallographic etching of the semiconductor substrate to form the recesses with the slanted sidewall surfaces, followed by deposition of a stress-inducing dielectric layer thereover.
摘要翻译：本发明涉及具有位于源极和漏极（S / D）区域处的应力诱导结构的改进的金属氧化物半导体场效应晶体管（MOSFET）器件。具体地，每个MOSFET包括位于半导体衬底中的源区和漏区。这种源极和漏极区域包括具有相对于半导体衬底的上表面倾斜的一个或多个侧壁表面的凹部。应力诱导电介质层位于源极和漏极区域的凹部的倾斜侧壁表面上。这样的MOSFET可以通过半导体衬底的晶体刻蚀容易地形成，以形成具有倾斜侧壁表面的凹部，然后在其上沉积应力诱导介电层。

64. 发明授权

US07560758B2 MOSFETs comprising source/drain recesses with slanted sidewall surfaces, and methods for fabricating the same 有权
标题翻译：包括具有倾斜侧壁表面的源极/漏极凹部的MOSFET及其制造方法
公开(公告)号：US07560758B2
公开(公告)日：2009-07-14
申请号：US11427491
申请日：2006-06-29
申请人： Huilong Zhu , Hong Lin
发明人： Huilong Zhu , Hong Lin
IPC分类号： H01L29/80
CPC分类号： H01L29/66636 , H01L29/045 , H01L29/665 , H01L29/66772 , H01L29/7843 , H01L29/78618 , Y10S257/902
摘要： The present invention relates to improved metal-oxide-semiconductor field effect transistor (MOSFET) devices with stress-inducing structures located at the source and drain (S/D) regions. Specifically, each MOSFET comprises source and drain regions located in a semiconductor substrate. Such source and drain regions comprise recesses with one or more sidewall surfaces that are slanted in relation to an upper surface of the semiconductor substrate. A stress-inducing dielectric layer is located over the slanted sidewall surfaces of the recesses at the source and drain regions. Such MOSFETs can be readily formed by crystallographic etching of the semiconductor substrate to form the recesses with the slanted sidewall surfaces, followed by deposition of a stress-inducing dielectric layer thereover.
摘要翻译：本发明涉及具有位于源极和漏极（S / D）区域处的应力诱导结构的改进的金属氧化物半导体场效应晶体管（MOSFET）器件。具体地，每个MOSFET包括位于半导体衬底中的源区和漏区。这种源极和漏极区域包括具有相对于半导体衬底的上表面倾斜的一个或多个侧壁表面的凹部。应力诱导电介质层位于源极和漏极区域的凹部的倾斜侧壁表面上。这样的MOSFET可以通过半导体衬底的晶体刻蚀容易地形成，以形成具有倾斜侧壁表面的凹部，然后在其上沉积应力诱导介电层。

65. 发明申请

US20090137557A1 Calcilytic Compounds 审中-公开
标题翻译：钙化合物
公开(公告)号：US20090137557A1
公开(公告)日：2009-05-28
申请号：US12094665
申请日：2006-11-21
申请人： Thomas Wen Fu Ku , Hong Lin , Juan I. Luengo , Robert W. Marquis Jr. , Joshi M. Ramanjulu , Robert Trout , Dennis S. Yamashita
发明人： Thomas Wen Fu Ku , Hong Lin , Juan I. Luengo , Robert W. Marquis Jr. , Joshi M. Ramanjulu , Robert Trout , Dennis S. Yamashita
IPC分类号： A61K31/513 , C07D239/22 , C07D413/04 , A61K31/55 , A61P19/10 , A61K31/5377 , C07D487/04
CPC分类号： C07D239/36 , C07D239/40 , C07D239/47 , C07D239/72 , C07D239/91 , C07D401/04 , C07D403/04 , C07D405/04 , C07D409/04 , C07D409/06 , C07D409/14 , C07D413/14 , C07D417/04 , C07D417/14 , C07D487/04 , C07D491/044
摘要： Novel calcilytic compounds, pharmaceutical compositions, methods of synthesis and methods of using them are provided.
摘要翻译：提供了新的钙化合物，药物组合物，合成方法和使用它们的方法。

66. 发明授权

US07365015B2 Damascene replacement metal gate process with controlled gate profile and length using Si1-xGex as sacrificial material 有权
标题翻译：使用Si1-xGex作为牺牲材料的具有受控栅极轮廓和长度的镶嵌金属栅极工艺
公开(公告)号：US07365015B2
公开(公告)日：2008-04-29
申请号：US10889901
申请日：2004-07-13
申请人： Hong Lin , Wai Lo , Sey-Shing Sun , Richard Carter
发明人： Hong Lin , Wai Lo , Sey-Shing Sun , Richard Carter
IPC分类号： H01L29/76
CPC分类号： H01L29/66545 , H01L21/28079 , H01L21/28123 , H01L21/32134 , H01L21/32137
摘要： A method of forming a metal gate in a wafer. PolySi1-xGex and polysilicon are used to form a tapered groove. Gate oxide, PolySi1-xGex, and polysilicon is deposited on a wafer. A resist pattern is formed. A portion of the polysilicon, PolySi1-xGex, and gate oxide is removed to provide a tapered profile. The resist is removed; a dielectric liner is deposited, and then at least a portion of the dielectric liner is removed, thereby exposing the polysilicon and leaving the dielectric liner in contact with the polysilicon, PolyS1-xGex, and gate oxide. A dielectric is deposited, and a portion is removed thereby exposing the polysilicon. The polysilicon, PolySi1-xGex, and gate oxide is removed from inside the dielectric liner, thereby leaving a tapered gate groove. Metal is then deposited in the groove.
摘要翻译：一种在晶片中形成金属栅极的方法。多晶硅1-x x Ge x S和多晶硅用于形成锥形槽。栅极氧化物，多晶硅1-x x Ge x，并且多晶硅沉积在晶片上。形成抗蚀剂图案。去除多晶硅的一部分，多晶硅1-x N x N x N和栅极氧化物以提供锥形轮廓。去除抗蚀剂; 沉积电介质衬垫，然后去除电介质衬垫的至少一部分，从而暴露多晶硅并使电介质衬垫与多晶硅接触，PolyS 1-x Ge x 和/或栅极氧化物。沉积电介质，一部分被去除，从而暴露多晶硅。从电介质衬垫的内部去除多晶硅，多晶硅1 x x Ge x x和栅极氧化物，从而留下锥形栅极沟槽。然后将金属沉积在凹槽中。

67. 发明授权

US07341978B2 Superconductor wires for back end interconnects 有权
标题翻译：用于后端互连的超导线
公开(公告)号：US07341978B2
公开(公告)日：2008-03-11
申请号：US11072158
申请日：2005-03-04
申请人： Shiqun Gu , Wai Lo , Hong Lin
发明人： Shiqun Gu , Wai Lo , Hong Lin
IPC分类号： H01L33/00
CPC分类号： H01L21/76838 , H01L21/76834 , H01L23/53285 , H01L2924/0002 , H01L2924/00
摘要： An improvement to an integrated circuit, of electrically conductive interconnects formed of a superconducting material. In this manner, the electrically conductive interconnects can be made very small, and yet still have adequate conductively. In various embodiments, all of the electrically conductive interconnects are formed of the superconducting material. In some embodiments, the electrically conductive interconnects are formed of a variety of different superconducting materials. In one embodiment, only the backend electrically conductive interconnects are formed of the superconducting material. In some embodiments no vias are formed of the superconducting material. The interconductor dielectric layers are preferably formed of silicon oxide, and sometimes all of the interconductor dielectric layers are formed of silicon oxide. The superconducting material is in some embodiments at least one of an organic compound such as a potassium doped buckminsterfullerene, a cesium doped buckminsterfullerene, and other carbon containing compounds, a metallic material such as an inter-metallic material like Nb—Ti alloys and other substances formed by alloying metals, and an inorganic compound such as YBa2Cu3O7-x, (Pb,Bi)2Sr2Ca2Cu3O10-x and its derivatives, HgBaCaCuO and its derivatives, and TI—Ba—Ca—Cu—O and its derivatives.
摘要翻译：对由超导材料形成的导电互连的集成电路的改进。以这种方式，可以使导电互连非常小，但仍然具有足够的导电性。在各种实施例中，所有导电互连由超导材料形成。在一些实施例中，导电互连由各种不同的超导材料形成。在一个实施例中，只有后端导电互连由超导材料形成。在一些实施例中，没有由超导材料形成通孔。互导体电介质层优选由氧化硅形成，并且有时所有的互导电介质层均由氧化硅形成。在一些实施方案中，超导材料是有机化合物，例如掺杂钾的巴克敏斯特富勒烯，掺杂铯的德克敏斯特富勒烯和其它含碳化合物中的至少一种，金属材料如诸如Nb-Ti合金的金属间材料和其它物质由金属合金化而形成的无机化合物，例如YBa 2 N 3 O 7-x X，（Pb，Bi）2 Sr 2 O 2和其衍生物HgBaCaCuO及其衍生物和TI-Ba-Ca-Cu-O及其衍生物。

68. 发明授权

US07189628B1 Fabrication of trenches with multiple depths on the same substrate 有权
标题翻译：在同一基板上制作具有多个深度的沟槽
公开(公告)号：US07189628B1
公开(公告)日：2007-03-13
申请号：US10931605
申请日：2004-08-31
申请人： Mohammad R. Mirbedini , Venkatesh P. Gopinath , Hong Lin , Verne Hornback , Dodd Defibaugh , Ynhi Le
发明人： Mohammad R. Mirbedini , Venkatesh P. Gopinath , Hong Lin , Verne Hornback , Dodd Defibaugh , Ynhi Le
IPC分类号： H01L21/461
CPC分类号： H01L21/76232 , H01L21/76229 , H01L21/76283
摘要： Dual trench depths are achieved on the same wafer by forming an initial trench having a depth corresponding to the difference in final depths of the shallow and deep trenches. A second mask is used to open areas for the deep trenches over the preliminary trenches and for the shallow trenches at additional locations. Etching of the shallow and deep trenches then proceeds simultaneously.
摘要翻译：通过形成具有对应于浅沟槽和深沟槽的最终深度的差的深度的初始沟槽，在同一晶片上实现双沟槽深度。第二个掩模用于打开初步沟槽上的深沟槽的区域，并在另外的位置打开浅沟槽。浅沟和深沟的蚀刻然后同时进行。

69. 发明授权

US07081406B2 Interconnect dielectric tuning 失效
标题翻译：互连电介质调谐
公开(公告)号：US07081406B2
公开(公告)日：2006-07-25
申请号：US10915719
申请日：2004-08-10
申请人： Wai Lo , Hong Lin , Shiqun Gu , Wilbur G. Catabay , Zhihai Wang , Wei-Jen Hsia
发明人： Wai Lo , Hong Lin , Shiqun Gu , Wilbur G. Catabay , Zhihai Wang , Wei-Jen Hsia
IPC分类号： H01L21/4763
CPC分类号： H01L21/7682 , H01L21/76838 , H01L23/5222 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An improvement to a method of forming an integrated circuit. An etch stop layer is formed to overlie the front end processing layers of the integrated circuit. Support structures are formed that are disposed so as to support electrically conductive interconnects on various levels of the integrated circuit. Substantially all of the non electrically conductive layers above the etch stop layer that were formed during the fabrication of the interconnects are removed.
摘要翻译：对形成集成电路的方法的改进。形成蚀刻停止层以覆盖集成电路的前端处理层。形成支撑结构，其被布置为支撑集成电路的各个级别上的导电互连。基本上去除了在制造互连期间形成的蚀刻停止层上方的所有非导电层。

70. 发明授权

US06806038B2 Plasma passivation 失效
标题翻译：等离子体钝化
公开(公告)号：US06806038B2
公开(公告)日：2004-10-19
申请号：US10190954
申请日：2002-07-08
申请人： Shiqun Gu , Hong Lin , Ryan Tadashi Fujimoto
发明人： Shiqun Gu , Hong Lin , Ryan Tadashi Fujimoto
IPC分类号： G03F700
CPC分类号： H01L21/02071
摘要： A method for forming a conductive trace on a substrate. The conductive trace is patterned with a photoresist mask and etched, thereby forming a polymer layer on a top surface and sidewalls of the photoresist mask and on sidewalls of the conductive trace. The polymer layer contains entrained chlorine gas. The substrate is heated on a chuck in a reaction chamber. A remote plasma is generated from ammonia gas and oxygen gas. The substrate is contacted with the ammonia and oxygen plasma, thereby withdrawing a substantial portion of the entrained chlorine gas from the polymer layer. A radio frequency potential is applied to the chuck on which the substrate resides, thereby creating a reactive ion etchant from the ammonia and oxygen plasma in the reaction chamber and removing the polymer layer from the top surface of the photoresist mask. The photoresist mask is thus exposed, and then removed in an ashing process.
摘要翻译：一种在衬底上形成导电迹线的方法。导电迹线用光致抗蚀剂掩模图案化并被蚀刻，从而在光致抗蚀剂掩模的顶表面和侧壁以及导电迹线的侧壁上形成聚合物层。聚合物层含有夹带的氯气。基板在反应室中的卡盘上加热。从氨气和氧气产生远程等离子体。基板与氨和氧等离子体接触，从而从聚合物层中取出大部分夹带的氯气。将射频电势施加到其上存在基板的卡盘，从而在反应室中从氨和氧等离子体产生反应离子蚀刻剂，并从光致抗蚀剂掩模的顶表面除去聚合物层。因此曝光光致抗蚀剂掩模，然后在灰化过程中去除。

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