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1. 发明授权

US07977712B2 Asymmetric source and drain field effect structure 有权
标题翻译：不对称源极和漏极场效应结构
公开(公告)号：US07977712B2
公开(公告)日：2011-07-12
申请号：US12059059
申请日：2008-03-31
申请人： Huilong Zhu , Hong Lin , Katherine L. Saenger , Kai Xiu , Haizhou Yin
发明人： Huilong Zhu , Hong Lin , Katherine L. Saenger , Kai Xiu , Haizhou Yin
IPC分类号： H01L29/04
CPC分类号： H01L21/823807 , H01L21/28132 , H01L21/823814 , H01L21/823864 , H01L29/045 , H01L29/6659 , H01L29/66659 , H01L29/7835
摘要： A semiconductor structure, such as a CMOS semiconductor structure, includes a field effect device that includes a plurality of source and drain regions that are asymmetric. Such a source region and drain region asymmetry is induced by fabricating the semiconductor structure using a semiconductor substrate that includes a horizontal plateau region contiguous with and adjoining a sloped incline region. Within the context of a CMOS semiconductor structure, such a semiconductor substrate allows for fabrication of a pFET and an nFET upon different crystallographic orientation semiconductor regions, while one of the pFET and the nFET (i.e., typically the pFET) has asymmetric source and drain regions.
摘要翻译：诸如CMOS半导体结构的半导体结构包括具有不对称的多个源区和漏区的场效应器件。通过使用包括与倾斜斜面区域相邻并相邻的水平平台区域的半导体衬底制造半导体结构来诱导这种源区和漏区不对称。在CMOS半导体结构的上下文中，这种半导体衬底允许在不同的晶体取向半导体区域上制造pFET和nFET，而pFET和nFET（即，通常为pFET）中的一个具有不对称的源极和漏极区域。

2. 发明申请

US20090242942A1 ASYMMETRIC SOURCE AND DRAIN FIELD EFFECT STRUCTURE AND METHOD 有权
标题翻译：不对称源和排水场效应结构与方法
公开(公告)号：US20090242942A1
公开(公告)日：2009-10-01
申请号：US12059059
申请日：2008-03-31
申请人： Huilong Zhu , Hong Lin , Katherine L. Saenger , Kai Xiu , Haizhou Yin
发明人： Huilong Zhu , Hong Lin , Katherine L. Saenger , Kai Xiu , Haizhou Yin
IPC分类号： H01L29/04 , H01L21/8238
CPC分类号： H01L21/823807 , H01L21/28132 , H01L21/823814 , H01L21/823864 , H01L29/045 , H01L29/6659 , H01L29/66659 , H01L29/7835
摘要： A semiconductor structure, such as a CMOS semiconductor structure, includes a field effect device that includes a plurality of source and drain regions that are asymmetric. Such a source region and drain region asymmetry is induced by fabricating the semiconductor structure using a semiconductor substrate that includes a horizontal plateau region contiguous with and adjoining a sloped incline region. Within the context of a CMOS semiconductor structure, such a semiconductor substrate allows for fabrication of a pFET and an nFET upon different crystallographic orientation semiconductor regions, while one of the pFET and the nFET (i.e., typically the pFET) has asymmetric source and drain regions.
摘要翻译：诸如CMOS半导体结构的半导体结构包括具有不对称的多个源区和漏区的场效应器件。通过使用包括与倾斜斜面区域相邻并相邻的水平平台区域的半导体衬底制造半导体结构来诱导这种源区和漏区不对称。在CMOS半导体结构的上下文中，这种半导体衬底允许在不同的晶体取向半导体区域上制造pFET和nFET，而pFET和nFET（即，通常为pFET）中的一个具有不对称的源极和漏极区域。

3. 发明申请

US20080001260A1 MOSFETS COMPRISING SOURCE/DRAIN RECESSES WITH SLANTED SIDEWALL SURFACES, AND METHODS FOR FABRICATING THE SAME 有权
标题翻译：包含带有凸面表面的源/漏区的MOSFETs及其制造方法
公开(公告)号：US20080001260A1
公开(公告)日：2008-01-03
申请号：US11427491
申请日：2006-06-29
申请人： Huilong Zhu , Hong Lin
发明人： Huilong Zhu , Hong Lin
IPC分类号： H01L29/06
CPC分类号： H01L29/66636 , H01L29/045 , H01L29/665 , H01L29/66772 , H01L29/7843 , H01L29/78618 , Y10S257/902
摘要： The present invention relates to improved metal-oxide-semiconductor field effect transistor (MOSFET) devices with stress-inducing structures located at the source and drain (S/D) regions. Specifically, each MOSFET comprises source and drain regions located in a semiconductor substrate. Such source and drain regions comprise recesses with one or more sidewall surfaces that are slanted in relation to an upper surface of the semiconductor substrate. A stress-inducing dielectric layer is located over the slanted sidewall surfaces of the recesses at the source and drain regions. Such MOSFETs can be readily formed by crystallographic etching of the semiconductor substrate to form the recesses with the slanted sidewall surfaces, followed by deposition of a stress-inducing dielectric layer thereover.
摘要翻译：本发明涉及具有位于源极和漏极（S / D）区域处的应力诱导结构的改进的金属氧化物半导体场效应晶体管（MOSFET）器件。具体地，每个MOSFET包括位于半导体衬底中的源区和漏区。这种源极和漏极区域包括具有相对于半导体衬底的上表面倾斜的一个或多个侧壁表面的凹部。应力诱导电介质层位于源极和漏极区域的凹部的倾斜侧壁表面上。这样的MOSFET可以通过半导体衬底的晶体刻蚀容易地形成，以形成具有倾斜侧壁表面的凹部，然后在其上沉积应力诱导介电层。

4. 发明申请

US20080057710A1 MOSFETS COMPRISING SOURCE/DRAIN RECESSES WITH SLANTED SIDEWALL SURFACES, AND METHODS FOR FABRICATING THE SAME 有权
公开(公告)号：US20080057710A1
公开(公告)日：2008-03-06
申请号：US11928356
申请日：2007-10-30
申请人： Huilong Zhu , Hong Lin
发明人： Huilong Zhu , Hong Lin
IPC分类号： H01L21/44
CPC分类号： H01L29/66636 , H01L29/045 , H01L29/665 , H01L29/66772 , H01L29/7843 , H01L29/78618 , Y10S257/902
摘要： The present invention relates to improved metal-oxide-semiconductor field effect transistor (MOSFET) devices with stress-inducing structures located at the source and drain (S/D) regions. Specifically, each MOSFET comprises source and drain regions located in a semiconductor substrate. Such source and drain regions comprise recesses with one or more sidewall surfaces that are slanted in relation to an upper surface of the semiconductor substrate. A stress-inducing dielectric layer is located over the slanted sidewall surfaces of the recesses at the source and drain regions. Such MOSFETs can be readily formed by crystallographic etching of the semiconductor substrate to form the recesses with the slanted sidewall surfaces, followed by deposition of a stress-inducing dielectric layer thereover.

5. 发明申请

US20070221959A1 STRUCTURE AND METHOD FOR FABRICATING RECESSED CHANNEL MOSFET WITH FANNED OUT TAPERED SURFACE RAISED SOURCE/DRAIN 审中-公开
标题翻译：用于制造带有锥形表面加工源/漏斗的残留通道MOSFET的结构和方法
公开(公告)号：US20070221959A1
公开(公告)日：2007-09-27
申请号：US11308410
申请日：2006-03-22
申请人： Huilong Zhu , Hong Lin
发明人： Huilong Zhu , Hong Lin
IPC分类号： H01L29/76
CPC分类号： H01L29/66621 , H01L29/66553
摘要： A raised source/drain field effect transistor has a surface of a raised source/drain that tapers downward in a direction of a gate electrode that is also included within the field effect transistor. The downward tapered surface is preferably an end surface. Due to the downward taper, the field effect transistor has a reduced gate to raised source/drain region capacitance. The downward taper also facilitates forming a halo region within the field effect transistor. Due to the raised source/drain, a silicide layer may be included within the raised source/drain region absent silicide penetration through a thin junction within an intrinsic source/drain region also included within the raised source/drain region.
摘要翻译：升高的源极/漏极场效应晶体管具有在也包括在场效应晶体管内的栅电极的方向上向下逐渐变细的升高的源极/漏极的表面。向下的锥形表面优选为端面。由于向下的锥度，场效应晶体管具有减小的栅极以提高源/漏区电容。向下的锥形还有助于在场效应晶体管内形成晕圈。由于升高的源极/漏极，在升高的源极/漏极区域内可以包括硅化物层，而硅化物穿透也包括在升高的源极/漏极区域内的本征源极/漏极区域内的薄结。

6. 发明授权

US07816261B2 MOSFETS comprising source/drain recesses with slanted sidewall surfaces, and methods for fabricating the same 有权
标题翻译：包括具有倾斜侧壁表面的源极/漏极凹部的MOSFET，及其制造方法
公开(公告)号：US07816261B2
公开(公告)日：2010-10-19
申请号：US11928356
申请日：2007-10-30
申请人： Huilong Zhu , Hong Lin
发明人： Huilong Zhu , Hong Lin
IPC分类号： H01L21/44
CPC分类号： H01L29/66636 , H01L29/045 , H01L29/665 , H01L29/66772 , H01L29/7843 , H01L29/78618 , Y10S257/902
摘要： The present invention relates to improved metal-oxide-semiconductor field effect transistor (MOSFET) devices with stress-inducing structures located at the source and drain (S/D) regions. Specifically, each MOSFET comprises source and drain regions located in a semiconductor substrate. Such source and drain regions comprise recesses with one or more sidewall surfaces that are slanted in relation to an upper surface of the semiconductor substrate. A stress-inducing dielectric layer is located over the slanted sidewall surfaces of the recesses at the source and drain regions. Such MOSFETs can be readily formed by crystallographic etching of the semiconductor substrate to form the recesses with the slanted sidewall surfaces, followed by deposition of a stress-inducing dielectric layer thereover.
摘要翻译：本发明涉及具有位于源极和漏极（S / D）区域处的应力诱导结构的改进的金属氧化物半导体场效应晶体管（MOSFET）器件。具体地，每个MOSFET包括位于半导体衬底中的源区和漏区。这种源极和漏极区域包括具有相对于半导体衬底的上表面倾斜的一个或多个侧壁表面的凹部。应力诱导电介质层位于源极和漏极区域的凹部的倾斜侧壁表面上。这样的MOSFET可以通过半导体衬底的晶体刻蚀容易地形成，以形成具有倾斜侧壁表面的凹部，然后在其上沉积应力诱导介电层。

7. 发明授权

US07560758B2 MOSFETs comprising source/drain recesses with slanted sidewall surfaces, and methods for fabricating the same 有权
标题翻译：包括具有倾斜侧壁表面的源极/漏极凹部的MOSFET及其制造方法
公开(公告)号：US07560758B2
公开(公告)日：2009-07-14
申请号：US11427491
申请日：2006-06-29
申请人： Huilong Zhu , Hong Lin
发明人： Huilong Zhu , Hong Lin
IPC分类号： H01L29/80
CPC分类号： H01L29/66636 , H01L29/045 , H01L29/665 , H01L29/66772 , H01L29/7843 , H01L29/78618 , Y10S257/902
摘要： The present invention relates to improved metal-oxide-semiconductor field effect transistor (MOSFET) devices with stress-inducing structures located at the source and drain (S/D) regions. Specifically, each MOSFET comprises source and drain regions located in a semiconductor substrate. Such source and drain regions comprise recesses with one or more sidewall surfaces that are slanted in relation to an upper surface of the semiconductor substrate. A stress-inducing dielectric layer is located over the slanted sidewall surfaces of the recesses at the source and drain regions. Such MOSFETs can be readily formed by crystallographic etching of the semiconductor substrate to form the recesses with the slanted sidewall surfaces, followed by deposition of a stress-inducing dielectric layer thereover.
摘要翻译：本发明涉及具有位于源极和漏极（S / D）区域处的应力诱导结构的改进的金属氧化物半导体场效应晶体管（MOSFET）器件。具体地，每个MOSFET包括位于半导体衬底中的源区和漏区。这种源极和漏极区域包括具有相对于半导体衬底的上表面倾斜的一个或多个侧壁表面的凹部。应力诱导电介质层位于源极和漏极区域的凹部的倾斜侧壁表面上。这样的MOSFET可以通过半导体衬底的晶体刻蚀容易地形成，以形成具有倾斜侧壁表面的凹部，然后在其上沉积应力诱导介电层。

8. 发明授权

US10068990B2 Method of manufacturing MOS transistor with stack of cascaded nanowires 有权
公开(公告)号：US10068990B2
公开(公告)日：2018-09-04
申请号：US14387830
申请日：2013-08-06
申请人： Huaxiang Yin , Xiaolong Ma , Weijia Xu , Qiuxia Xu , Huilong Zhu
发明人： Huaxiang Yin , Xiaolong Ma , Weijia Xu , Qiuxia Xu , Huilong Zhu
IPC分类号： H01L29/78 , H01L29/06 , H01L29/66 , H01L29/786 , H01L29/423
摘要： A MOS transistor with stacked nanowires and a method of manufacturing the same. The transistor may include a stack of cascaded nanowires extending in a first direction on a substrate; a gate stack extending in a second direction across the nanowire stack; source and drain regions disposed on opposite sides of the gate stack in the second direction; and a channel region constituted of the nanowire stack between the source and drain regions. The cascaded nanowires can be formed by repeated operations of etching back, and lateral etching and then filling of grooves, thereby increasing an effective width of the channel, increasing a total area of an effective conductive section, and thus improving a drive current.

9. 发明授权

US09576802B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US09576802B2
公开(公告)日：2017-02-21
申请号：US14412173
申请日：2012-07-19
申请人： Haizhou Yin , Huilong Zhu , Keke Zhang
发明人： Haizhou Yin , Huilong Zhu , Keke Zhang
IPC分类号： H01L21/331 , H01L21/28 , H01L29/66 , H01L21/3105 , H01L29/78 , H01L29/423 , H01L29/417
CPC分类号： H01L21/28114 , H01L21/28088 , H01L21/31051 , H01L29/41783 , H01L29/42376 , H01L29/4966 , H01L29/6653 , H01L29/66545 , H01L29/6659 , H01L29/66628 , H01L29/78 , H01L29/7834
摘要： A method for manufacturing a semiconductor device is disclosed. The method comprises: forming a T-shape dummy gate structure on the substrate; removing the T-shape dummy gate structure and retaining a T-shape gate trench; forming a T-shape metal gate structure by filling a metal layer in the T-shape gate trench. According to the semiconductor device manufacturing method disclosed in the present application, the overhang phenomenon and the formation of voids are avoided in the subsequent metal gate filling process by forming a T-shape dummy gate and a T-shape gate trench, and the device performance is improved.
摘要翻译：公开了一种制造半导体器件的方法。该方法包括：在衬底上形成T形虚拟栅极结构; 去除T形虚拟栅极结构并保持T形栅极沟槽; 通过在T形栅极沟槽中填充金属层来形成T形金属栅极结构。根据本申请中公开的半导体器件制造方法，通过形成T形虚拟栅极和T形栅极沟槽，在随后的金属栅极填充处理中避免了突出现象和空隙的形成，并且器件性能改进了

10. 发明授权

US09356025B2 Enhancing MOSFET performance with corner stresses of STI 有权
标题翻译：通过STI拐角应力增强MOSFET性能
公开(公告)号：US09356025B2
公开(公告)日：2016-05-31
申请号：US14348579
申请日：2012-03-29
申请人： Huilong Zhu , Zhijiong Luo , Haizhou Yin
发明人： Huilong Zhu , Zhijiong Luo , Haizhou Yin
IPC分类号： H01L27/092 , H01L29/78 , H01L21/8238 , H01L21/762 , H01L29/66
CPC分类号： H01L27/092 , H01L21/76224 , H01L21/823807 , H01L21/823878 , H01L29/66575 , H01L29/7846
摘要： The present invention relates to enhancing MOSFET performance with the corner stresses of STI. A method of manufacturing a MOS device comprises the steps of: providing a semiconductor substrate; forming trenches on the semiconductor substrate and at least a pMOS region and at least an nMOS region surrounded by the trenches; filling the trenches with a dielectric material having a stress; removing at least the dielectric material having a stress in the trenches which is adjacent to a position where a channel is to be formed on each of the pMOS and nMOS regions so as to form exposed regions; filling the exposed regions with a insulating material; and forming pMOS and nMOS devices on the pMOS region and the nMOS region, respectively, wherein each of the pMOS and nMOS devices comprises a channel, a gate formed above the channel, and a source and a drain formed at both sides of the channel; wherein in a channel length direction, the boundary of each exposed region is substantially aligned with the boundary of the position of the channel, or the boundary of each exposed region extends along the channel length direction to be aligned with the boundary of corresponding pMOS or nMOS region.
摘要翻译：本发明涉及利用STI的拐角应力来增强MOSFET的性能。一种制造MOS器件的方法包括以下步骤：提供半导体衬底; 在所述半导体衬底和至少一个pMOS区域和由所述沟槽包围的至少nMOS区域中形成沟槽; 用具有应力的介电材料填充沟槽; 至少去除在沟道中具有应力的介电材料，所述沟槽邻近要在pMOS和nMOS区域中的每一个上形成沟道的位置，以形成暴露区域; 用绝缘材料填充暴露的区域; 以及分别在pMOS区域和nMOS区域上形成pMOS和nMOS器件，其中pMOS和nMOS器件中的每一个包括沟道，形成在沟道上方的栅极以及形成在沟道两侧的源极和漏极; 其中在通道长度方向上，每个曝光区域的边界基本上与通道位置的边界对齐，或者每个曝光区域的边界沿着沟道长度方向延伸以与对应的pMOS或nMOS的边界对准地区。

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