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1. 发明申请

US20080150090A1 DAMASCENE REPLACEMENT METAL GATE PROCESS WITH CONTROLLED GATE PROFILE AND LENGTH USING Si1-xGex AS SACRIFICIAL MATERIAL 审中-公开
标题翻译：使用Si1-xGex作为材料的具有控制门型材和长度的金属浇注过程
公开(公告)号：US20080150090A1
公开(公告)日：2008-06-26
申请号：US12021728
申请日：2008-01-29
申请人： Hong Lin , Wai Lo , Sey-Shing Sun , Richard Carter
发明人： Hong Lin , Wai Lo , Sey-Shing Sun , Richard Carter
IPC分类号： H01L29/40
CPC分类号： H01L29/66545 , H01L21/28079 , H01L21/28123 , H01L21/32134 , H01L21/32137
摘要： A method of forming a metal gate in a wafer. PolySi1-xGex and polysilicon are used to form a tapered groove. Gate oxide, PolySi1-xGex, and polysilicon is deposited on a wafer. A resist pattern is formed. A portion of the polysilicon, PolySi1-xGex, and gate oxide is removed to provide a tapered profile. The resist is removed; a dielectric liner is deposited, and then at least a portion of the dielectric liner is removed, thereby exposing the polysilicon and leaving the dielectric liner in contact with the polysilicon, PolySi1-xGex, and gate oxide. A dielectric is deposited, and a portion is removed thereby exposing the polysilicon. The polysilicon, PolySi1-xGex, and gate oxide is removed from inside the dielectric liner, thereby leaving a tapered gate groove. Metal is then deposited in the groove.
摘要翻译：一种在晶片中形成金属栅极的方法。多晶硅1-x x Ge x S和多晶硅用于形成锥形槽。栅极氧化物，多晶硅1-x x Ge x，并且多晶硅沉积在晶片上。形成抗蚀剂图案。去除多晶硅的一部分，多晶硅1-x N x N x N和栅极氧化物以提供锥形轮廓。去除抗蚀剂; 沉积电介质衬垫，然后去除电介质衬垫的至少一部分，从而暴露多晶硅并使电介质衬垫与多晶硅接触，多晶硅1-x Ge x 和/或栅极氧化物。沉积电介质，一部分被去除，从而暴露多晶硅。从电介质衬垫的内部去除多晶硅，多晶硅1 x x Ge x x和栅极氧化物，从而留下锥形栅极沟槽。然后将金属沉积在凹槽中。

2. 发明申请

US20060011994A1 Damascene replacement metal gate process with controlled gate profile and length using Si1-xGex as sacrificial material 有权
标题翻译：使用Si1-xGex作为牺牲材料的具有受控栅极轮廓和长度的镶嵌金属栅极工艺
公开(公告)号：US20060011994A1
公开(公告)日：2006-01-19
申请号：US10889901
申请日：2004-07-13
申请人： Hong Lin , Wai Lo , Sey-Shing Sun , Richard Carter
发明人： Hong Lin , Wai Lo , Sey-Shing Sun , Richard Carter
IPC分类号： H01L29/76
CPC分类号： H01L29/66545 , H01L21/28079 , H01L21/28123 , H01L21/32134 , H01L21/32137
摘要： A method of forming a metal gate in a wafer. PolySi1-xGex and polysilicon are used to form a tapered groove. Gate oxide, PolySi1-xGex, and polysilicon is deposited on a wafer. A resist pattern is formed. A portion of the polysilicon, PolySi1-xGex, and gate oxide is removed to provide a tapered profile. The resist is removed; a dielectric liner is deposited, and then at least a portion of the dielectric liner is removed, thereby exposing the polysilicon and leaving the dielectric liner in contact with the polysilicon, PolyS1-xGex, and gate oxide. A dielectric is deposited, and a portion is removed thereby exposing the polysilicon. The polysilicon, PolySi1-xGex, and gate oxide is removed from inside the dielectric liner, thereby leaving a tapered gate groove. Metal is then deposited in the groove.
摘要翻译：一种在晶片中形成金属栅极的方法。多晶硅1-x x Ge x S和多晶硅用于形成锥形槽。栅极氧化物，多晶硅1-x x Ge x，并且多晶硅沉积在晶片上。形成抗蚀剂图案。去除多晶硅的一部分，多晶硅1-x N x N x N和栅极氧化物以提供锥形轮廓。去除抗蚀剂; 沉积电介质衬垫，然后去除电介质衬垫的至少一部分，从而暴露多晶硅并使电介质衬垫与多晶硅接触，PolyS 1-x Ge x 和/或栅极氧化物。沉积电介质，一部分被去除，从而暴露多晶硅。从电介质衬垫的内部去除多晶硅，多晶硅1 x x Ge x x和栅极氧化物，从而留下锥形栅极沟槽。然后将金属沉积在凹槽中。

3. 发明申请

US20060035425A1 Application of gate edge liner to maintain gate length CD in a replacement gate transistor flow 有权
公开(公告)号：US20060035425A1
公开(公告)日：2006-02-16
申请号：US10916322
申请日：2004-08-11
申请人： Richard Carter , Wai Lo , Sey-Shing Sun , Hong Lin , Verne Hornback
发明人： Richard Carter , Wai Lo , Sey-Shing Sun , Hong Lin , Verne Hornback
IPC分类号： H01L21/8238
CPC分类号： H01L29/6656 , H01L21/823828 , H01L29/66545 , H01L29/6659 , H01L29/7833
摘要： A method to maintain a well-defined gate stack profile, deposit or grow a uniform gate dielectric, and maintain gate length CD control by means of an inert insulating liner deposited after dummy gate etch and before the spacer process. The liner material is selective to wet chemicals used to remove the dummy gate oxide thereby preventing undercut in the spacer region. The method is aimed at making the metal gate electrode technology a feasible technology with maximum compatibility with the existing fabrication environment for multiple generations of CMOS transistors, including those belonging to the 65 nm, 45 nm and 25 nm technology nodes, that are being used in analog, digital or mixed signal integrated circuit for various applications such as communication, entertainment, education and security products.

4. 发明授权

US07365015B2 Damascene replacement metal gate process with controlled gate profile and length using Si1-xGex as sacrificial material 有权
标题翻译：使用Si1-xGex作为牺牲材料的具有受控栅极轮廓和长度的镶嵌金属栅极工艺
公开(公告)号：US07365015B2
公开(公告)日：2008-04-29
申请号：US10889901
申请日：2004-07-13
申请人： Hong Lin , Wai Lo , Sey-Shing Sun , Richard Carter
发明人： Hong Lin , Wai Lo , Sey-Shing Sun , Richard Carter
IPC分类号： H01L29/76
CPC分类号： H01L29/66545 , H01L21/28079 , H01L21/28123 , H01L21/32134 , H01L21/32137
摘要： A method of forming a metal gate in a wafer. PolySi1-xGex and polysilicon are used to form a tapered groove. Gate oxide, PolySi1-xGex, and polysilicon is deposited on a wafer. A resist pattern is formed. A portion of the polysilicon, PolySi1-xGex, and gate oxide is removed to provide a tapered profile. The resist is removed; a dielectric liner is deposited, and then at least a portion of the dielectric liner is removed, thereby exposing the polysilicon and leaving the dielectric liner in contact with the polysilicon, PolyS1-xGex, and gate oxide. A dielectric is deposited, and a portion is removed thereby exposing the polysilicon. The polysilicon, PolySi1-xGex, and gate oxide is removed from inside the dielectric liner, thereby leaving a tapered gate groove. Metal is then deposited in the groove.
摘要翻译：一种在晶片中形成金属栅极的方法。多晶硅1-x x Ge x S和多晶硅用于形成锥形槽。栅极氧化物，多晶硅1-x x Ge x，并且多晶硅沉积在晶片上。形成抗蚀剂图案。去除多晶硅的一部分，多晶硅1-x N x N x N和栅极氧化物以提供锥形轮廓。去除抗蚀剂; 沉积电介质衬垫，然后去除电介质衬垫的至少一部分，从而暴露多晶硅并使电介质衬垫与多晶硅接触，PolyS 1-x Ge x 和/或栅极氧化物。沉积电介质，一部分被去除，从而暴露多晶硅。从电介质衬垫的内部去除多晶硅，多晶硅1 x x Ge x x和栅极氧化物，从而留下锥形栅极沟槽。然后将金属沉积在凹槽中。

5. 发明授权

US07405116B2 Application of gate edge liner to maintain gate length CD in a replacement gate transistor flow 有权
标题翻译：门边缘衬垫的应用以保持栅极长度CD在替代栅极晶体管流中
公开(公告)号：US07405116B2
公开(公告)日：2008-07-29
申请号：US10916322
申请日：2004-08-11
申请人： Richard J. Carter , Wai Lo , Sey-Shing Sun , Hong Lin , Verne Hornback
发明人： Richard J. Carter , Wai Lo , Sey-Shing Sun , Hong Lin , Verne Hornback
IPC分类号： H01L21/338
CPC分类号： H01L29/6656 , H01L21/823828 , H01L29/66545 , H01L29/6659 , H01L29/7833
摘要： A method to maintain a well-defined gate stack profile, deposit or grow a uniform gate dielectric, and maintain gate length CD control by means of an inert insulating liner deposited after dummy gate etch and before the spacer process. The liner material is selective to wet chemicals used to remove the dummy gate oxide thereby preventing undercut in the spacer region. The method is aimed at making the metal gate electrode technology a feasible technology with maximum compatibility with the existing fabrication environment for multiple generations of CMOS transistors, including those belonging to the 65 nm, 45 nm and 25 nm technology nodes, that are being used in analog, digital or mixed signal integrated circuit for various applications such as communication, entertainment, education and security products.
摘要翻译：保持良好限定的栅极堆叠轮廓的方法，沉积或生长均匀的栅极电介质，并且通过在虚拟栅极蚀刻之后和间隔物工艺之前沉积的惰性绝缘衬垫来维持栅极长度CD控制。衬垫材料对用于去除伪栅极氧化物的湿化学品是选择性的，从而防止间隔区域中的底切。该方法旨在使金属栅极电极技术成为与现有制造环境兼容的可行技术，用于多代CMOS晶体管，包括属于65nm，45nm和25nm技术节点的CMOS晶体管，这些晶体管正在用于模拟，数字或混合信号集成电路，用于通信，娱乐，教育和安全产品等各种应用。

6. 发明申请

US20080308882A1 APPLICATION OF GATE EDGE LINER TO MAINTAIN GATE LENGTH CD IN A REPLACEMENT GATE TRANSISTOR FLOW 有权
标题翻译：门盖边缘应用于更换门盖晶体管流程中的门长度CD
公开(公告)号：US20080308882A1
公开(公告)日：2008-12-18
申请号：US12140773
申请日：2008-06-17
申请人： Richard J. Carter , Wai Lo , Sey-Shing Sun , Hong Lin , Verne Hornback
发明人： Richard J. Carter , Wai Lo , Sey-Shing Sun , Hong Lin , Verne Hornback
IPC分类号： H01L29/00
CPC分类号： H01L29/49 , G02B6/3897 , G02B6/445 , H01L29/51 , H02G15/117
摘要： A method to maintain a well-defined gate stack profile, deposit or grow a uniform gate dielectric, and maintain gate length CD control by means of an inert insulating liner deposited after dummy gate etch and before the spacer process. The liner material is selective to wet chemicals used to remove the dummy gate oxide thereby preventing undercut in the spacer region. The method is aimed at making the metal gate electrode technology a feasible technology with maximum compatibility with the existing fabrication environment for multiple generations of CMOS transistors, including those belonging to the 65 nm, 45 nm and 25 nm technology nodes, that are being used in analog, digital or mixed signal integrated circuit for various applications such as communication, entertainment, education and security products.
摘要翻译：保持良好限定的栅极堆叠轮廓的方法，沉积或生长均匀的栅极电介质，并且通过在虚拟栅极蚀刻之后和间隔物工艺之前沉积的惰性绝缘衬垫来维持栅极长度CD控制。衬垫材料对用于去除伪栅极氧化物的湿化学品是选择性的，从而防止间隔区域中的底切。该方法旨在使金属栅极电极技术成为与现有制造环境兼容的可行技术，用于多代CMOS晶体管，包括属于65nm，45nm和25nm技术节点的CMOS晶体管，这些晶体管正在用于模拟，数字或混合信号集成电路，用于通信，娱乐，教育和安全产品等各种应用。

7. 发明授权

US08384165B2 Application of gate edge liner to maintain gate length CD in a replacement gate transistor flow 有权
标题翻译：门边缘衬垫的应用以保持栅极长度CD在替代栅极晶体管流中
公开(公告)号：US08384165B2
公开(公告)日：2013-02-26
申请号：US12140773
申请日：2008-06-17
申请人： Richard J. Carter , Wai Lo , Sey-Shing Sun , Hong Lin , Verne Hornback
发明人： Richard J. Carter , Wai Lo , Sey-Shing Sun , Hong Lin , Verne Hornback
IPC分类号： H01L29/49 , H01L29/51
CPC分类号： H01L29/49 , G02B6/3897 , G02B6/445 , H01L29/51 , H02G15/117
摘要： A method to maintain a well-defined gate stack profile, deposit or grow a uniform gate dielectric, and maintain gate length CD control by means of an inert insulating liner deposited after dummy gate etch and before the spacer process. The liner material is selective to wet chemicals used to remove the dummy gate oxide thereby preventing undercut in the spacer region. The method is aimed at making the metal gate electrode technology a feasible technology with maximum compatibility with the existing fabrication environment for multiple generations of CMOS transistors, including those belonging to the 65 nm, 45 nm and 25 nm technology nodes, that are being used in analog, digital or mixed signal integrated circuit for various applications such as communication, entertainment, education and security products.
摘要翻译：保持良好限定的栅极堆叠轮廓的方法，沉积或生长均匀的栅极电介质，并且通过在虚拟栅极蚀刻之后和间隔物工艺之前沉积的惰性绝缘衬垫来维持栅极长度CD控制。衬垫材料对用于去除伪栅极氧化物的湿化学品是选择性的，从而防止间隔区域中的底切。该方法旨在使金属栅极电极技术成为与现有制造环境兼容的可行技术，用于多代CMOS晶体管，包括属于65nm，45nm和25nm技术节点的CMOS晶体管，这些晶体管正在用于模拟，数字或混合信号集成电路，用于通信，娱乐，教育和安全产品等各种应用。

8. 发明申请

US20060118919A1 Bi-axial texturing of high-K dielectric films to reduce leakage currents 失效
公开(公告)号：US20060118919A1
公开(公告)日：2006-06-08
申请号：US11007392
申请日：2004-12-07
申请人： Wai Lo , Sey-Shing Sun , Wilbur Catabay
发明人： Wai Lo , Sey-Shing Sun , Wilbur Catabay
IPC分类号： H01L29/04
CPC分类号： H01L29/51 , C23C14/226 , C23C14/3442 , C23C14/46 , C23C16/486 , H01L21/02189 , H01L21/02266 , H01L21/28194 , H01L21/31604 , H01L21/31616 , H01L21/31641 , H01L21/31645
摘要： The present invention is directed to a method of fabricating a high-K dielectric films having a high degree of crystallographic alignment at grain boundaries of the film. A disclosed method involves providing a substrate and then depositing a material used in forming the high-K dielectric film and also using an ion beam to assist in the preferential formation of crystal lattices having a selected crystallographic orientation. The resultant dielectric film having a high degree of crystallographic alignment at grain boundaries of the film. Another disclosed method involves providing a substrate and then angularly depositing a material onto the substrate in order to assist in the preferential formation of crystal lattices having a selected crystallographic orientation. The resultant dielectric film having a high degree of crystallographic alignment at grain boundaries of the film.

9. 发明授权

US07064062B2 Incorporating dopants to enhance the dielectric properties of metal silicates 失效
标题翻译：掺入掺杂剂以增强金属硅酸盐的介电性能
公开(公告)号：US07064062B2
公开(公告)日：2006-06-20
申请号：US10738761
申请日：2003-12-16
申请人： Wai Lo , Verne Hornback , Wilbur G. Catabay , Wei-Jen Hsia , Sey-Shing Sun
发明人： Wai Lo , Verne Hornback , Wilbur G. Catabay , Wei-Jen Hsia , Sey-Shing Sun
IPC分类号： H01L21/4763 , B05D3/02
CPC分类号： H01L21/02142 , H01L21/02323 , H01L21/3115 , H01L21/31604 , H01L21/31612 , H01L21/31637 , H01L21/31645
摘要： The present invention provides a method of forming a high-k dielectric layer on a semiconductor wafer. A metal silicate dielectric layer is initially deposited on the wafer. A dopant having dissociable oxygen is introduced into the metal silicate on the wafer. According to one embodiment the metal silicate comprises a group IV metal and the dopant is an oxide of one of an alkaline metal and an alkaline earth metal. According to another embodiment the metal silicate comprises a group III metal.
摘要翻译：本发明提供了在半导体晶片上形成高k电介质层的方法。金属硅酸盐介电层最初沉积在晶片上。将具有可离解氧的掺杂剂引入到晶片上的金属硅酸盐中。根据一个实施方案，金属硅酸盐包含IV族金属，掺杂剂是碱金属和碱土金属之一的氧化物。根据另一个实施方案，金属硅酸盐包含III族金属。

10. 发明授权

US07619272B2 Bi-axial texturing of high-K dielectric films to reduce leakage currents 失效
标题翻译：高K电介质膜的双轴纹理化以减少漏电流
公开(公告)号：US07619272B2
公开(公告)日：2009-11-17
申请号：US11007392
申请日：2004-12-07
申请人： Wai Lo , Sey-Shing Sun , Wilbur Catabay
发明人： Wai Lo , Sey-Shing Sun , Wilbur Catabay
IPC分类号： H01L29/76
CPC分类号： H01L29/51 , C23C14/226 , C23C14/3442 , C23C14/46 , C23C16/486 , H01L21/02189 , H01L21/02266 , H01L21/28194 , H01L21/31604 , H01L21/31616 , H01L21/31641 , H01L21/31645
摘要： The present invention is directed to a method of fabricating a high-K dielectric films having a high degree of crystallographic alignment at grain boundaries of the film. A disclosed method involves providing a substrate and then depositing a material used in forming the high-K dielectric film and also using an ion beam to assist in the preferential formation of crystal lattices having a selected crystallographic orientation. The resultant dielectric film having a high degree of crystallographic alignment at grain boundaries of the film. Another disclosed method involves providing a substrate and then angularly depositing a material onto the substrate in order to assist in the preferential formation of crystal lattices having a selected crystallographic orientation. The resultant dielectric film having a high degree of crystallographic alignment at grain boundaries of the film.
摘要翻译：本发明涉及制造在膜的晶界处具有高度晶体取向度的高K电介质膜的方法。所公开的方法包括提供衬底，然后沉积用于形成高K电介质膜的材料，并且还使用离子束来辅助优选形成具有选定结晶取向的晶格。所得的电介质膜在膜的晶界处具有高度的结晶取向度。另一公开的方法包括提供衬底，然后将材料成角度地沉积到衬底上，以帮助优先形成具有选定结晶取向的晶格。所得的电介质膜在膜的晶界处具有高度的结晶取向度。

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