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61. 发明授权

US06434072B1 Row decoded biasing of sense amplifier for improved one's margin 有权
公开(公告)号：US06434072B1
公开(公告)日：2002-08-13
申请号：US09862694
申请日：2001-05-22
申请人： Patrick J. Mullarkey , Scott J. Derner
发明人： Patrick J. Mullarkey , Scott J. Derner
IPC分类号： G11C702
摘要： A structure and method to improve sense amplifier operation in memory circuits is provided. An illustrative method of the present invention includes taking the predecoded the row address signals (i.e. RA123 , LPHe , LPHo ) that run down the rowdriver seams in a memory array (peripheral circuitry), and decoding those address signals in the sense amplifier gaps. The decoding is done to fire a signal that runs up the sense amplifier gap and biases the sense amplifier to fire in one direction or the other. Exemplary embodiments of the present invention are as follows. One method of the present invention includes putting two small n-channel transistors in parallel with each of the cross-coupled n-channel transistors in the n-sense amplifier. The gates of the two small n-channel transistors are initially low. Then, depending on the intended direction for biasing the sense amplifier, the gate of one of the small n-channel transistors would go to DVC2 until the p-sense amplifier fires. The reference digitline (DIG*) coupled in parallel with the fired small n-channel is pulled to ground harder, or assisted to ground faster than the other digitline (DIG) with the effect of favoring a “sensed” logical “1” on the latter. The biasing of the sense amplifier is set so that a zero can still be read out correctly. In result, where a detected signal voltage difference between the digitline (DIG) and the reference digitline (DIG*) is small, e.g., to the point where a normal sense amplifier will read either toward a logical “1” or a logical “0,” the biasing will cause the sense amplifier to read a logical “1”. A second method of the present invention includes using two separate n-sense amplifier bus lines (RNL*s) in each individual sense amplifier gap. One n-sense amplifier bus line (RNL*) is connected to each of the cross-coupled n-channel transistors in the n-sense amplifier. One of the separate n-sense amplifier bus lines (RNL*s) is biased greater than the other. When the n-sense amplifier fires, the digitline (DIG) favors sensing a logical “1”.

62. 发明授权

US06385691B2 Memory device with command buffer that allows internal command buffer jumps 有权
标题翻译：具有命令缓冲区的内存设备，允许内部命令缓冲区跳转
公开(公告)号：US06385691B2
公开(公告)日：2002-05-07
申请号：US09764502
申请日：2001-01-17
申请人： Patrick J. Mullarkey , Casey R. Kurth , Scott J. Derner
发明人： Patrick J. Mullarkey , Casey R. Kurth , Scott J. Derner
IPC分类号： G06F1200
CPC分类号： G11C7/1072
摘要： A memory device includes a memory array, a plurality of external lines, a command buffer, and control logic. The plurality of external lines is adapted for receiving an external command. The command buffer is adapted to store at least one command buffer entry. The control logic is coupled to the plurality of external lines and the command buffer. The control logic is adapted to access the memory array based on one of the command buffer entry and the external command. A method for providing commands to a memory device is provided. The memory device includes a command buffer, control logic and a memory array. The method includes reading a first buffered command from the command buffer. The first buffered command is provided to the control logic. The memory array is accessed based on the first buffered command.
摘要翻译：存储器件包括存储器阵列，多条外部线，命令缓冲器和控制逻辑。多个外部线路适于接收外部命令。命令缓冲器适于存储至少一个命令缓冲器条目。控制逻辑耦合到多条外部线路和命令缓冲器。控制逻辑适于基于命令缓冲器条目和外部命令之一访问存储器阵列。提供了一种向存储器件提供命令的方法。存储器件包括命令缓冲器，控制逻辑和存储器阵列。该方法包括从命令缓冲区读取第一缓冲命令。第一个缓冲命令提供给控制逻辑。基于第一个缓冲命令访问存储器阵列。

63. 发明授权

US06292421B1 Method and apparatus for multiple row activation in memory devices 有权
标题翻译：存储器件中多行激活的方法和装置
公开(公告)号：US06292421B1
公开(公告)日：2001-09-18
申请号：US09629573
申请日：2000-07-31
申请人： Michael A. Shore , Patrick J. Mullarkey
发明人： Michael A. Shore , Patrick J. Mullarkey
IPC分类号： G11C700
CPC分类号： G11C29/34
摘要： A memory device test circuit and method are described. These operate to maintain a local phase signal active over multiple row activate commands. As a result, an arbitrary number of word lines may be activated together, in an arbitrary order and in arbitrary locations, in response to user-programmable instructions. This allows test sequences to be tailored after the memory device has been designed and can greatly reduce testing times for memory devices.
摘要翻译：描述了存储器件测试电路和方法。这些操作用于通过多个行激活命令维持本地相位信号的活动。结果，响应于用户可编程指令，可以以任意顺序和任意位置一起激活任意数量的字线。这样就可以在设计存储器件之后对测试序列进行定制，并可以大大减少存储器件的测试时间。

64. 发明授权

US06275085B1 Comparator for determining process variations 有权
标题翻译：用于确定过程变化的比较器
公开(公告)号：US06275085B1
公开(公告)日：2001-08-14
申请号：US09317387
申请日：1999-05-24
申请人： Patrick J. Mullarkey
发明人： Patrick J. Mullarkey
IPC分类号： H03H1126
CPC分类号： H03K19/00323 , H03K5/159 , H03K5/26
摘要： A comparison circuit may be fabricated along with a primary circuit on a semiconductor substrate. The propagation delay of a comparison signal across a first path of circuit elements is compared to propagation delays of the comparison signal across a second path of delay elements. As a semiconductor fabrication process varies, the relative propagation delays across the first and second paths will vary in a manner correlative to the process variations. By monitoring the relative propagation delays, the fabrication process may be controlled to ensure that the process does not vary to an undesirable extent. Also, various programmable delay elements may be fabricated into the primary circuit, and these programmable delay elements may be activated and/or deactivated in response to the relative propagation delays of the comparison circuit.
摘要翻译：可以在半导体衬底上与初级电路一起制造比较电路。跨越电路元件的第一路径的比较信号的传播延迟与延迟元件的第二路径上的比较信号的传播延迟进行比较。随着半导体制造过程的变化，穿过第一和第二路径的相对传播延迟将以与过程变化相关的方式变化。通过监测相对传播延迟，可以控制制造过程以确保该过程不会变化到不期望的程度。此外，可以将各种可编程延迟元件制造成初级电路，并且这些可编程延迟元件可以响应于比较电路的相对传播延迟而被激活和/或去激活。

65. 发明授权

US06269451B1 Method and apparatus for adjusting data timing by delaying clock signal 失效
标题翻译：用于通过延迟时钟信号来调整数据定时的方法和装置
公开(公告)号：US06269451B1
公开(公告)日：2001-07-31
申请号：US09032256
申请日：1998-02-27
申请人： Patrick J. Mullarkey
发明人： Patrick J. Mullarkey
IPC分类号： G06F104
CPC分类号： G06F5/06 , G06F2205/104
摘要： A circuit for adjusting a time when data is delivered to a data terminal with respect to an external clock signal includes a data passing circuit and a delay adjusting circuit. The delay adjusting circuit accepts a plurality of control signals each arranged to control passgates arranged in columns, with one column being controlled by a respective one of the control signals. A clock signal passes in parallel manner through a variety of delay gates, and each delay gate is coupled in series with one of the passgates. By selecting a path through desired passgates, one delay path is selected and the delay time added to the clock signal. This delayed clock signal is used to control the data passing circuit, which controls when data is output to the output terminals relative to the original clock signal. The control signals are created by selectively coupling or decoupling the control signals from a static voltage, and fuses or antifuses can be used to facilitate this coupling or decoupling.
摘要翻译：用于调整数据相对于外部时钟信号传送到数据终端的时间的电路包括数据通过电路和延迟调整电路。延迟调整电路接受多个控制信号，每个控制信号被布置成控制列列排列的通道，一列由相应的一个控制信号控制。时钟信号以并行方式通过各种延迟门，并且每个延迟门与其中一个通风门串联耦合。通过选择通过所需传送门的路径，选择一个延迟路径，并将延迟时间加到时钟信号上。该延迟时钟信号用于控制数据通过电路，其控制当数据相对于原始时钟信号被输出到输出端子时。通过选择性地将控制信号与静态电压耦合或去耦产生控制信号，并且可以使用熔丝或反熔丝来促进该耦合或去耦。

66. 发明授权

US06252816B1 Circuit and method for refreshing data stored in a memory cell 有权
公开(公告)号：US06252816B1
公开(公告)日：2001-06-26
申请号：US09564303
申请日：2000-05-03
申请人： Patrick J. Mullarkey
发明人： Patrick J. Mullarkey
IPC分类号： G11C700
CPC分类号： G11C11/406 , G11C2211/4061
摘要： An IC includes a memory array that has memory cells for storing data and that refreshes the data stored in a memory cell during a respective refresh cycle of a refresh mode. The integrated circuit also includes a refresh circuit that during a first portion of the refresh mode implements a first series of refresh cycles in the memory array at a first frequency and that during a second portion of the refresh mode implements a second series of refresh cycles in the memory array at a second frequency. Such a refresh circuit allows longer internal row-line on times during a self-refresh mode without affecting the auto-refresh TRC, which is the specified maximum time that the IC requires to execute an auto-refresh cycle. Therefore, the IC can consume less power during a self-refresh mode and still meet the same auto-refresh specification.

67. 发明授权

US6160413A Apparatus and method for disabling and re-enabling access to IC test functions 有权
标题翻译：用于禁用和重新启用IC测试功能的设备和方法
公开(公告)号：US6160413A
公开(公告)日：2000-12-12
申请号：US222674
申请日：1998-12-29
申请人： Daryl L. Habersetzer , Casey R. Kurth , Patrick J. Mullarkey , Jason E. Graalum
发明人： Daryl L. Habersetzer , Casey R. Kurth , Patrick J. Mullarkey , Jason E. Graalum
IPC分类号： G01R31/28 , G01R31/317
CPC分类号： G01R31/31701 , G01R31/2884
摘要： A test-mode latching circuit residing on an integrated circuit with test circuitry and operational circuitry has an enable state and a disable state. In the enable state, a test key is able to be latched so as to trigger a test mode. In the disable state, test key inputs are not latched, and thus, test modes are not entered. Initially, the circuit is readily enabled so that the IC can be tested upon fabrication. The circuit is locked in a disable state before external sale. A re-enable circuit is present to preclude inadvertent switching of the latching circuit back into the enable state during customer operation. Safeguards are implemented to avoid inadvertently re-enabling the latching circuit. To re-enable the latching circuit, an out-of-spec voltage is applied to an anti-fuse capacitor or programmable logic circuit while an out-of-spec voltage of the same or another signal is detected at a field device. In one embodiment, the state switches to the enable state in response to the out-of-spec voltage. In alternative embodiments, an additional or subsequent signal, such as a prescribed clock pattern, occurs before the first circuit switches to the enable state.
摘要翻译：测试模式锁存电路驻留在具有测试电路和具有使能状态和禁止状态的操作电路的集成电路上。在使能状态下，可以锁存测试键以触发测试模式。在禁用状态下，测试键输入不被锁存，因此不输入测试模式。最初，该电路容易启用，使IC可以在制造时进行测试。电路在外部销售之前被锁定在禁用状态。存在重启动电路，以防止在客户操作期间将锁存电路意外切换回使能状态。实施保护措施以避免无意中重新启用锁存电路。为了重新启用锁存电路，在现场设备上检测到相同或另一信号的超出规格的电压时，会将超出规格的电压施加到反熔丝电容器或可编程逻辑电路。在一个实施例中，状态响应于超出规格的电压而切换到使能状态。在替代实施例中，在第一电路切换到使能状态之前发生附加或后续信号，例如规定的时钟模式。

68. 发明授权

US6154410A Method and apparatus for reducing antifuse programming time 失效
标题翻译：减少反熔丝编程时间的方法和装置
公开(公告)号：US6154410A
公开(公告)日：2000-11-28
申请号：US795531
申请日：1997-02-05
申请人： Douglas J. Cutter , Kurt D. Beigel , Adrian E. Ong , Fan Ho , Patrick J. Mullarkey , Dien Luong , Brett Debenham , Kim Pierce
发明人： Douglas J. Cutter , Kurt D. Beigel , Adrian E. Ong , Fan Ho , Patrick J. Mullarkey , Dien Luong , Brett Debenham , Kim Pierce
IPC分类号： G11C17/18 , G11C7/00
CPC分类号： G11C17/18
摘要： Method and apparatus are disclosed for reducing antifuse programming time by connecting the programming voltage to the electrode of the antifuse element that has roughened polysilicon.
摘要翻译：公开了通过将编程电压连接到具有粗糙多晶硅的反熔丝元件的电极来减少反熔丝编程时间的方法和装置。

69. 发明授权

US6115306A Method and apparatus for multiple row activation in memory devices 有权
公开(公告)号：US6115306A
公开(公告)日：2000-09-05
申请号：US384134
申请日：1999-08-27
申请人： Michael A. Shore , Patrick J. Mullarkey
发明人： Michael A. Shore , Patrick J. Mullarkey
IPC分类号： G11C7/00 , G11C29/00 , G11C29/34 , G11C8/00
CPC分类号： G11C29/34
摘要： A memory device test circuit and method are described. These operate to maintain a local phase signal active over multiple row activate commands. As a result, an arbitrary number of word lines may be activated together, in an arbitrary order and in arbitrary locations, in response to user-programmable instructions. This allows test sequences to be tailored after the memory device has been designed and can greatly reduce testing times for memory devices.

70. 发明授权

US06075737A Row decoded biasing of sense amplifier for improved one's margin 有权
公开(公告)号：US06075737A
公开(公告)日：2000-06-13
申请号：US204112
申请日：1998-12-02
申请人： Patrick J. Mullarkey , Scott J. Derner
发明人： Patrick J. Mullarkey , Scott J. Derner
IPC分类号： G11C7/06 , G11C7/02
CPC分类号： G11C7/065
摘要： A structure and method to improve sense amplifier operation in memory circuits is provided. An illustrative method of the present invention includes taking the predecoded the row address signals (i.e. RA123 , LPHe , LPHo ) that run down the rowdriver seams in a memory array (peripheral circuitry), and decoding those address signals in the sense amplifier gaps. The decoding is done to fire a signal that runs up the sense amplifier gap and biases the sense amplifier to fire in one direction or the other. Exemplary embodiments of the present invention are as follows. One method of the present invention includes putting two small n-channel transistors in parallel with each of the cross-coupled n-channel transistors in the n-sense amplifier. The gates of the two small n-channel transistors are initially low. Then, depending on the intended direction for biasing the sense amplifier, the gate of one of the small n-channel transistors would go to DVC2 until the p-sense amplifier fires. The reference digitline (DIG*) coupled in parallel with the fired small n-channel is pulled to ground harder, or assisted to ground faster than the other digitline (DIG) with the effect of favoring a "sensed" logical "1" on the latter. The biasing of the sense amplifier is set so that a zero can still be read out correctly. In result, where a detected signal voltage difference between the digitline (DIG) and the reference digitline (DIG*) is small, e.g., to the point where a normal sense amplifier will read either toward a logical "1" or a logical "0," the biasing will cause the sense amplifier to read a logical "1".A second method of the present invention includes using two separate n-sense amplifier bus lines (RNL*s) in each individual sense amplifier gap. One n-sense amplifier bus line (RNL*) is connected to each of the cross-coupled n-channel transistors in the n-sense amplifier. One of the separate n-sense amplifier bus lines (RNL*s) is biased greater than the other. When the n-sense amplifier fires, the digitline (DIG) favors sensing a logical "1".

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