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1. 发明授权

US06826071B2 Circuit for programming antifuse bits 失效
标题翻译：用于编程反熔丝位的电路
公开(公告)号：US06826071B2
公开(公告)日：2004-11-30
申请号：US10098262
申请日：2002-03-15
申请人： Patrick J. Mullarkey , Casey R. Kurth , Jason Graalum , Daryl L. Habersetzer
发明人： Patrick J. Mullarkey , Casey R. Kurth , Jason Graalum , Daryl L. Habersetzer
IPC分类号： G11C1700
CPC分类号： G11C17/18
摘要： A method of verifying whether unprogrammed antifuses are leaky in a semiconductor memory. The method involves the steps of: connecting the antifuse in series with a node; providing current to the node, the current being sufficient to charge the node from a first to a second voltage; detecting whether the voltage at the node charges to the second voltage, or remains at the first voltage to indicate that the antifuse is leaky; outputting signals indicating the result of the detection; and detecting the voltage at the node remains at the first voltage indicates that the antifuse is leaky. In another embodiment, a method of verifying whether antifuses have been programmed properly in a semiconductor memory. The method includes the steps of: connecting the antifuse in series with a node; providing current to the node through a parallel combination of a first transistor and a second transistor that is sufficient to charge the node from a first voltage to a second voltage; and detecting whether the voltage at the node charges to the second voltage or remains at the first voltage to indicate that the antifuse is programmed properly; outputting first and second signals indicating the result of the detection; and detecting the voltage at the node remains at the first voltage indicates that the antifuse is programmed properly.
摘要翻译：验证半导体存储器中未编程的反熔丝是否泄漏的方法。该方法包括以下步骤：将反熔丝与节点串联连接; 向节点提供电流，电流足以使节点从第一电压到第二电压充电; 检测节点处的电压是否充电到第二电压，或者保持在第一电压以指示反熔丝泄漏; 输出指示检测结果的信号; 并且检测节点处的电压保持在第一电压，表示反熔丝泄漏。在另一个实施例中，验证在半导体存储器中是否正确地编程了反熔丝的方法。该方法包括以下步骤：将反熔丝与节点串联连接; 通过第一晶体管和第二晶体管的并联组合向节点提供电流，其足以将节点从第一电压充电到第二电压; 并且检测节点处的电压是否充电到第二电压或者保持在第一电压以指示反熔丝被正确编程; 输出表示检测结果的第一和第二信号; 并且检测节点处的电压保持在第一电压，表示反熔丝被正确编程。

2. 发明授权

US06701470B1 Method for testing a memory device having different number of data pads than the tester 失效
标题翻译：用于测试具有与测试器不同数量的数据焊盘数量的存储器件的方法
公开(公告)号：US06701470B1
公开(公告)日：2004-03-02
申请号：US09649829
申请日：2000-08-29
申请人： Patrick J. Mullarkey , Michael A. Shore
发明人： Patrick J. Mullarkey , Michael A. Shore
IPC分类号： G11C2900
CPC分类号： G11C29/1201 , G11C29/48
摘要： Testing a memory device having M data pads with a tester having N
摘要翻译：用具有N

3. 发明授权

US06678186B2 Row decoded biasing of sense amplifier for improved one's margin 有权
标题翻译：读出放大器的行解码偏置，提高了余量
公开(公告)号：US06678186B2
公开(公告)日：2004-01-13
申请号：US10216990
申请日：2002-08-12
申请人： Patrick J. Mullarkey , Scott J. Derner
发明人： Patrick J. Mullarkey , Scott J. Derner
IPC分类号： G11C700
CPC分类号： G11C7/065
摘要： A structure and method to improve sense amplifier operation in memory circuits is provided. An illustrative method of the present invention includes taking the predecoded the row address signals (i.e. RA123 , LPHe , LPHo ) that run down the rowdriver seams in a memory array (peripheral circuitry), and decoding those address signals in the sense amplifier gaps. The decoding is done to fire a signal that runs up the sense amplifier gap and biases the sense amplifier to fire in one direction or the other.
摘要翻译：提供了一种用于改善存储器电路中的读出放大器操作的结构和方法。本发明的说明性方法包括对在存储器阵列（外围电路）中的行驱动器接缝运行的行地址信号（即，RA123 ，LPHe ，LPHo ）进行预解码，并对其进行解码读出放大器间隙中的地址信号。完成解码以激发上升读出放大器间隙的信号，并将读出放大器偏置在一个方向或另一个方向上发射。

4. 发明授权

US06590407B2 Apparatus for disabling and re-enabling access to IC test functions 有权
标题翻译：用于禁用和重新启用IC测试功能的设备
公开(公告)号：US06590407B2
公开(公告)日：2003-07-08
申请号：US10222113
申请日：2002-08-16
申请人： Daryl L. Habersetzer , Casey R. Kurth , Patrick J. Mullarkey , Jason E. Graalum
发明人： Daryl L. Habersetzer , Casey R. Kurth , Patrick J. Mullarkey , Jason E. Graalum
IPC分类号： G01R3128
CPC分类号： G01R31/31701 , G01R31/2884
摘要： A test-mode latching circuit residing on an integrated circuit with test circuitry and operational circuitry has an enable state and a disable state. In the enable state, a test key is able to be latched so as to trigger a test mode. In the disable state, test key inputs are not latched, and thus, test modes are not entered. Initially, the circuit is readily enabled so that the IC can be tested upon fabrication. The circuit is locked in a disable state before external sale. A re-enable circuit is present to preclude inadvertent switching of the latching circuit back into the enable state during customer operation. Safeguards are implemented to avoid inadvertently re-enabling the latching circuit. To re-enable the latching circuit, an out-of-spec voltage is applied to an anti-fuse capacitor or programmable logic circuit while an out-of-spec voltage of the same or another signal is detected at a field device. In one embodiment, the state switches to the enable state in response to the out-of-spec voltage. In alternative embodiments, an additional or subsequent signal, such as a prescribed clock pattern, occurs before the first circuit switches to the enable state.
摘要翻译：驻留在具有测试电路和操作电路的集成电路上的测试模式锁存电路具有使能状态和禁止状态。在使能状态下，可以锁存测试键以触发测试模式。在禁用状态下，测试键输入不被锁存，因此不输入测试模式。最初，该电路容易启用，使IC可以在制造时进行测试。电路在外部销售之前被锁定在禁用状态。存在重启动电路，以防止在客户操作期间将锁存电路意外切换回使能状态。实施保护措施以避免无意中重新启用锁存电路。为了重新启用锁存电路，在现场设备上检测到相同或另一信号的超出规格的电压时，会将超出规格的电压施加到反熔丝电容器或可编程逻辑电路。在一个实施例中，状态响应于超出规格的电压而切换到使能状态。在替代实施例中，在第一电路切换到使能状态之前发生附加或后续信号，例如规定的时钟模式。

5. 发明授权

US06351141B2 Method and apparatus for limited reprogrammability of fuse options using one-time programmable elements 失效
标题翻译：使用一次性可编程元件的熔丝选项的有限可编程性的方法和装置
公开(公告)号：US06351141B2
公开(公告)日：2002-02-26
申请号：US09882516
申请日：2001-06-15
申请人： Patrick J. Mullarkey
发明人： Patrick J. Mullarkey
IPC分类号： G06F738
CPC分类号： H03K19/1732 , H03K19/1736
摘要： A method and apparatus for limited reprogrammability of fuse options in a semiconductor device is disclosed. In one embodiment, option circuitry includes a plurality of programmable devices each actuable from a first state to a second state and an option circuitry, which is coupled to the plurality of programmable devices to receive a plurality of logic signals reflecting the respective states of the plurality of programmable devices. The option circuitry is responsive to the plurality of logic signals to assert a particular one of a plurality of distinct option signals. The particular option signal is determined based on the particular combination of respective states of the plurality of programmable devices. The semiconductor device is responsive to assertion of each of the plurality of distinct option signals to operate in a distinct one of at least two operational modes. The option circuitry is responsive to at least two distinct combinations of respective states of the plurality of programmable devices to assert the same option signal, such that the semiconductor device can be programmed to operate first in a first of the at least two operational modes, then in a second of the at least two operational modes, and then again in the first of the at least two operational modes.
摘要翻译：公开了一种用于半导体器件中的熔丝选项的有限重新编程性的方法和装置。在一个实施例中，选项电路包括可从第一状态致动到第二状态的多个可编程设备和选项电路，其耦合到多个可编程设备以接收反映多个状态的多个逻辑信号的可编程器件。选项电路响应于多个逻辑信号以断言多个不同选项信号中的特定一个。特定选项信号基于多个可编程设备的各自状态的特定组合来确定。半导体器件响应于多个不同选项信号中的每一个的断言以至少两种操作模式中的不同的一种运行。选项电路响应多个可编程设备的相应状态的至少两个不同的组合来断言相同的选项信号，使得半导体器件可以被编程为首先在至少两个操作模式中的第一个中操作，然后在所述至少两个操作模式中的第二个中，然后再次在所述至少两个操作模式中的第一个中。

6. 发明授权

US06327196B1 Synchronous memory device having an adjustable data clocking circuit 有权
标题翻译：具有可调节数据时钟电路的同步存储器件
公开(公告)号：US06327196B1
公开(公告)日：2001-12-04
申请号：US09534186
申请日：2000-03-24
申请人： Patrick J. Mullarkey
发明人： Patrick J. Mullarkey
IPC分类号： G11C700
CPC分类号： G06F5/06 , G06F2205/104
摘要： A circuit for adjusting a time when data is delivered to a data terminal with respect to an external clock signal includes a data passing circuit and a delay adjusting circuit. The delay adjusting circuit accepts a plurality of control signals each arranged to control passgates arranged in columns, with one column being controlled by a respective one of the control signals. A clock signal passes in parallel manner through a variety of delay gates, and each delay gate is coupled in series with one of the passgates. By selecting a path through desired passgates, one delay path is selected and the delay time added to the clock signal. This delayed clock signal is used to control the data passing circuit, which controls when data is output to the output terminals relative to the original clock signal. The control signals are created by selectively coupling or decoupling the control signals from a static voltage, and fuses or antifuses can be used to facilitate this coupling or decoupling.
摘要翻译：用于调整数据相对于外部时钟信号传送到数据终端的时间的电路包括数据通过电路和延迟调整电路。延迟调整电路接受多个控制信号，每个控制信号被布置成控制列列排列的通道，一列由相应的一个控制信号控制。时钟信号以并行方式通过各种延迟门，并且每个延迟门与其中一个通风门串联耦合。通过选择通过所需传送门的路径，选择一个延迟路径，并将延迟时间加到时钟信号上。该延迟时钟信号用于控制数据通过电路，其控制当数据相对于原始时钟信号被输出到输出端子时。通过选择性地将控制信号与静态电压耦合或去耦产生控制信号，并且可以使用熔丝或反熔丝来促进该耦合或去耦。

7. 发明授权

US06285600B1 Device and method for supplying current to a semiconductor memory to support a boosted voltage within the memory during testing 有权
标题翻译：用于向半导体存储器提供电流以在测试期间支持存储器内的升压电压的装置和方法
公开(公告)号：US06285600B1
公开(公告)日：2001-09-04
申请号：US09688993
申请日：2000-10-16
申请人： Patrick J. Mullarkey
发明人： Patrick J. Mullarkey
IPC分类号： G11C700
CPC分类号： G11C29/50 , G11C5/145 , G11C11/401 , G11C11/4074 , G11C29/12 , G11C2029/5004
摘要： A Dynamic Random Access Memory (DRAM) device includes a bus for distributing a boosted voltage VCCP within the device. A conventional internal voltage regulator, ring oscillator, and charge pump help to boost the boosted voltage VCCP on the bus when the voltage VCCP falls below a preset minimum. During testing of the DRAM device, when the demand on the boosted voltage VCCP can be four or more times as much as it is under normal operating conditions, an external current source drives current ICCP into an unused bond pad, such as a no-connection (NC) or address signal bond pad. An NMOS transistor switch then connects this bond pad to the boosted voltage VCCP bus when a pump circuit controlled by the ring oscillator activates the switch. As a result, the external current augments the efforts of the internal charge pump to boost the voltage VCCP during testing, so there is no need to build the internal charge pump with oversized capacitors to handle the excessive VCCP demand during testing.
摘要翻译：动态随机存取存储器（DRAM）装置包括用于在该装置内分配升压电压VCCP的总线。当电压VCCP低于预设的最小值时，传统的内部稳压器，环形振荡器和电荷泵有助于提高总线上的升压电压VCCP。在DRAM器件的测试期间，当对升压电压VCCP的需求可以是正常操作条件下的四倍或更多倍时，外部电流源将电流ICCP驱动到未使用的接合焊盘中，例如不连接（NC）或地址信号焊盘。然后，当由环形振荡器控制的泵电路激活开关时，NMOS晶体管开关将该接合焊盘连接到升压电压VCCP总线。因此，外部电流增加了内部电荷泵的努力，以在测试期间提高电压VCCP，因此不需要构建具有超大电容器的内部电荷泵来处理测试期间过度的VCCP需求。

8. 发明授权

US06236606B1 Row decoded biasing of sense amplifier for improved one's margin 有权
公开(公告)号：US06236606B1
公开(公告)日：2001-05-22
申请号：US09517028
申请日：2000-03-02
申请人： Patrick J. Mullarkey , Scott J. Derner
发明人： Patrick J. Mullarkey , Scott J. Derner
IPC分类号： G11C702
CPC分类号： G11C7/065
摘要： A structure and method to improve sense amplifier operation in memory circuits is provided. An illustrative method of the present invention includes taking the predecoded the row address signals (i.e. RA123 , LPHe , LPHo ) that run down the rowdriver seams in a memory array (peripheral circuitry), and decoding those address signals in the sense amplifier gaps. The decoding is done to fire a signal that runs up the sense amplifier gap and biases the sense amplifier to fire in one direction or the other. Exemplary embodiments of the present invention are as follows. One method of the present invention includes putting two small n-channel transistors in parallel with each of the cross-coupled n-channel transistors in the n-sense amplifier. The gates of the two small n-channel transistors are initially low. Then, depending on the intended direction for biasing the sense amplifier, the gate of one of the small n-channel transistors would go to DVC2 until the p-sense amplifier fires. The reference digitline (DIG*) coupled in parallel with the fired small n-channel is pulled to ground harder, or assisted to ground faster than the other digitline (DIG) with the effect of favoring a “sensed” logical “1” on the latter. The biasing of the sense amplifier is set so that a zero can still be read out correctly. In result, where a detected signal voltage difference between the digitline (DIG) and the reference digitline (DIG*) is small, e.g., to the point where a normal sense amplifier will read either toward a logical “1” or a logical “0,” the biasing will cause the sense amplifier to read a logical “1”. A second method of the present invention includes using two separate n-sense amplifier bus lines (RNL*s) in each individual sense amplifier gap. One n-sense amplifier bus line (RNL*) is connected to each of the cross-coupled n-channel transistors in the n-sense amplifier. One of the separate n-sense amplifier bus lines (RNL*s) is biased greater than the other. When the n-sense amplifier fires, the digitline (DIG) favors sensing a logical “1”.

9. 发明授权

US6111451A Efficient VCCP supply with regulation for voltage control 有权
标题翻译：高效的VCCP电源具有电压调节功能
公开(公告)号：US6111451A
公开(公告)日：2000-08-29
申请号：US253323
申请日：1999-02-19
申请人： Mohamed A. Imam , Patrick J. Mullarkey
发明人： Mohamed A. Imam , Patrick J. Mullarkey
IPC分类号： G11C5/14 , G11C11/4074 , H02M7/06 , G06G7/64
CPC分类号： G11C5/147 , G11C11/4074 , G11C5/14 , H02M7/06
摘要： A highly efficient compact multiple output voltage generation circuit is designed for use in integrated circuit devices such as DRAMs which require multiple internal voltage supplies for optimum performance. An oscillator is connected to a primary coil of a microtransformer. The microtransformer secondary coil has multiple taps one of which is connected to ground. A second transformer tap is connected to a transformer output node. The oscillating transformer output signal is capacitively coupled to a voltage rectifier. The input to the rectifier is biased to one diode drop below Vcc. The output of the rectifier is an internal supply voltage greater than ground. Another transformer tap is connected to a negative oscillation output node. The negative oscillating signal is rectified to produce a negative internal supply voltage. The voltage generation circuit operates effectively at low Vcc input levels where capacitor based voltage pumps often fail. The circuit is compatible with CMOS manufacturing processes.
摘要翻译：高效的紧凑型多输出电压产生电路被设计用于诸如需要多个内部电压供应以获得最佳性能的DRAM的集成电路器件中。振荡器连接到微型变压器的初级线圈。微型变压器次级线圈具有多个抽头，其中一个连接到地。第二个变压器抽头连接到变压器输出节点。振荡变压器输出信号电容耦合到电压整流器。整流器的输入偏置到低于Vcc的一个二极管压降。整流器的输出是大于地的内部电源电压。另一个变压器抽头连接到负振荡输出节点。负振荡信号被整流以产生负的内部电源电压。电压产生电路在低Vcc输入电平下有效地运行，其中基于电容器的电压泵通常失效。该电路与CMOS制造工艺兼容。

10. 发明授权

US5793691A Memory device with MOS transistors having bodies biased by temperature-compensated voltage 失效
标题翻译：具有MOS晶体管的存储器件具有被温度补偿电压偏置的体
公开(公告)号：US5793691A
公开(公告)日：1998-08-11
申请号：US785824
申请日：1997-01-09
申请人： Patrick J. Mullarkey
发明人： Patrick J. Mullarkey
IPC分类号： G11C5/14 , G11C11/4074 , H03K19/0175
CPC分类号： G11C5/146 , G11C11/4074 , G11C5/147
摘要： A memory device includes a plurality of PMOS transistors and a voltage regulator circuit. Each transistor has a gate, a source region, a drain region, and a well containing the source and drain regions. Each transistor is characterized by a threshold voltage which is dependent on temperature and on a body-source bias voltage. Each transistor is also characterized by a sub-threshold current which is dependent on the transistor's threshold voltage. The voltage regulator circuit is operatively coupled to each well to provide the body-source bias voltage to each well. The voltage regulator circuit temperature-compensates the body-source bias voltage to maintain the threshold voltage of each transistor approximately constant despite changes in temperature. The memory device thus advantageously has a relatively constant stand-by current despite temperature variations.
摘要翻译：存储器件包括多个PMOS晶体管和电压调节器电路。每个晶体管具有栅极，源极区，漏极区和包含源极和漏极区的阱。每个晶体管的特征在于取决于温度和体源偏置电压的阈值电压。每个晶体管的特征还在于取决于晶体管阈值电压的次阈值电流。电压调节器电路可操作地耦合到每个阱以向每个阱提供主体偏置电压。电压调节器电路温度补偿体源偏置电压，以保持每个晶体管的阈值电压，尽管温度有变化，但其电压近似恒定。因此，尽管温度变化，存储器件有利地具有相对恒定的备用电流。

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