专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08429470B2 Memory devices, testing systems and methods 有权
标题翻译：内存设备，测试系统和方法
公开(公告)号：US08429470B2
公开(公告)日：2013-04-23
申请号：US12721346
申请日：2010-03-10
申请人： Michael A. Shore
发明人： Michael A. Shore
IPC分类号： G11C29/00
CPC分类号： G11C29/44 , G11C29/36 , G11C29/38 , G11C29/4401 , G11C29/883 , G11C2229/723
摘要： Testing systems and methods, as well as memory devices using such testing systems and methods, may facilitate testing of memory devices using a read-modify-write test procedure. One such testing system receives a signal indicative of at least some of a plurality of bits of data read from an address differing from each other, and then masks subsequent write operations at the same address. Therefore, any address at which the bits of read data do not all have the same value may be considered to be faulty. Failure data from the test can therefore be stored in the same array of memory cells that is being tested.
摘要翻译：使用这种测试系统和方法的测试系统和方法以及存储器件可以使用读 - 修改 - 写测试程序来促进对存储器件的测试。一个这样的测试系统接收指示从彼此不同的地址读取的多个数据位中的至少一些的信号，然后在相同的地址处屏蔽后续的写入操作。因此，读取数据的比特并不都具有相同值的任何地址可能被认为是有缺陷的。因此，来自测试的故障数据可以存储在正在测试的同一阵列的存储单元中。

2. 发明授权

US08427895B2 Systems, memories, and methods for repair in open digit memory architectures 有权
标题翻译：开放式数字存储器架构中的系统，记忆和修复方法
公开(公告)号：US08427895B2
公开(公告)日：2013-04-23
申请号：US13620018
申请日：2012-09-14
申请人： Michael S. Lane , Michael A. Shore
发明人： Michael S. Lane , Michael A. Shore
IPC分类号： G11C7/14 , G11C7/06
CPC分类号： G11C29/04 , G11C7/06 , G11C29/808
摘要： A memory with extra digit lines in full size end arrays with an open digit architecture, which can use the extra digit lines to form repair cells. In one example, folded digit sense amplifiers are connected to an end array with an open digit architecture such that each sense amplifier corresponds to a group of four digit lines. Two digit lines of the group connect to two open digit sense amplifiers and the other two digit lines connect to the corresponding folded digit sense amplifier. A repair method can be performed on memories including the end arrays with folded digit sense amplifiers. A row in a core array including a replaceable IO is activated and a row in an end array is activated. The repair cells in the end array can be sensed by the folded digit sense amplifiers to generate a replacement IO, which is selected rather than the replaceable IO.
摘要翻译：具有开放数字体系结构的全尺寸终端阵列中的额外数字线的存储器，可以使用额外的数字线形成修复单元。在一个示例中，折叠数字读出放大器连接到具有开放数字架构的端部阵列，使得每个读出放大器对应于一组四位数字线。该组的两位数字线连接到两个开放数字读出放大器，另外两个数字线连接到相应的折叠数字读出放大器。可以对包括具有折叠数字读出放大器的端阵列的存储器执行修复方法。激活包含可替换IO的核心阵列中的一行，并激活末端阵列中的一行。结束阵列中的修复单元可以被折叠的数字读出放大器感测以产生替换IO，而不是可更换的IO。

3. 发明授权

US08351285B2 Systems, memories, and methods for repair in open digit memory architectures 有权
标题翻译：开放式数字存储器架构中的系统，记忆和修复方法
公开(公告)号：US08351285B2
公开(公告)日：2013-01-08
申请号：US12497192
申请日：2009-07-02
申请人： Michael S. Lane , Michael A. Shore
发明人： Michael S. Lane , Michael A. Shore
IPC分类号： G11C7/14 , G11C7/06
CPC分类号： G11C29/04 , G11C7/06 , G11C29/808
摘要： Memories, systems, and methods for repairing are provided. A memory with extra digit lines in end arrays with an open digit architecture, which can use the extra digit lines to form repair cells. In one example, folded digit sense amplifiers are connected to an end array with an open digit architecture such that each sense amplifier corresponds to a group of four adjacent digit lines. Two digit lines of the group connect to two open digit sense amplifiers and the other two digit lines connect to the corresponding folded digit sense amplifier. To repair memories including folded digit end arrays, a row in a core array that includes a replaceable IO is activated and a row in an end array is activated. The repair cells in the end array can be sensed by the folded digit sense amplifiers to generate a replacement IO, which is selected rather than the replaceable IO.
摘要翻译：提供了修复的记忆，系统和方法。具有开放数字架构的端阵列中带有额外数字线的存储器，可以使用额外的数字线形成修复单元。在一个示例中，折叠数字读出放大器连接到具有开放数字架构的端阵列，使得每个读出放大器对应于一组四个相邻的数字线。该组的两位数字线连接到两个开放数字读出放大器，另外两个数字线连接到相应的折叠数字读出放大器。要修复包含折叠数字端阵列的内存，激活包含可替换IO的核心阵列中的一行，并激活端阵列中的一行。结束阵列中的修复单元可以被折叠的数字读出放大器感测以产生替换IO，而不是可更换的IO。

4. 发明授权

US06373761B1 Method and apparatus for multiple row activation in memory devices 失效
标题翻译：存储器件中多行激活的方法和装置
公开(公告)号：US06373761B1
公开(公告)日：2002-04-16
申请号：US09654852
申请日：2000-09-05
申请人： Michael A. Shore , Patrick J. Mullarkey
发明人： Michael A. Shore , Patrick J. Mullarkey
IPC分类号： G11C2900
CPC分类号： G11C29/34
摘要： A memory device test circuit and method are described. These operate to maintain a local phase signal active over multiple row activate commands. As a result, an arbitrary number of word lines may be activated together, in an arbitrary order and in arbitrary locations, in response to user-programmable instructions. This allows test sequences to be tailored after the memory device has been designed and can greatly reduce testing times for memory devices.
摘要翻译：描述了存储器件测试电路和方法。这些操作用于通过多个行激活命令维持本地相位信号的活动。结果，响应于用户可编程指令，可以以任意顺序和任意位置一起激活任意数量的字线。这样可以在设计存储器件之后对测试序列进行定制，并可大大减少存储器件的测试时间。

5. 发明授权

US6141276A Apparatus and method for increasing test flexibility of a memory device 有权
公开(公告)号：US6141276A
公开(公告)日：2000-10-31
申请号：US389680
申请日：1999-09-02
申请人： Patrick J. Mullarkey , Michael A. Shore
发明人： Patrick J. Mullarkey , Michael A. Shore
IPC分类号： G11C7/22 , G11C7/00
CPC分类号： G11C7/22
摘要： Operation control circuitry for altering a sequence of internal memory operations in a memory device while in a test mode. The operation control circuitry includes a code circuit for providing an operation code in accordance to a user programmable code. An operation control circuit generates operation control signals in response to receiving command signals from a command circuit included in the operation control circuitry. The operation control signals generated by the operation control circuit control the occurrence of the internal memory operations according to an operation code.

6. 发明授权

US6044029A Device and method for repairing a memory array by storing each bit in multiple memory cells in the array 失效
公开(公告)号：US6044029A
公开(公告)日：2000-03-28
申请号：US15543
申请日：1998-01-29
申请人： Michael A. Shore
发明人： Michael A. Shore
IPC分类号： G11C7/00 , G11C7/10 , G11C8/00 , G11C11/408 , G11C29/00
CPC分类号： G11C8/12 , G11C11/403 , G11C11/4082 , G11C11/4085 , G11C11/4087 , G11C29/74 , G11C29/781 , G11C29/80 , G11C29/88 , G11C7/00 , G11C7/10 , G11C11/401 , G11C2211/4013 , G11C29/783
摘要： A DRAM array is repairable when the array includes memory cells that are defective because their storage capacitors are unable to retain a sufficient electric charge to properly store "1" and "0" bits. To repair the array, both even and odd row decoders in the array are permanently enabled so that each row address the array receives causes the even row decoder to energize at least one even word line and the odd row decoder to energize at least one odd word line. As a result, at least two memory cells are accessed for each row address so that each "1" or "0" bit is stored as an electric charge in at least two memory cells. By grouping enough memory cells together in this manner to store each "1" and "0" bit, the grouped memory cells are able to retain a sufficient total electric charge as a group to properly store each bit even when individual memory cells in the group are unable to do so.

7. 发明授权

US5966334A Device and method for repairing a memory array by storing each bit in multiple memory cells in the array 失效
公开(公告)号：US5966334A
公开(公告)日：1999-10-12
申请号：US015380
申请日：1998-01-29
申请人： Michael A. Shore
发明人： Michael A. Shore
IPC分类号： G11C7/00 , G11C7/10 , G11C8/00 , G11C11/408 , G11C29/00
CPC分类号： G11C8/12 , G11C11/403 , G11C11/4082 , G11C11/4085 , G11C11/4087 , G11C29/74 , G11C29/781 , G11C29/80 , G11C29/88 , G11C7/00 , G11C7/10 , G11C11/401 , G11C2211/4013 , G11C29/783
摘要： A DRAM array is repairable when the array includes memory cells that are defective because their storage capacitors are unable to retain a sufficient electric charge to properly store "1" and "0" bits. To repair the array, both even and odd row decoders in the array are permanently enabled so that each row address the array receives causes the even row decoder to energize at least one even word line and the odd row decoder to energize at least one odd word line. As a result, at least two memory cells are accessed for each row address so that each "1" or "0" bit is stored as an electric charge in at least two memory cells. By grouping enough memory cells together in this manner to store each "1" and "0" bit, the grouped memory cells are able to retain a sufficient total electric charge as a group to properly store each bit even when individual memory cells in the group are unable to do so.

8. 发明授权

US5381368A Hardware implemented row copy enable mode for DRAMS to create repetitive backgrounds for video images or DRAM testing 失效
标题翻译：硬件实现DRAMS的行复制启用模式，为视频图像或DRAM测试创建重复的背景
公开(公告)号：US5381368A
公开(公告)日：1995-01-10
申请号：US165773
申请日：1993-12-10
申请人： Donald M. Morgan , Michael A. Shore
发明人： Donald M. Morgan , Michael A. Shore
IPC分类号： G11C7/10 , G11C11/4096 , G11C29/34 , G11C11/40
CPC分类号： G11C7/1006 , G11C11/4096 , G11C29/34
摘要： There is a hardware implemented row copy operation mode for a DRAM to relieve the VRAMs from this slower repetitive operation. In addition, by providing circuitry that will generate a solid repetitive pattern for the full or portions of the screen. Another advantage of the invention occurs during testing of a DRAM with this circuitry. By having the ability of filling the memory array with, for example all digital ones in each cell, the quality of the die can easily be tested by modifying individual cells with a digital zero. Uniquely, this circuitry relieves the testing circuitry from filling in a background of information like the all ones background. Another feature of the invention allows graphic cards that exclusively use DRAMs, to eliminate the additional circuitry needed to perform the row copy feature, or creation of backgrounds.
摘要翻译：存在用于DRAM的硬件实现的行复制操作模式以从该较慢的重复操作中减轻VRAM。此外，通过提供将为屏幕的全部或部分产生固体重复图案的电路。本发明的另一个优点是在利用该电路测试DRAM期间发生。通过具有用例如每个单元中的所有数字填充存储器阵列的能力，可以通过用数字零修改单个单元来容易地测试管芯的质量。独一无二的是，该电路可以使测试电路免于填充所有信息的背景。本发明的另一个特征是允许独特地使用DRAM的图形卡来消除执行行复制特征所需的附加电路或背景的创建。

9. 发明授权

US06701470B1 Method for testing a memory device having different number of data pads than the tester 失效
标题翻译：用于测试具有与测试器不同数量的数据焊盘数量的存储器件的方法
公开(公告)号：US06701470B1
公开(公告)日：2004-03-02
申请号：US09649829
申请日：2000-08-29
申请人： Patrick J. Mullarkey , Michael A. Shore
发明人： Patrick J. Mullarkey , Michael A. Shore
IPC分类号： G11C2900
CPC分类号： G11C29/1201 , G11C29/48
摘要： Testing a memory device having M data pads with a tester having N
摘要翻译：用具有N

10. 发明授权

US06442094B2 Device and method for repairing a memory array by storing each bit in multiple memory cells in the array 有权
标题翻译：通过将每个位存储在阵列中的多个存储单元中来修复存储器阵列的装置和方法
公开(公告)号：US06442094B2
公开(公告)日：2002-08-27
申请号：US09886762
申请日：2001-06-21
申请人： Michael A. Shore
发明人： Michael A. Shore
IPC分类号： G11C700
CPC分类号： G11C8/12 , G11C7/00 , G11C7/10 , G11C11/401 , G11C11/403 , G11C11/4082 , G11C11/4085 , G11C11/4087 , G11C29/74 , G11C29/781 , G11C29/783 , G11C29/80 , G11C29/88 , G11C2211/4013
摘要： A DRAM array is repairable when the array includes memory cells that are defective because their storage capacitors are unable to retain a sufficient electric charge to properly store “1” and “0” bits. To repair the array, both even and odd row decoders in the array are permanently enabled so that each row address the array receives causes the even row decoder to energize at least one even word line and the odd row decoder to energize at least one odd word line. As a result, at least two memory cells are accessed for each row address so that each “1” or “0” bit is stored as an electric charge in at least two memory cells. By grouping enough memory cells together in this manner to store each “1” and “0” bit, the grouped memory cells are able to retain a sufficient total electric charge as a group to properly store each bit even when individual memory cells in the group are unable to do so.
摘要翻译：当阵列包括有缺陷的存储器单元时，可以修复DRAM阵列，因为它们的存储电容器不能保持足够的电荷以正确地存储“1”和“0”位。为了修复阵列，阵列中的偶数行解码器和奇数行解码器被永久地启用，使得阵列接收的每个行地址使得偶数行解码器激励至少一个偶数字线，而奇数行解码器激励至少一个奇数字线。结果，对于每个行地址访问至少两个存储单元，使得每个“1”或“0”位作为电荷存储在至少两个存储单元中。通过以这种方式将足够的存储器单元分组在一起以存储每个“1”和“0”位，分组的存储器单元能够保持足够的总电荷作为组，以适当地存储每个位，即使组中的各个存储单元不能这样做

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式