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1. 发明授权

US08609492B2 Vertical memory cell 有权
标题翻译：垂直存储单元
公开(公告)号：US08609492B2
公开(公告)日：2013-12-17
申请号：US13192207
申请日：2011-07-27
申请人： Kurt D. Beigel , Sanh D. Tang
发明人： Kurt D. Beigel , Sanh D. Tang
IPC分类号： H01L21/336
CPC分类号： H01L29/0638 , H01L27/1027 , H01L27/10802 , H01L29/0688 , H01L29/7841 , H01L29/78642 , H01L29/7889
摘要： Methods of forming, devices, and apparatus associated with a vertical memory cell are provided. One example method of forming a vertical memory cell can include forming a semiconductor structure over a conductor line. The semiconductor structure can have a first region that includes a first junction between first and second doped materials. An etch-protective material is formed on a first pair of sidewalls of the semiconductor structure above the first region. A volume of the first region is reduced relative to a body region of the semiconductor structure in a first dimension.
摘要翻译：提供了形成装置的方法以及与垂直存储单元相关联的装置。形成垂直存储单元的一个示例性方法可以包括在导体线上形成半导体结构。半导体结构可以具有包括第一和第二掺杂材料之间的第一结的第一区域。在第一区域上方的半导体结构的第一对侧壁上形成蚀刻保护材料。第一区域的体积相对于半导体结构的体区在第一维度上减小。

2. 发明授权

US08035160B2 Recessed access device for a memory 有权
标题翻译：嵌入式存储设备
公开(公告)号：US08035160B2
公开(公告)日：2011-10-11
申请号：US12627869
申请日：2009-11-30
申请人： Kurt D. Beigel , Jigish D. Trivedi , Kevin G. Duesman
发明人： Kurt D. Beigel , Jigish D. Trivedi , Kevin G. Duesman
IPC分类号： H01L29/66
CPC分类号： H01L29/66621 , H01L27/10876
摘要： Semiconductor memory devices having recessed access devices are disclosed. In some embodiments, a method of forming the recessed access device includes forming a device recess in a substrate material that extends to a first depth in the substrate that includes a gate oxide layer in the recess. The device recess may be extended to a second depth that is greater that the first depth to form an extended portion of the device recess. A field oxide layer may be provided within an interior of the device recess that extends inwardly into the interior of the device recess and into the substrate. Active regions may be formed in the substrate that abut the field oxide layer, and a gate material may be deposited into the device recess.
摘要翻译：公开了具有凹入式存取装置的半导体存储器件。在一些实施例中，形成凹陷进入装置的方法包括在衬底材料中形成器件凹部，该衬底材料延伸到衬底中的第一深度，该第一深度包括凹陷中的栅极氧化物层。装置凹部可以延伸到大于第一深度的第二深度，以形成装置凹部的延伸部分。场氧化物层可以设置在器件凹部的内部，其内部延伸到器件凹部的内部并进入衬底。活性区域可以形成在衬底中，其邻接场氧化物层，并且栅极材料可以沉积到器件凹部中。

3. 发明申请

US20100072532A1 Recessed Access Device For A Memory 有权
标题翻译：嵌入式存储设备
公开(公告)号：US20100072532A1
公开(公告)日：2010-03-25
申请号：US12627869
申请日：2009-11-30
申请人： Kurt D. Beigel , Jigish D. Trivedi , Kevin G. Duesman
发明人： Kurt D. Beigel , Jigish D. Trivedi , Kevin G. Duesman
IPC分类号： H01L27/108 , H01L27/105
CPC分类号： H01L29/66621 , H01L27/10876
摘要： Semiconductor memory devices having recessed access devices are disclosed. In some embodiments, a method of forming the recessed access device includes forming a device recess in a substrate material that extends to a first depth in the substrate that includes a gate oxide layer in the recess. The device recess may be extended to a second depth that is greater that the first depth to form an extended portion of the device recess. A field oxide layer may be provided within an interior of the device recess that extends inwardly into the interior of the device recess and into the substrate. Active regions may be formed in the substrate that abut the field oxide layer, and a gate material may be deposited into the device recess.
摘要翻译：公开了具有凹入式存取装置的半导体存储器件。在一些实施例中，形成凹陷进入装置的方法包括在衬底材料中形成器件凹部，该衬底材料延伸到衬底中的第一深度，该第一深度包括凹陷中的栅极氧化物层。装置凹部可以延伸到大于第一深度的第二深度，以形成装置凹部的延伸部分。场氧化物层可以设置在器件凹部的内部，其内部延伸到器件凹部的内部并进入衬底。活性区域可以形成在衬底中，其邻接场氧化物层，并且栅极材料可以沉积到器件凹部中。

4. 发明授权

US07674683B2 Bulk-isolated PN diode and method of forming a bulk-isolated PN diode 失效
标题翻译：大容量隔离PN二极管和形成大容量隔离PN二极管的方法
公开(公告)号：US07674683B2
公开(公告)日：2010-03-09
申请号：US12111014
申请日：2008-04-28
申请人： Kurt D. Beigel
发明人： Kurt D. Beigel
IPC分类号： H01L21/04 , H01L21/761
CPC分类号： H01L27/0814 , H01L27/0629 , H01L29/417 , H01L29/861
摘要： A technique for making a bulk isolated PN diode is disclosed. In one embodiment, a method may include providing a substrate having a doped region and disposing a dielectric material over the doped region. The method may also include forming first and second holes in the dielectric material exposing the doped region, and forming respective first and second polysilicon plugs within the first and second holes over the doped region. In one embodiment, the first and second polysilicon plugs are doped opposite one another such that a PN junction is formed between the first or second polysilicon plug and the doped region of the substrate, and has a cross-sectional area generally defined by the first or second hole adjacent the PN junction. Various devices, systems, and other methods are also disclosed.
摘要翻译：公开了一种制造大容量隔离PN二极管的技术。在一个实施例中，方法可以包括提供具有掺杂区域的衬底并且在掺杂区域上设置电介质材料。该方法还可以包括在暴露掺杂区域的电介质材料中形成第一和第二孔，以及在掺杂区域上的第一和第二孔内形成相应的第一和第二多晶硅栓塞。在一个实施例中，第一和第二多晶硅插塞彼此相对掺杂，使得PN结形成在第一或第二多晶硅插塞与衬底的掺杂区域之间，并且具有通常由第一或第二多晶硅邻近PN结的第二个孔。还公开了各种装置，系统和其它方法。

5. 发明授权

US07645671B2 Recessed access device for a memory 有权
标题翻译：嵌入式存储设备
公开(公告)号：US07645671B2
公开(公告)日：2010-01-12
申请号：US11598449
申请日：2006-11-13
申请人： Kurt D. Beigel , Jigish D. Trivedi , Kevin G. Duesman
发明人： Kurt D. Beigel , Jigish D. Trivedi , Kevin G. Duesman
IPC分类号： H01L21/336
CPC分类号： H01L29/66621 , H01L27/10876
摘要： Semiconductor memory devices having recessed access devices are disclosed. In some embodiments, a method of forming the recessed access device includes forming a device recess in a substrate material that extends to a first depth in the substrate that includes a gate oxide layer in the recess. The device recess may be extended to a second depth that is greater that the first depth to form an extended portion of the device recess. A field oxide layer may be provided within an interior of the device recess that extends inwardly into the interior of the device recess and into the substrate. Active regions may be formed in the substrate that abut the field oxide layer, and a gate material may be deposited into the device recess.
摘要翻译：公开了具有凹入式存取装置的半导体存储器件。在一些实施例中，形成凹陷进入装置的方法包括在衬底材料中形成器件凹部，该衬底材料延伸到衬底中的第一深度，该第一深度包括凹陷中的栅极氧化物层。装置凹部可以延伸到大于第一深度的第二深度，以形成装置凹部的延伸部分。场氧化物层可以设置在器件凹部的内部，其内部延伸到器件凹部的内部并进入衬底。活性区域可以形成在衬底中，其邻接场氧化物层，并且栅极材料可以沉积到器件凹部中。

6. 发明授权

US07442600B2 Methods of forming threshold voltage implant regions 失效
标题翻译：形成阈值电压注入区域的方法
公开(公告)号：US07442600B2
公开(公告)日：2008-10-28
申请号：US10925736
申请日：2004-08-24
申请人： Hongmei Wang , Kurt D. Beigel , Fred D. Fishburn , Rongsheng Yang
发明人： Hongmei Wang , Kurt D. Beigel , Fred D. Fishburn , Rongsheng Yang
IPC分类号： H01L21/8238
CPC分类号： H01L21/26513 , H01L21/324 , H01L21/823412 , H01L27/0811 , H01L27/088 , H01L29/66537 , H01L29/7833
摘要： The invention includes methods of forming channel region implants for two transistor devices simultaneously, in which a mask is utilized to block a larger percentage of a channel region location of one of the devices relative to the other. The invention also pertains to methods of forming capacitor structures in which a first capacitor electrode is spaced from a semiconductor substrate by a dielectric material, a second capacitor electrode comprises a conductively-doped diffusion region within the semiconductor material, and a capacitor channel region location is beneath the dielectric material and adjacent the conductively-doped diffusion region. An implant mask is formed to cover only a first portion of the capacitor channel region location and to leave a second portion of the capacitor channel region location uncovered. While the implant mask is in place, dopant is implanted into the uncovered second portion of the capacitor channel region location.
摘要翻译：本发明包括同时形成两个晶体管器件的沟道区域植入物的方法，其中掩模用于阻挡相对于另一个器件之一的较大百分比的沟道区域位置。本发明还涉及形成电容器结构的方法，其中第一电容器电极通过电介质材料与半导体衬底隔开，第二电容器电极包括半导体材料内的导电掺杂扩散区，电容器通道区位置为在介电材料的下方并与导电掺杂的扩散区相邻。形成注入掩模以仅覆盖电容器沟道区位置的第一部分并且留下未覆盖的电容器沟道区位置的第二部分。当植入掩模就位时，掺杂剂被注入到电容器通道区域位置的未覆盖的第二部分中。

7. 发明授权

US07384840B2 Bulk-isolated PN diode and method of forming a bulk-isolated PN diode 有权
公开(公告)号：US07384840B2
公开(公告)日：2008-06-10
申请号：US10930512
申请日：2004-08-31
申请人： Kurt D. Beigel
发明人： Kurt D. Beigel
IPC分类号： H01L21/8234
CPC分类号： H01L27/0814 , H01L27/0629 , H01L29/417 , H01L29/861
摘要： A technique for making a bulk isolated PN diode. Specifically, a technique is provided for making a voltage clamp with a pair of bulk isolated PN diode. Another embodiment provides for a voltage clamp with a pair of bulk isolated PN diodes in parallel with a pair of MOSFET diode-connected transistors. In addition, a method for manufacturing the bulk isolated PN diodes is recited.

8. 发明申请

US20080113478A1 Recessed access device for a memory 有权
标题翻译：嵌入式存储设备
公开(公告)号：US20080113478A1
公开(公告)日：2008-05-15
申请号：US11598449
申请日：2006-11-13
申请人： Kurt D. Beigel , Jigish D. Trivedi , Kevin G. Duesman
发明人： Kurt D. Beigel , Jigish D. Trivedi , Kevin G. Duesman
IPC分类号： H01L21/8242
CPC分类号： H01L29/66621 , H01L27/10876
摘要： Semiconductor memory devices having recessed access devices are disclosed. In some embodiments, a method of forming the recessed access device includes forming a device recess in a substrate material that extends to a first depth in the substrate that includes a gate oxide layer in the recess. The device recess may be extended to a second depth that is greater that the first depth to form an extended portion of the device recess. A field oxide layer may be provided within an interior of the device recess that extends inwardly into the interior of the device recess and into the substrate. Active regions may be formed in the substrate that abut the field oxide layer, and a gate material may be deposited into the device recess.
摘要翻译：公开了具有凹入式存取装置的半导体存储器件。在一些实施例中，形成凹陷进入装置的方法包括在衬底材料中形成器件凹部，该衬底材料延伸到衬底中的第一深度，该第一深度包括凹陷中的栅极氧化物层。装置凹部可以延伸到大于第一深度的第二深度，以形成装置凹部的延伸部分。场氧化物层可以设置在器件凹部的内部，其内部延伸到器件凹部的内部并进入衬底。活性区域可以形成在衬底中，其邻接场氧化物层，并且栅极材料可以沉积到器件凹部中。

9. 发明授权

US06778452B2 Circuit and method for voltage regulation in a semiconductor device 失效
公开(公告)号：US06778452B2
公开(公告)日：2004-08-17
申请号：US10608060
申请日：2003-06-27
申请人： Kurt D. Beigel , Douglas J. Cutter , Manny K. Ma , Gordon D. Roberts , James E. Miller , Daryl L. Habersetzer , Jeffrey D. Bruce , Eric T. Stubbs
发明人： Kurt D. Beigel , Douglas J. Cutter , Manny K. Ma , Gordon D. Roberts , James E. Miller , Daryl L. Habersetzer , Jeffrey D. Bruce , Eric T. Stubbs
IPC分类号： G11C700
CPC分类号： G11C29/026 , G11C11/401 , G11C29/02 , G11C29/025 , G11C29/028 , G11C29/12 , G11C29/44 , G11C29/48 , G11C29/50 , G11C29/50012 , G11C29/56 , G11C2029/5004
摘要： As part of a memory array, a circuit is provided for altering the drive applied to an access transistor that regulates electrical communication within the memory array. In one embodiment, the circuit is used to alter the drive applied to a sense amp's voltage-pulling transistor, thereby allowing modification of the voltage-pulling rate for components of the sense amp. A sample of test data is written to the memory array and read several times at varying drive rates in order to determine the sense amp's ability to accommodate external circuitry. In another embodiment, the circuit is used to alter the drive applied to a bleeder device that regulates communication between the digit lines of the memory array and its cell plate. Slowing said communication allows defects within the memory array to have a more pronounced effect and hence increases the chances of finding such defects during testing. The circuit is configured to accept and apply a plurality of voltages, either through a contact pad or from a series of discrete voltage sources coupled to the circuit.

10. 发明授权

US06525399B2 Junctionless antifuses and systems containing junctionless antifuses 有权
公开(公告)号：US06525399B2
公开(公告)日：2003-02-25
申请号：US09990022
申请日：2001-11-21
申请人： Douglas J. Cutter , Fan Ho , Kurt D. Beigel
发明人： Douglas J. Cutter , Fan Ho , Kurt D. Beigel
IPC分类号： H01L2900
CPC分类号： H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： A method and apparatus for forming a junctionless antifuse semiconductor structure comprises forming an antifuse in non-active areas of a semiconductor wafer. In one embodiment, the antifuse is formed over a polysilicon layer, which is coupled to a field oxide layer. In a further embodiment, the polysilicon layer comprises a bottom conductor layer in the antifuse. In another embodiment, a refractory metal silicide layer is formed between the polysilicon layer and the antifuse. In yet a further embodiment, the refractory metal silicide layer comprises the bottom conductor layer in the antifuse.

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