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61. 发明授权

US07538579B1 Omnibus logic element 有权
标题翻译：综合逻辑元素
公开(公告)号：US07538579B1
公开(公告)日：2009-05-26
申请号：US11607171
申请日：2006-12-01
申请人： James Schleicher , Richard Yuan , Bruce Pedersen , Sinan Kaptanoglu , Gregg Baeckler , David Lewis , Mike Hutton , Andy Lee , Rahul Saini , Henry Kim
发明人： James Schleicher , Richard Yuan , Bruce Pedersen , Sinan Kaptanoglu , Gregg Baeckler , David Lewis , Mike Hutton , Andy Lee , Rahul Saini , Henry Kim
IPC分类号： H03K19/177
CPC分类号： H03K19/17728 , G06F7/50 , H03K19/017581
摘要： Disclosed is an LE that can provide a number of advantageous features. For example, the LE can provide efficient and flexible use of LUTs and input sharing. The LE may also provide for flexible use of one or more dedicated adders and include register functionality.
摘要翻译：公开了可以提供许多有利特征的LE。例如，LE可以提供LUT和输入共享的高效灵活的使用。 LE还可以灵活地使用一个或多个专用加法器并且包括寄存器功能。

62. 发明授权

US07432734B2 Versatile logic element and logic array block 有权
公开(公告)号：US07432734B2
公开(公告)日：2008-10-07
申请号：US11743625
申请日：2007-05-02
申请人： David M. Lewis , Paul Leventis , Andy L. Lee , Henry Kim , Bruce Pedersen , Chris Wysocki , Christopher F. Lane , Alexander Marquardt , Vikram Santurkar , Vaughn Betz
发明人： David M. Lewis , Paul Leventis , Andy L. Lee , Henry Kim , Bruce Pedersen , Chris Wysocki , Christopher F. Lane , Alexander Marquardt , Vikram Santurkar , Vaughn Betz
IPC分类号： H01L25/00 , H03K19/177
CPC分类号： H03K19/17764 , H03K19/1737 , H03K19/17728 , H03K19/17736
摘要： An embodiment of this invention pertains to a versatile and flexible logic element and logic array block (“LAB”). Each logic element includes a programmable combinational logic function block such as a lookup table (“LUT”) and a flip-flop. Within the logic element, multiplexers are provided to allow the flip-flop and the LUT to be programmably connected such that either the output of the LUT may be connected to the input of the flip-flop or the output of the flip-flop may be connected to the input of the LUT. An additional multiplexer allows the output of the flip-flop in one logic element to be connected to the input of a flip-flop in a different logic element within the same LAB. Output multiplexers selects between the output of the LUT and the output of the flip-flop to generate signals that drive routing lines within the LAB and to routing lines external to the LAB. These output multiplexers are constructed such that the combinational output (output from the LUT) is faster than the output from the flip-flop. A collection of routing lines and multiplexers within the LAB are used to provide inputs to the LUTs. Each of the input multiplexers for each logic element is connected to a subset of the routing lines within the LAB using a specific pattern of connectivity of multiplexers to associated wires that maximizes the efficiency of use of the routing wires. Control signals for the set of logic elements within the LAB are generated using a secondary signal generation unit that minimizes contention for shared signals. One of the control signals is an “add-or-subtract control signal” that allows all of the LEs in a LAB to perform either addition or subtraction under the control of a logic signal. In a PLD supporting redundancy, the carry chain for the LABs is arranged in the same direction that redundancy shifts to remap defective LABs and a multiplexer on the carry input of a LAB is used to select the appropriate carry output from another LAB depending on whether redundancy is engaged.

63. 发明授权

US07406668B1 Methods for producing mappings of logic suitable for FPGA and structured ASIC implementations 失效
标题翻译：用于生成适用于FPGA和结构化ASIC实现的逻辑映射的方法
公开(公告)号：US07406668B1
公开(公告)日：2008-07-29
申请号：US11072560
申请日：2005-03-03
申请人： Bruce Pedersen , Jinyong Yuan
发明人： Bruce Pedersen , Jinyong Yuan
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： Implementation of a logic design in either an FPGA or a structured ASIC is facilitated by designing either type of implementation so that it takes into account the possible need to migrate the design to the other type of implementation. Portions of the design that are being considered for one type of implementation (e.g., FPGA implementation) are assessed for suitability and/or desirability based not only on their suitability/desirability in that one type of implementation, but also based on their suitability/desirability in the other type of implementation (e.g., structured ASIC implementation).
摘要翻译：通过设计任何一种实现方式来实现FPGA或结构化ASIC中的逻辑设计，从而考虑到可能需要将设计迁移到其他类型的实现。根据其适用性/适用性，还可以根据其适用性/可取性评估正在考虑用于一种类型实现的部分（例如，FPGA实现）的适用性和/或可取性。在其他类型的实现（例如，结构化ASIC实现）中。

64. 发明授权

US07312632B2 Fracturable lookup table and logic element 有权
标题翻译：可破坏的查找表和逻辑元素
公开(公告)号：US07312632B2
公开(公告)日：2007-12-25
申请号：US11753048
申请日：2007-05-24
申请人： David Lewis , Bruce Pedersen , Sinan Kaptanoglu , Andy Lee
发明人： David Lewis , Bruce Pedersen , Sinan Kaptanoglu , Andy Lee
IPC分类号： H03K19/173
CPC分类号： H03K19/17728 , H03K19/1737
摘要： A logic element includes memory elements, multiplexers, and controls. The multiplexers are arranged in levels including a highest level of multiplexers with inputs connected to the memory elements and outputs connected to inputs of a next-to-highest level of multiplexers and a first level of multiplexers with inputs connected to outputs of a second level of multiplexers and at least one output. The controls are connected to the multiplexers. In a first operational mode the controls determine a first-mode output at the at least one output of the first level of multiplexers, and in a second operational mode the controls determine a plurality of second-mode outputs at selected outputs of multiplexers not at the first level of multiplexers.
摘要翻译：逻辑元件包括存储器元件，多路复用器和控制器。多路复用器被布置在包括最高级别的多路复用器的级别中，其中连接到存储器元件的输入端和连接到下一级到最高级复用器的输出的输出端和第一级多路复用器，其输入端连接到第二级多路复用器和至少一个输出。控制器连接到多路复用器。在第一操作模式中，所述控制确定所述第一级多路复用器的所述至少一个输出处的第一模式输出，并且在第二操作模式中，所述控制确定多路复用器的选定输出处的多个第二模式输出，第一级多路复用器。

65. 发明申请

US20070252617A1 VERSATILE LOGIC ELEMENT AND LOGIC ARRAY BLOCK 有权
公开(公告)号：US20070252617A1
公开(公告)日：2007-11-01
申请号：US11743625
申请日：2007-05-02
申请人： David Lewis , Paul Leventis , Andy Lee , Henry Kim , Bruce Pedersen , Chris Wysocki , Christopher Lane , ALexander Marquardt , Vikram Santurkar , Vaughn Betz
发明人： David Lewis , Paul Leventis , Andy Lee , Henry Kim , Bruce Pedersen , Chris Wysocki , Christopher Lane , ALexander Marquardt , Vikram Santurkar , Vaughn Betz
IPC分类号： H03K19/177
CPC分类号： H03K19/17764 , H03K19/1737 , H03K19/17728 , H03K19/17736
摘要： An embodiment of this invention pertains to a versatile and flexible logic element and logic array block (“LAB”). Each logic element includes a programmable combinational logic function block such as a lookup table (“LUT”) and a flip-flop. Within the logic element, multiplexers are provided to allow the flip-flop and the LUT to be programmably connected such that either the output of the LUT may be connected to the input of the flip-flop or the output of the flip-flop may be connected to the input of the LUT. An additional multiplexer allows the output of the flip-flop in one logic element to be connected to the input of a flip-flop in a different logic element within the same LAB. Output multiplexers selects between the output of the LUT and the output of the flip-flop to generate signals that drive routing lines within the LAB and to routing lines external to the LAB. These output multiplexers are constructed such that the combinational output (output from the LUT) is faster than the output from the flip-flop. A collection of routing lines and multiplexers within the LAB are used to provide inputs to the LUTs. Each of the input multiplexers for each logic element is connected to a subset of the routing lines within the LAB using a specific pattern of connectivity of multiplexers to associated wires that maximizes the efficiency of use of the routing wires. Control signals for the set of logic elements within the LAB are generated using a secondary signal generation unit that minimizes contention for shared signals. One of the control signals is an “add-or-subtract control signal” that allows all of the LEs in a LAB to perform either addition or subtraction under the control of a logic signal. In a PLD supporting redundancy, the carry chain for the LABs is arranged in the same direction that redundancy shifts to remap defective LABs and a multiplexer on the carry input of a LAB is used to select the appropriate carry output from another LAB depending on whether redundancy is engaged.

66. 发明申请

US20070222477A1 FRACTURABLE LOOKUP TABLE AND LOGIC ELEMENT 有权
标题翻译：可折叠的表和逻辑元件
公开(公告)号：US20070222477A1
公开(公告)日：2007-09-27
申请号：US11753048
申请日：2007-05-24
申请人： David Lewis , Bruce Pedersen , Sinan Kaptanoglu , Andy Lee
发明人： David Lewis , Bruce Pedersen , Sinan Kaptanoglu , Andy Lee
IPC分类号： H03K19/177
CPC分类号： H03K19/17728 , H03K19/1737
摘要： A logic element includes memory elements, multiplexers, and controls. The multiplexers are arranged in levels including a highest level of multiplexes with inputs connected to the memory elements and outputs connected to inputs of a next-to-highest level of multiplexers and a first level of multiplexers with inputs connected to outputs of a second level of multiplexers and at least one output. The controls are connected to the multiplexers. In a first operational mode the controls determine a first-mode output at the at least one output of the first level of multiplexers, and in a second operational mode the controls determine a plurality of second-mode outputs at selected outputs of multiplexers not at the first level of multiplexers.
摘要翻译：逻辑元件包括存储器元件，多路复用器和控制器。多路复用器被布置成包括具有连接到存储器元件的输入的最高级复用的输出和连接到下一个到最高级多路复用器的输出的输出以及具有连接到第二级的多路复用器的输出的第一级多路复用器多路复用器和至少一个输出。控制器连接到多路复用器。在第一操作模式中，所述控制确定所述第一级多路复用器的所述至少一个输出处的第一模式输出，并且在第二操作模式中，所述控制确定多路复用器的选定输出处的多个第二模式输出，第一级多路复用器。

67. 发明授权

US07253660B1 Multiplexing device including a hardwired multiplexer in a programmable logic device 有权
标题翻译：多路复用器件包括可编程逻辑器件中的硬连线多路复用器
公开(公告)号：US07253660B1
公开(公告)日：2007-08-07
申请号：US10305886
申请日：2002-11-27
申请人： Paul Leventis , Bruce Pedersen , Chris Lane , Srinivas Reddy , David Lewis
发明人： Paul Leventis , Bruce Pedersen , Chris Lane , Srinivas Reddy , David Lewis
IPC分类号： H01L25/00 , H03K19/177
CPC分类号： H03K17/002
摘要： A multiplexing device is described. In one embodiment, the multiplexing device includes: a hardwired multiplexer including a plurality of input terminals; a plurality of select terminals; and at least one output terminal, where the plurality of input terminals are coupled to a plurality of block input lines or a plurality of functional element input terminals. In one embodiment, the plurality of input terminals are hardwired to the plurality of block input lines or the plurality of functional element input terminals. In one embodiment, the plurality of select terminals are coupled to a second plurality of functional element input terminals or a plurality of functional element output terminals. In one embodiment, the plurality of block input lines include a plurality of logic array block (LAB) lines, the plurality of functional element input terminals include a plurality of logic element (LE) input terminals, and the plurality of functional element output terminals include LE output terminals. In another embodiment the multiplexing device includes: a hardwired multiplexer including a plurality of data signal input terminals; and a first plurality of LEs including a first plurality of LE output terminals, where the plurality of data signal input terminals are coupled to the first plurality of LE output terminals.
摘要翻译：描述多路复用装置。在一个实施例中，多路复用装置包括：硬连线多路复用器，包括多个输入端; 多个选择端子; 以及至少一个输出端子，其中多个输入端子耦合到多个块输入线或多个功能元件输入端子。在一个实施例中，多个输入端子被硬连线到多个块输入线或多个功能元件输入端子。在一个实施例中，多个选择端子耦合到第二多个功能元件输入端子或多个功能元件输出端子。在一个实施例中，多个块输入线包括多个逻辑阵列块（LAB）线，多个功能元件输入端包括多个逻辑元件（LE）输入端，多个功能元件输出端包括 LE输出端子。在另一实施例中，多路复用装置包括：硬连线多路复用器，包括多个数据信号输入端; 以及包括第一多个LE输出端子的第一多个LE，其中所述多个数据信号输入端子耦合到所述第一多个LE输出端子。

68. 发明授权

US07249339B1 Method and apparatus for optimizing delay paths through field programmable gate arrays 有权
标题翻译：用于通过现场可编程门阵列优化延迟路径的方法和装置
公开(公告)号：US07249339B1
公开(公告)日：2007-07-24
申请号：US10918974
申请日：2004-08-16
申请人： Bruce Pedersen
发明人： Bruce Pedersen
IPC分类号： G06F17/50
CPC分类号： G06F17/5054 , G06F17/5031
摘要： A method for improving a design on a field programmable gate array (FPGA) includes modifying the design in response to a unate characteristic of an input to a node on the FPGA, and rising and falling delays of a node feeding the input.
摘要翻译：用于改进现场可编程门阵列（FPGA）设计的方法包括响应于FPGA上的节点的输入的单一特性以及馈送输入的节点的上升和下降延迟来修改设计。

69. 发明授权

US07129745B2 Apparatus and methods for adjusting performance of integrated circuits 有权
公开(公告)号：US07129745B2
公开(公告)日：2006-10-31
申请号：US10865402
申请日：2004-06-10
申请人： David Lewis , Vaughn Betz , Irfan Rahim , Peter McElheny , Yow-Juang W. Liu , Bruce Pedersen
发明人： David Lewis , Vaughn Betz , Irfan Rahim , Peter McElheny , Yow-Juang W. Liu , Bruce Pedersen
IPC分类号： H03K19/173
CPC分类号： G06F17/5054 , H03K5/133 , H03K19/00369 , H03K2005/00058 , H03K2005/00156 , H03K2217/0018
摘要： A programmable logic device (PLD) includes a delay circuit and a body-bias generator. The delay circuit has a delay configured to represent a delay of user circuit implement in the PLD. The body-bias generator is configured to adjust the body bias of a transistor within the user circuit. The body-bias generator adjusts the body bias of the transistor in response to a level derived from the signal propagation delay of the delay circuit.

70. 发明授权

US07100141B1 Technology mapping technique for fracturable logic elements 有权
$Technology mapping technique for fracturable logic elements$
标题翻译：可分割逻辑元件的技术映射技术
公开(公告)号：US07100141B1
公开(公告)日：2006-08-29
申请号：US10745913
申请日：2003-12-23
申请人： Boris Ratchev , Yean-Yow Hwang , Bruce Pedersen
发明人： Boris Ratchev , Yean-Yow Hwang , Bruce Pedersen
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： A technique of minimizes circuit area on programmable logic with fracturable logic elements by using “balancing” in the technology mapping stage of the programmable logic computer-aided-design flow. A fracturable LE can be used for logic implementation in many ways, such as being used as one maximum-sized look-up table (LUT) or multiple smaller LUTs. One of more inputs of the multiple smaller LUTs may be shared. By balancing, this means mean that the technology mapping algorithm is tuned to use more small LUTs and fewer maximum-sized LUTs to implement the circuit. Although this is counterintuitive since the larger LUTs are more effective at absorbing gates, the technique achieves a smaller final circuit area by packing small LUTs into fracturable LEs.
摘要翻译：通过在可编程逻辑计算机辅助设计流程的技术映射阶段中使用“平衡”来最小化具有可分解逻辑元件的可编程逻辑电路面积的技术。可破碎的LE可以用于许多方式的逻辑实现，例如用作一个最大尺寸的查找表（LUT）或多个较小的LUT。可以共享多个较小LUT的更多输入中的一个。通过平衡，这意味着技术映射算法被调整为使用更小的LUT和更少的最大尺寸的LUT来实现电路。虽然这是违反直觉的，因为较大的LUT在吸收栅极方面更有效，但是该技术通过将小型LUT封装成可分裂的LE来实现较小的最终电路面积。

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